UM10398 LPC1111 LPC1112 LPC1113 LPC1114 LPC11C12 LPC11C14 LPC1100 LPC1100L - Datasheet Archive

 

LPC111x/LPC11C1x User manual Rev. 2 - 2 November 2010 User manual Document information Info Content Keywords ARM Cortex-M0,

 

UM10398 UM10398 LPC111x/LPC11C1x User manual Rev. 2 - 2 November 2010 User manual Document information Info Content Keywords ARM Cortex-M0, LPC1111 LPC1111, LPC1112 LPC1112, LPC1113 LPC1113, LPC1114 LPC1114, LPC11C12 LPC11C12, LPC11C14 LPC11C14, LPC1100 LPC1100, LPC1100L LPC1100L, LPC11C00 LPC11C00 Abstract LPC111x/LPC11C1x User manual UM10398 UM10398 NXP Semiconductors LPC111x/LPC11C1x UM Revision history Rev Date 2 20101102 Modifications: Description LPC111x/LPC11C1x User manual Parts LPC111x/102/202/302 (LPC1100L LPC1100L series) added (Table 1, Table 277). · 1 · · · · · · · · · · Sections clocking and power control removed and content combined with section basic configuration for each chapter. PLL output frequency updated (< 100 MHz) in Section 3.10 "System PLL functional description". Description of Deep-sleep and Deep-power down modes updated in Section 3.8 "Power management". Chapter 5 "LPC111x/102/202/302 Power profiles" added. WDT changed to 24-bit timer in Chapter 17 "LPC111x/LPC11C1x WatchDog Timer (WDT)". Connection to standard debug connector explained in Section 21.6.2 "Debug connections". Register SYSTCKCAL moved to location 0x4004 8154 (Table 6 and Table 33). Flash signature generation added (Section 20.10 "Flash signature generation"). Baudrates for ISP restricted (230400 bps removed) in Section 20.5 "UART ISP commands". Flash write disturbance effect described in Section 20.5.7 "Copy RAM to flash (UART ISP)". 20100721 LPC111x/LPC11C1x User manual Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com UM10398 UM10398 User manual All information provided in this document is subject to legal disclaimers. Rev. 2 - 2 November 2010 © NXP B.V. 2010. All rights reserved. 2 of 407 UM10398 UM10398 Chapter 1: LPC111x/LPC11C1x Introductory information Rev. 2 - 2 November 2010 User manual 1.1 Introduction The LPC111x/LPC11C1x are a ARM Cortex-M0 based, low-cost 32-bit MCU family, designed for 8/16-bit microcontroller applications, offering performance, low power, simple instruction set and memory addressing together with reduced code size compared to existing 8/16-bit architectures. The LPC111x/LPC11C1x operate at CPU frequencies of up to 50 MHz. The peripheral complement of the LPC111x/LPC11C1x includes up to 32 kB of flash memory, up to 8 kB of data memory, one C_CAN controller (LPC11C12/14 LPC11C12/14), one Fast-mode Plus I2C-bus interface, one RS-485/EIA-485 RS-485/EIA-485 UART, up to two SPI interfaces with SSP features, four general purpose timers, a 10-bit ADC, and up to 42 general purpose I/O pins. On-chip C_CAN drivers and flash In-System Programming tools via C_CAN are included on the LPC11C12/C14 LPC11C12/C14. Remark: The LPC111x/LPC11C1x series consists of the LPC1100 LPC1100 series (parts LPC111x/101/201/301), the LPC1100L LPC1100L series (parts LPC111x/102/202/302), and the LPC11C00 LPC11C00 series (parts LPC11C1x/301). The LPC1100L LPC1100L include the power profiles and the LPC11C00 LPC11C00 include the C_CAN controller and on-chip CAN drivers. 1.2 Features · System: ­ ARM Cortex-M0 processor, running at frequencies of up to 50 MHz. ­ ARM Cortex-M0 built-in Nested Vectored Interrupt Controller (NVIC). ­ Serial Wire Debug. ­ System tick timer. · Memory: ­ 32 kB (LPC1114/LPC11C14 LPC1114/LPC11C14), 24 kB (LPC1113 LPC1113), 16 kB (LPC1112/LPC11C12 LPC1112/LPC11C12), or 8 kB (LPC1111 LPC1111) on-chip flash programming memory. ­ 8 kB, 4 kB, or 2 kB SRAM. ­ In-System Programming (ISP) and In-Application Programming (IAP) via on-chip bootloader software. · Digital peripherals: ­ Up to 42 General Purpose I/O (GPIO) pins with configurable pull-up/pull-down resistors. ­ GPIO pins can be used as edge and level sensitive interrupt sources. ­ High-current output driver (20 mA) on one pin. ­ High-current sink drivers (20 mA) on two I2C-bus pins in Fast-mode Plus. UM10398 UM10398 User manual All information provided in this document is subject to legal disclaimers. Rev. 2 - 2 November 2010 © NXP B.V. 2010. All rights reserved. 3 of 407 UM10398 UM10398 NXP Semiconductors Chapter 1: LPC111x/LPC11C1x Introductory information ­ Four general purpose timers/counters with a total of four capture inputs and 13 match outputs. ­ Programmable WatchDog Timer (WDT). · Analog peripherals: ­ 10-bit ADC with input multiplexing among 8 pins. · Serial interfaces: ­ UART with fractional baud rate generation, internal FIFO, and RS-485 RS-485 support. ­ Two SPI controllers with SSP features and with FIFO and multi-protocol capabilities (second SPI on LQFP48 LQFP48 and PLCC44 PLCC44 packages only). ­ I2C-bus interface supporting full I2C-bus specification and Fast-mode Plus with a data rate of 1 Mbit/s with multiple address recognition and monitor mode. ­ C_CAN controller (LPC11C12/C14 LPC11C12/C14 only). On-chip CAN and CANopen drivers included. · Clock generation: ­ 12 MHz internal RC oscillator trimmed to 1% accuracy that can optionally be used as a system clock. ­ Crystal oscillator with an operating range of 1 MHz to 25 MHz. ­ Programmable watchdog oscillator with a frequency range of 7.8 kHz to 1.8 MHz. ­ PLL allows CPU operation up to the maximum CPU rate without the need for a high-frequency crystal. May be run from the system oscillator or the internal RC oscillator. ­ Clock output function with divider that can reflect the system oscillator clock, IRC clock, CPU clock, and the Watchdog clock. · Power control: ­ Integrated PMU (Power Management Unit) to minimize power consumption during Sleep, Deep-sleep, and Deep power-down modes. ­ Power profiles residing in boot ROM allowing to optimize performance and minimize power consumption for any given application through one simple function call. (On LPC111x/102/202/302 only.) ­ Three reduced power modes: Sleep, Deep-sleep, and Deep power-down. ­ Processor wake-up from Deep-sleep mode via a dedicated start logic using up to 13 of the functional pins. ­ Power-On Reset (POR). ­ Brownout detect with four separate thresholds for interrupt and forced reset. · Unique device serial number for identification. · Single 3.3 V power supply (1.8 V to 3.6 V). · Available as 48-pin LQFP package, 33-pin HVQFN package, and 44-pin PLCC package. UM10398 UM10398 User manual All information provided in this document is subject to legal disclaimers. Rev. 2 - 2 November 2010 © NXP B.V. 2010. All rights reserved. 4 of 407 UM10398 UM10398 NXP Semiconductors Chapter 1: LPC111x/LPC11C1x Introductory information 1.3 Ordering information Table 1. Ordering information Type number Package Name Description Version LPC1111FHN33/101 LPC1111FHN33/101 HVQFN33 HVQFN33 HVQFN: plastic thermal enhanced very thin quad flat package; no leads; 33 terminals; body 7 × 7 × 0.85 mm n/a LPC1111FHN33/102 LPC1111FHN33/102 HVQFN33 HVQFN33 HVQFN: plastic thermal enhanced very thin quad flat package; no leads; 33 terminals; body 7 × 7 × 0.85 mm n/a LPC1111FHN33/201 LPC1111FHN33/201 HVQFN33 HVQFN33 HVQFN: plastic thermal enhanced very thin quad flat package; no leads; 33 terminals; body 7 × 7 × 0.85 mm n/a LPC1111FHN33/202 LPC1111FHN33/202 HVQFN33 HVQFN33 HVQFN: plastic thermal enhanced very thin quad flat package; no leads; 33 terminals; body 7 × 7 × 0.85 mm n/a LPC1112FHN33/101 LPC1112FHN33/101 HVQFN33 HVQFN33 HVQFN: plastic thermal enhanced very thin quad flat package; no leads; 33 terminals; body 7 × 7 × 0.85 mm n/a LPC1112FHN33/102 LPC1112FHN33/102 HVQFN33 HVQFN33 HVQFN: plastic thermal enhanced very thin quad flat package; no leads; 33 terminals; body 7 × 7 × 0.85 mm n/a LPC1112FHN33/201 LPC1112FHN33/201 HVQFN33 HVQFN33 HVQFN: plastic thermal enhanced very thin quad flat package; no leads; 33 terminals; body 7 × 7 × 0.85 mm n/a LPC1112FHN33/202 LPC1112FHN33/202 HVQFN33 HVQFN33 HVQFN: plastic thermal enhanced very thin quad flat package; no leads; 33 terminals; body 7 × 7 × 0.85 mm n/a LPC1113FHN33/201 LPC1113FHN33/201 HVQFN33 HVQFN33 HVQFN: plastic thermal enhanced very thin quad flat package; no leads; 33 terminals; body 7 × 7 × 0.85 mm n/a LPC1113FHN33/202 LPC1113FHN33/202 HVQFN33 HVQFN33 HVQFN: plastic thermal enhanced very thin quad flat package; no leads; 33 terminals; body 7 × 7 × 0.85 mm n/a LPC1113FHN33/301 LPC1113FHN33/301 HVQFN33 HVQFN33 HVQFN: plastic thermal enhanced very thin quad flat package; no leads; 33 terminals; body 7 × 7 × 0.85 mm n/a LPC1113FHN33/302 LPC1113FHN33/302 HVQFN33 HVQFN33 HVQFN: plastic thermal enhanced very thin quad flat package; no leads; 33 terminals; body 7 × 7 × 0.85 mm n/a LPC1114FHN33/201 LPC1114FHN33/201 HVQFN33 HVQFN33 HVQFN: plastic thermal enhanced very thin quad flat package; no leads; 33 terminals; body 7 × 7 × 0.85 mm n/a LPC1114FHN33/202 LPC1114FHN33/202 HVQFN33 HVQFN33 HVQFN: plastic thermal enhanced very thin quad flat package; no leads; 33 terminals; body 7 × 7 × 0.85 mm n/a LPC1114FHN33/301 LPC1114FHN33/301 HVQFN33 HVQFN33 HVQFN: plastic thermal enhanced very thin quad flat package; no leads; 33 terminals; body 7 × 7 × 0.85 mm n/a LPC1114FHN33/302 LPC1114FHN33/302 HVQFN33 HVQFN33 HVQFN: plastic thermal enhanced very thin quad flat package; no leads; 33 terminals; body 7 × 7 × 0.85 mm n/a LPC1113FBD48/301 LPC1113FBD48/301 LQFP48 LQFP48 LQFP48 LQFP48: plastic low profile quad flat package; 48 leads; body 7 × 7 × sot313-2 1.4 mm LPC1113FBD48/302 LPC1113FBD48/302 LQFP48 LQFP48 LQFP48 LQFP48: plastic low profile quad flat package; 48 leads; body 7 × 7 × sot313-2 1.4 mm LPC1114FBD48/301 LPC1114FBD48/301 LQFP48 LQFP48 LQFP48 LQFP48: plastic low profile quad flat package; 48 leads; body 7 × 7 × sot313-2 1.4 mm LPC1114FBD48/302 LPC1114FBD48/302 LQFP48 LQFP48 LQFP48 LQFP48: plastic low profile quad flat package; 48 leads; body 7 × 7 × sot313-2 1.4 mm LPC1114FA44/301 LPC1114FA44/301 PLCC44 PLCC44 PLCC44 PLCC44; plastic leaded chip carrier; 44 leads UM10398 UM10398 User manual All information provided in this document is subject to legal disclaimers. Rev. 2 - 2 November 2010 sot187-2 © NXP B.V. 2010. All rights reserved. 5 of 407 UM10398 UM10398 NXP Semiconductors Chapter 1: LPC111x/LPC11C1x Introductory information Table 1. Ordering information .continued Type number Package Name Description Version LPC1114FA44/302 LPC1114FA44/302 PLCC44 PLCC44 PLCC44 PLCC44; plastic leaded chip carrier; 44 leads sot187-2 LPC11C12FBD48/301 LPC11C12FBD48/301 LQFP48 LQFP48 LQFP48 LQFP48: plastic low profile quad flat package; 48 leads; body 7 × 7 × sot313-2 1.4 mm LPC11C14FBD48/301 LPC11C14FBD48/301 LQFP48 LQFP48 LQFP48 LQFP48: plastic low profile quad flat package; 48 leads; body 7 × 7 × sot313-2 1.4 mm Table 2. Ordering options Series Flash Total UART I2C/ SRAM RS-485 RS-485 Fm+ SPI C_CAN Power ADC profiles channels Package LPC1111FHN33/101 LPC1111FHN33/101 LPC1100 LPC1100 8 kB 2 kB 1 1 1 - no 8 HVQFN33 HVQFN33 LPC1111FHN33/102 LPC1111FHN33/102 LPC1100L LPC1100L 8 kB 2 kB 1 1 1 - yes 8 HVQFN33 HVQFN33 LPC1111FHN33/201 LPC1111FHN33/201 LPC1100 LPC1100 8 kB 4 kB 1 1 1 - no 8 HVQFN33 HVQFN33 LPC1111FHN33/202 LPC1111FHN33/202 LPC1100L LPC1100L 8 kB 4 kB 1 1 1 - yes 8 HVQFN33 HVQFN33 LPC1112FHN33/101 LPC1112FHN33/101 LPC1100 LPC1100 16 kB 2 kB 1 1 1 - no 8 HVQFN33 HVQFN33 LPC1112FHN33/102 LPC1112FHN33/102 LPC1100L LPC1100L 16 kB 2 kB 1 1 1 - yes 8 HVQFN33 HVQFN33 LPC1112FHN33/201 LPC1112FHN33/201 LPC1100 LPC1100 16 kB 4 kB 1 1 1 - no 8 HVQFN33 HVQFN33 LPC1112FHN33/202 LPC1112FHN33/202 LPC1100L LPC1100L 16 kB 4 kB 1 1 1 - yes 8 HVQFN33 HVQFN33 LPC1113FHN33/201 LPC1113FHN33/201 LPC1100 LPC1100 24 kB 4 kB 1 1 1 - no 8 HVQFN33 HVQFN33 LPC1113FHN33/202 LPC1113FHN33/202 LPC1100L LPC1100L 24 kB 4 kB 1 1 1 - yes 8 HVQFN33 HVQFN33 LPC1113FHN33/301 LPC1113FHN33/301 LPC1100 LPC1100 24 kB 8 kB 1 1 1 - no 8 HVQFN33 HVQFN33 LPC1113FHN33/302 LPC1113FHN33/302 LPC1100L LPC1100L 24 kB 8 kB 1 1 1 - yes 8 HVQFN33 HVQFN33 LPC1113FBD48/301 LPC1113FBD48/301 LPC1100 LPC1100 24 kB 8 kB 1 1 2 - no 8 LQFP48 LQFP48 LPC1113FBD48/302 LPC1113FBD48/302 LPC1100L LPC1100L 24 kB 8 kB 1 1 2 - yes 8 LQFP48 LQFP48 LPC1114FHN33/201 LPC1114FHN33/201 LPC1100 LPC1100 32 kB 4 kB 1 1 1 - no 8 HVQFN33 HVQFN33 LPC1114FHN33/202 LPC1114FHN33/202 LPC1100L LPC1100L 32 kB 4 kB 1 1 1 - yes 8 HVQFN33 HVQFN33 LPC1114FHN33/301 LPC1114FHN33/301 LPC1100 LPC1100 8 kB 1 1 1 - no 8 HVQFN33 HVQFN33 Type number LPC1111 LPC1111 LPC1112 LPC1112 LPC1113 LPC1113 LPC1114 LPC1114 32 kB LPC1114FHN33/302 LPC1114FHN33/302 LPC1100L LPC1100L 32 kB 8 kB 1 1 1 - yes 8 HVQFN33 HVQFN33 LPC1114FBD48/301 LPC1114FBD48/301 LPC1100 LPC1100 32 kB 8 kB 1 1 2 - no 8 LQFP48 LQFP48 LPC1114FBD48/302 LPC1114FBD48/302 LPC1100L LPC1100L 32 kB 8 kB 1 1 2 - yes 8 LQFP48 LQFP48 LPC1114FA44/301 LPC1114FA44/301 LPC1100 LPC1100 32 kB 8 kB 1 1 2 - no 8 PLCC44 PLCC44 LPC1114FA44/302 LPC1114FA44/302 LPC1100L LPC1100L 32 kB 8 kB 1 1 2 - yes 8 PLCC44 PLCC44 LPC11C12FBD48/301 LPC11C12FBD48/301 LPC11C00 LPC11C00 16 kB 8 kB 1 1 2 1 no 8 LQFP48 LQFP48 LPC11C14FBD48/301 LPC11C14FBD48/301 LPC11C00 LPC11C00 32 kB 8 kB 1 1 2 1 no 8 LQFP48 LQFP48 LPC11C1x UM10398 UM10398 User manual All information provided in this document is subject to legal disclaimers. Rev. 2 - 2 November 2010 © NXP B.V. 2010. All rights reserved. 6 of 407 UM10398 UM10398 NXP Semiconductors Chapter 1: LPC111x/LPC11C1x Introductory information 1.4 Block diagram XTALIN XTALOUT RESET SWD LPC1111/12/13/14 LPC1111/12/13/14 LPC11C12/C14 LPC11C12/C14 IRC TEST/DEBUG INTERFACE CLOCK GENERATION, POWER CONTROL, SYSTEM FUNCTIONS POR ARM CORTEX-M0 system bus clocks and controls FLASH 8/16/24/32 kB slave GPIO ports PIO0/1/2/3 HIGH-SPEED GPIO CLKOUT SRAM 2/4/8 kB slave ROM slave slave AHB-LITE BUS slave AHB TO APB BRIDGE RXD TXD DTR, DSR(1), CTS, DCD(1), RI(1), RTS CT32B0 CT32B0_MAT[3:0] CT32B0 CT32B0_CAP0 CT32B1 CT32B1_MAT[3:0] CT32B1 CT32B1_CAP0 CT16B0 CT16B0_MAT[2:0] CT16B0 CT16B0_CAP0 CT16B1 CT16B1_MAT[1:0] CT16B1 CT16B1_CAP0 UART 10-bit ADC AD[7:0] SPI0 SCK0, SSEL0 MISO0, MOSI0 SPI1(1) SCK1, SSEL1 MISO1, MOSI1 32-bit COUNTER/TIMER 0 32-bit COUNTER/TIMER 1 I2C-BUS 16-bit COUNTER/TIMER 0 WDT 16-bit COUNTER/TIMER 1 CAN_TXD CAN_RXD SCL SDA IOCONFIG C_CAN(2) SYSTEM CONTROL PMU (1) LQFP48/PLCC44 LQFP48/PLCC44 packages only. (2) LPC11C12/C14 LPC11C12/C14 only. Fig 1. LPC111x/LPC11C1x block diagram UM10398 UM10398 User manual All information provided in this document is subject to legal disclaimers. Rev. 2 - 2 November 2010 © NXP B.V. 2010. All rights reserved. 7 of 407 UM10398 UM10398 NXP Semiconductors Chapter 1: LPC111x/LPC11C1x Introductory information 1.5 ARM Cortex-M0 processor The ARM Cortex-M0 processor is described in detail in Section 22.2 "About the Cortex-M0 processor and core peripherals". For the LPC111x/LPC11C1x, the ARM Cortex-M0 processor core is configured as follows: · System options: ­ The Nested Vectored Interrupt Controller (NVIC) is included and supports up to 32 interrupts. ­ The system tick timer is included. · Debug options: Serial Wire Debug is included with two watchpoints and four breakpoints. UM10398 UM10398 User manual All information provided in this document is subject to legal disclaimers. Rev. 2 - 2 November 2010 © NXP B.V. 2010. All rights reserved. 8 of 407 UM10398 UM10398 Chapter 2: LPC111x/LPC11C1x Memory mapping Rev. 2 - 2 November 2010 User manual 2.1 How to read this chapter Table 3 and Table 4 show the memory configurations for different LPC111x/LPC11C1x parts. Table 3. LPC111x memory configuration Part Flash Suffix SRAM /101; /102 /201; /202 /301; /302 LPC1111 LPC1111 8 kB 2 kB 4 KB - LPC1112 LPC1112 16 kB 2 kB 4 KB - LPC1113 LPC1113 24 kB - 4 KB 8 kB LPC1114 LPC1114 32 kB - 4 KB 8 kB LPC11C12 LPC11C12 16 kB - - 8 kB LPC11C14 LPC11C14 32 kB - - 8 kB Table 4. LPC11C1x memory configuration Part Flash SRAM LPC11C12/301 LPC11C12/301 16 kB 8 kB LPC11C14/301 LPC11C14/301 32 kB 8 kB 2.2 Memory map Figure 2 shows the memory and peripheral address space of the LPC111x/LPC11C1x. The AHB peripheral area is 2 MB in size and is divided to allow for up to 128 peripherals. On the LPC111x/LPC11C1x, the GPIO ports are the only AHB peripherals. The APB peripheral area is 512 kB in size and is divided to allow for up to 32 peripherals. Each peripheral of either type is allocated 16 kB of space. This allows simplifying the address decoding for each peripheral. All peripheral register addresses are 32-bit word aligned regardless of their size. An implication of this is that word and half-word registers must be accessed all at once. For example, it is not possible to read or write the upper byte of a word register separately. UM10398 UM10398 User manual All information provided in this document is subject to legal disclaimers. Rev. 2 - 2 November 2010 © NXP B.V. 2010. All rights reserved. 9 of 407 UM10398 UM10398 NXP Semiconductors Chapter 2: LPC111x/LPC11C1x Memory mapping 4 GB LPC1111/12/13/14 LPC1111/12/13/14 LPC11C12/C14 LPC11C12/C14 AHB peripherals 0x5020 0000 0xFFFF FFFF reserved 16 - 127 reserved 0xE010 0000 private peripheral bus 0x5004 0000 0xE000 0000 12-15 GPIO PIO3 0x5020 0000 8-11 GPIO PIO2 0x5000 0000 4-7 GPIO PIO1 0-3 GPIO PIO0 reserved AHB peripherals APB peripherals reserved 0x5003 0000 0x5002 0000 0x5001 0000 0x5000 0000 0x4008 0000 23 - 31 reserved 0x4005 C000 0x4008 0000 APB peripherals 1 GB 22 SPI1(1) 0x4005 8000 reserved 0x4000 0000 0x4005 4000 20 C_CAN(2) reserved reserved 18 17 IOCONFIG 16 15 SPI0 flash controller 14 0x2000 0000 0.5 GB system control PMU 0x4004 8000 0x4004 4000 0x4003 C000 0x4003 8000 10 - 13 reserved 0x1FFF 4000 0x4002 8000 reserved 0x1FFF 0000 0x4002 4000 reserved reserved 0x0000 8000 32 kB on-chip flash (LPC1114 LPC1114; LPC11C14 LPC11C14) 24 kB on-chip flash (LPC1113 LPC1113) 0x4000 4000 0x4000 0000 0x0000 4000 16 kB on-chip flash (LPC1112 LPC1112; LPC11C12 LPC11C12) 8 kB on-chip flash (LPC1111 LPC1111) 0x0000 6000 0x4000 8000 I2C-bus 0x1000 0000 0x4000 C000 WDT 0x1000 0800 0x4001 0000 16-bit counter/timer 0 UART 2 kB SRAM (LPC1111/12/101/102 LPC1111/12/101/102) 0x4001 4000 16-bit counter/timer 1 4 kB SRAM (LPC1111/12/13/14/201/202 LPC1111/12/13/14/201/202) 0x4001 8000 32-bit counter/timer 0 0x1000 1000 0x4001 C000 32-bit counter/timer 1 0x1000 2000 8 kB SRAM (LPC1113/14/301/302 LPC1113/14/301/302; LPC11C1x) 0x4002 0000 ADC reserved 0 GB 0x4004 C000 0x4004 0000 reserved 16 kB boot ROM 0x4005 0000 0x0000 2000 0x0000 00C0 active interrupt vectors 0x0000 0000 0x0000 0000 (1) LQFP48/PLCC44 LQFP48/PLCC44 packages only. (2) LPC11C12/14 LPC11C12/14 only. Fig 2. LPC111x/LPC11C1x memory map UM10398 UM10398 User manual All information provided in this document is subject to legal disclaimers. Rev. 2 - 2 November 2010 © NXP B.V. 2010. All rights reserved. 10 of 407 UM10398 UM10398 Chapter 3: LPC111x/LPC11C1x System configuration Rev. 2 - 2 November 2010 User manual 3.1 How to read this chapter The C_CAN controller is available on parts LPC11C12/14 LPC11C12/14 only, and the corresponding clock and reset control bits (bit 17 in the SYSAHBCLKCTRL register and bit 3 in PRESETCTRL register) are reserved for all LPC1111x parts. Remark: For parts LPC111x/102/202/302, also refer to Chapter 5 for setting up power profiles. 3.2 Introduction The system configuration block controls oscillators, start logic, and clock generation of the LPC111x/LPC11C1x. Also included in this block are registers for setting the priority for AHB access and a register for remapping flash, SRAM, and ROM memory areas. 3.3 Pin description Table 5 shows pins that are associated with system control block functions. Table 5. Pin summary Pin name Pin direction Pin description CLKOUT O Clockout pin PIO0_0 to PIO0_11 I Start logic wake-up pins port 0 PIO1_0 I Start logic wake-up pin port 1 3.4 Clock generation See Figure 3 for an overview of the LPC111x/LPC11C1x Clock Generation Unit (CGU). The LPC111x/LPC11C1x include three independent oscillators. These are the system oscillator, the Internal RC oscillator (IRC), and the watchdog oscillator. Each oscillator can be used for more than one purpose as required in a particular application. Following reset, the LPC111x/LPC11C1x will operate from the Internal RC oscillator until switched by software. This allows systems to operate without any external crystal and the bootloader code to operate at a known frequency. The SYSAHBCLKCTRL register gates the system clock to the various peripherals and memories. UART, the WDT, and SPI0/1 have individual clock dividers to derive peripheral clocks from the main clock. The main clock and the clock outputs from the IRC, the system oscillator, and the watchdog oscillator can be observed directly on the CLKOUT pin. For details on power control see Section 3.8. UM10398 UM10398 User manual All information provided in this document is subject to legal disclaimers. Rev. 2 - 2 November 2010 © NXP B.V. 2010. All rights reserved. 11 of 407 UM10398 UM10398 NXP Semiconductors Chapter 3: LPC111x/LPC11C1x System configuration SYSTEM CLOCK DIVIDER AHB clock 0 (system) system clock AHB clocks 1 to 18 (memories and peripherals) 18 AHBCLKCTRL[1:18] SPI0 PERIPHERAL CLOCK DIVIDER SPI0_PCLK UART PERIPHERAL CLOCK DIVIDER IRC oscillator UART_PCLK SPI1 PERIPHERAL CLOCK DIVIDER SPI1_PCLK WDT CLOCK DIVIDER WDT_PCLK CLKOUT PIN CLOCK DIVIDER CLKOUT pin main clock watchdog oscillator MAINCLKSEL (main clock select) sys_pllclkout IRC oscillator IRC oscillator sys_pllclkin system oscillator SYSTEM PLL watchdog oscillator SYSPLLCLKSEL (system PLL clock select) WDTUEN (WDT clock update enable) IRC oscillator system oscillator watchdog oscillator CLKOUTUEN (CLKOUT update enable) Fig 3. LPC111x/LPC11C1x CGU block diagram 3.5 Register description All registers, regardless of size, are on word address boundaries. Details of the registers appear in the description of each function. See Section 3.11 for the flash access timing register, which can be re-configured as part the system setup. This register is not part of the system configuration block. Table 6. Register overview: system control block (base address 0x4004 8000) Name Access Address offset Description Reset value Reference SYSMEMREMAP R/W 0x000 System memory remap 0x002 Table 7 PRESETCTRL R/W 0x004 Peripheral reset control 0x000 Table 8 SYSPLLCTRL R/W 0x008 System PLL control 0x000 Table 9 SYSPLLSTAT R 0x00C System PLL status 0x000 Table 10 - - 0x010 - 0x01C Reserved - - UM10398 UM10398 User manual All information provided in this document is subject to legal disclaimers. Rev. 2 - 2 November 2010 © NXP B.V. 2010. All rights reserved. 12 of 407 UM10398 UM10398 NXP Semiconductors Chapter 3: LPC111x/LPC11C1x System configuration Table 6. Register overview: system control block (base address 0x4004 8000) .continued Name Access Address offset Description Reset value Reference SYSOSCCTRL R/W 0x020 System oscillator control 0x000 Table 11 WDTOSCCTRL R/W 0x024 Watchdog oscillator control 0x000 Table 12 IRCCTRL R/W 0x028 IRC control 0x080 Table 13 - - 0x02C Reserved - - SYSRSTSTAT R 0x030 System reset status register 0x000 Table 14 - - 0x034 - 0x03C Reserved - - SYSPLLCLKSEL R/W 0x040 System PLL clock source select 0x000 Table 15 SYSPLLCLKUEN R/W 0x044 System PLL clock source update enable 0x000 Table 16 - - 0x048 - 0x06C Reserved - - MAINCLKSEL R/W 0x070 Main clock source select 0x000 Table 17 MAINCLKUEN R/W 0x074 Main clock source update enable 0x000 Table 18 SYSAHBCLKDIV R/W 0x078 System AHB clock divider 0x001 Table 19 - - 0x07C Reserved - - SYSAHBCLKCTRL R/W 0x080 System AHB clock control 0x85F Table 20 - - 0x084 - 0x090 Reserved - - SSP0CLKDIV R/W 0x094 SPI0 clock divder 0x000 Table 21 UARTCLKDIV R/W 0x098 UART clock divder 0x000 Table 22 SSP1CLKDIV R/W 0x09C SPI1 clock divder 0x000 Table 23 - - 0x0A0-0x0CC Reserved - - WDTCLKSEL R/W 0x0D0 WDT clock source select 0x000 Table 24 WDTCLKUEN R/W 0x0D4 WDT clock source update enable 0x000 Table 25 WDTCLKDIV R/W 0x0D8 WDT clock divider 0x000 Table 26 - - 0x0DC Reserved - - CLKOUTCLKSEL R/W 0x0E0 CLKOUT clock source select 0x000 Table 27 CLKOUTUEN R/W 0x0E4 CLKOUT clock source update enable 0x000 Table 28 CLKOUTCLKDIV R/W 0x0E8 CLKOUT clock divider 0x000 Table 29 - - 0x0EC - 0x0FC Reserved - - PIOPORCAP0 R 0x100 POR captured PIO status 0 user dependent Table 30 PIOPORCAP1 R 0x104 POR captured PIO status 1 user dependent Table 31 - R 0x108 - 0x14C Reserved - - BODCTRL R/W 0x150 BOD control 0x000 Table 32 SYSTCKCAL R/W 0x154 System tick counter calibration 0x004 Table 33 - - 0x158 - 0x1FC Reserved - - STARTAPRP0 R/W 0x200 Start logic edge control register 0 Table 34 STARTERP0 R/W 0x204 Start logic signal enable register 0 Table 35 STARTRSRP0CLR W 0x208 Start logic reset register 0 n/a Table 36 STARTSRP0 R 0x20C Start logic status register 0 n/a Table 37 - - 0x210 - 0x22C Reserved - - UM10398 UM10398 User manual All information provided in this document is subject to legal disclaimers. Rev. 2 - 2 November 2010 © NXP B.V. 2010. All rights reserved. 13 of 407 UM10398 UM10398 NXP Semiconductors Chapter 3: LPC111x/LPC11C1x System configuration Table 6. Register overview: system control block (base address 0x4004 8000) .continued Name Access Address offset Description Reset value Reference PDSLEEPCFG R/W 0x230 Power-down states in Deep-sleep mode 0x0000 0000 Table 39 PDAWAKECFG R/W 0x234 Power-down states after wake-up from Deep-sleep mode 0x0000 EDF0 Table 40 PDRUNCFG R/W 0x238 Power-down configuration register 0x0000 EDF0 Table 41 - - 0x23C - 0x3F0 Reserved - - DEVICE_ID R 0x3F4 Device ID part dependent Table 42 3.5.1 System memory remap register The system memory remap register selects whether the ARM interrupt vectors are read from the boot ROM, the flash, or the SRAM. Table 7. System memory remap register (SYSMEMREMAP, address 0x4004 8000) bit description Bit Symbol 1:0 Value Description MAP Reset value System memory remap 10 0x0 0x1 User Flash Mode. Interrupt vectors are not re-mapped and reside in Flash. - - User RAM Mode. Interrupt vectors are re-mapped to Static RAM. 0x2 31:2 Boot Loader Mode. Interrupt vectors are re-mapped to Boot ROM. Reserved 0x00 3.5.2 Peripheral reset control register This register allows software to reset the SPI and I2C peripherals. Writing a 0 to the SSP0/1_RST_N or I2C_RST_N bits resets the SPI0/1 or I2C peripheral. Writing a 1 de-asserts the reset. Remark: Before accessing the SPI and I2C peripherals, write a 1 to this register to ensure that the reset signals to the SPI and I2C are de-asserted. Table 8. Peripheral reset control register (PRESETCTRL, address 0x4004 8004) bit description Bit Symbol Value 0 SSP0_RST_N Description Reset value SPI0 reset control 0 0 1 Resets the SPI0 peripheral. 1 SPI0 reset de-asserted. I2C_RST_N I2C reset control 0 UM10398 UM10398 User manual Resets the I2C peripheral. 1 0 I2C reset de-asserted. All information provided in this document is subject to legal disclaimers. Rev. 2 - 2 November 2010 © NXP B.V. 2010. All rights reserved. 14 of 407 UM10398 UM10398 NXP Semiconductors Chapter 3: LPC111x/LPC11C1x System configuration Table 8. Peripheral reset control register (PRESETCTRL, address 0x4004 8004) bit description Bit Symbol 2 SSP1_RST_N Description Reset value SPI1 reset control 0 0 Resets the SPI1 peripheral. 1 3 Value SPI1 reset de-asserted. CAN_RST_N C_CAN reset control 0 31:4 C_CAN reset de-asserted. - - Resets the C_CAN peripheral. 1 0 Reserved 0x00 3.5.3 System PLL control register This register connects and enables the system PLL and configures the PLL multiplier and divider values. The PLL accepts an input frequency from 10 MHz to 25 MHz from various clock sources. The input frequency is multiplied up to a high frequency, then divided down to provide the actual clock used by the CPU, peripherals, and memories. The PLL can produce a clock up to the maximum allowed for the CPU. Table 9. System PLL control register (SYSPLLCTRL, address 0x4004 8008) bit description Bit Symbol 4:0 MSEL 6:5 Value PSEL Description Reset value Feedback divider value. The division value M is the programmed MSEL value + 1. 00000: Division ratio M = 1 to 11111: Division ratio M = 32. 0x000 Post divider ratio P. The division ratio is 2 × P. 0x00 0x0 0x1 P=4 0x3 P=8 - - P=2 0x2 31:7 P=1 Reserved. Do not write ones to reserved bits. 0x0 3.5.4 System PLL status register This register is a Read-only register and supplies the PLL lock status (see Section 3.10.1). Table 10. System PLL status register (SYSPLLSTAT, address 0x4004 800C) bit description Bit Symbol 0 Value LOCK Description Reset value PLL lock status 0x0 0 1 31:1 UM10398 UM10398 User manual - PLL not locked PLL locked - Reserved All information provided in this document is subject to legal disclaimers. Rev. 2 - 2 November 2010 0x00 © NXP B.V. 2010. All rights reserved. 15 of 407 UM10398 UM10398 NXP Semiconductors Chapter 3: LPC111x/LPC11C1x System configuration 3.5.5 System oscillator control register This register configures the frequency range for the system oscillator. Table 11. System oscillator control register (SYSOSCCTRL, address 0x4004 8020) bit description Bit Symbol Value 0 BYPASS Description Reset value Bypass system oscillator 0x0 0 1 Oscillator is not bypassed. 1 Bypass enabled. PLL input (sys_osc_clk) is fed directly from the XTALIN and XTALOUT pins. FREQRANGE Determines frequency range for Low-power oscillator. 0 31:2 15 - 25 MHz frequency range - - 1 - 20 MHz frequency range. 1 Reserved 0x0 0x00 3.5.6 Watchdog oscillator control register This register configures the watchdog oscillator. The oscillator consists of an analog and a digital part. The analog part contains the oscillator function and generates an analog clock (Fclkana). With the digital part, the analog output clock (Fclkana) can be divided to the required output clock frequency wdt_osc_clk. The analog output frequency (Fclkana) can be adjusted with the FREQSEL bits between 500 kHz and 3.4 MHz. With the digital part Fclkana will be divided (divider ratios = 2, 4,.,64) to wdt_osc_clk using the DIVSEL bits. The output clock frequency of the watchdog oscillator can be calculated as wdt_osc_clk = Fclkana/(2 × (1 + DIVSEL) = 7.8 kHz to 1.7 MHz (nominal values). Remark: Any setting of the FREQSEL bits will yield a Fclkana value within ±40% of the listed frequency value. The watchdog oscillator is the clock source with the lowest power consumption. If accurate timing is required, use the IRC or system oscillator. Remark: The frequency of the watchdog oscillator is undefined after reset. The watchdog oscillator frequency must be programmed by writing to the WDTOSCCTRL register before using the watchdog oscillator. Table 12. Watchdog oscillator control register (WDTOSCCTRL, address 0x4004 8024) bit description Bit Symbol 4:0 8:5 Value Description Reset value DIVSEL Select divider for Fclkana. wdt_osc_clk = Fclkana/ (2 × (1 + DIVSEL) 00000: 2 × (1 + DIVSEL) = 2 00001: 2 × (1 + DIVSEL) = 4 to 11111: 2 × (1 + DIVSEL) = 64 0 FREQSEL Select watchdog oscillator analog output frequency (Fclkana). 0x00 0x1 0x2 UM10398 UM10398 User manual 0.5 MHz 0.8 MHz All information provided in this document is subject to legal disclaimers. Rev. 2 - 2 November 2010 © NXP B.V. 2010. All rights reserved. 16 of 407 UM10398 UM10398 NXP Semiconductors Chapter 3: LPC111x/LPC11C1x System configuration Table 12. Bit Watchdog oscillator control register (WDTOSCCTRL, address 0x4004 8024) bit description Description 1.1 MHz 0x4 1.4 MHz 0x5 1.6 MHz 0x6 1.8 MHz 0x7 2.0 MHz 0x8 2.2 MHz 0x9 2.4 MHz 0xA 2.6 MHz 0xB 2.7 MHz 0xC 2.9 MHz 0xD 3.1 MHz 0xE 3.2 MHz 0xF 3.4 MHz - - Value 0x3 31:9 Symbol Reset value Reserved 0x00 3.5.7 Internal resonant crystal control register This register is used to trim the on-chip 12 MHz oscillator. The trim value is factory-preset and written by the boot code on start-up. Table 13. Internal resonant crystal control register (IRCCTRL, address 0x4004 8028) bit description Bit Reset value TRIM Trim value 0x1000 0000, then flash will reprogram 31:9 User manual Description 7:0 UM10398 UM10398 Symbol - Reserved 0x00 All information provided in this document is subject to legal disclaimers. Rev. 2 - 2 November 2010 © NXP B.V. 2010. All rights reserved. 17 of 407 UM10398 UM10398 NXP Semiconductors Chapter 3: LPC111x/LPC11C1x System configuration 3.5.8 System reset status register if another reset signal - for example EXTRST - remains asserted after the POR signal is negated, then its bit is set to detected. Table 14. System reset status register (SYSRSTSTAT, address 0x4004 8030) bit description Bit Symbol 0 Value POR Description Reset value POR reset status 0x0 0 1 1 No POR detected. POR detected. EXTRST 0x0 0 1 No WDT reset detected. 1 3 RESET detected. 0 2 No RESET event detected. WDT reset detected. WDT Status of the Watchdog reset BOD Status of the Brown-out detect reset 0 4 BOD reset detected. SYSRST Status of the software system reset 0 System reset detected. - - Reserved 0x0 No System reset detected. 1 31:5 0x0 No BOD reset detected. 1 0x0 0x0 3.5.9 System PLL clock source select register This register selects the clock source for the system PLL. The SYSPLLCLKUEN register (see Section 3.5.10) must be toggled from LOW to HIGH for the update to take effect. Remark: When switching clock sources, both clocks must be running before the clock source is updated. Remark: When using the C_CAN controller with baudrates above 100 kbit/s, the system oscillator must be selected. Table 15. System PLL clock source select register (SYSPLLCLKSEL, address 0x4004 8040) bit description Bit Symbol 1:0 Value SEL Description Reset value System PLL clock source 0x00 0x0 0x1 UM10398 UM10398 User manual Reserved 0x3 - System oscillator 0x2 31:2 IRC oscillator Reserved - Reserved All information provided in this document is subject to legal disclaimers. Rev. 2 - 2 November 2010 0x00 © NXP B.V. 2010. All rights reserved. 18 of 407 UM10398 UM10398 NXP Semiconductors Chapter 3: LPC111x/LPC11C1x System configuration 3.5.10 System PLL clock source update enable register This register updates the clock source of the system PLL with the new input clock after the SYSPLLCLKSEL register has been written to. In order for the update to take effect, first write a zero to the SYSPLLUEN register and then write a one to SYSPLLUEN. Remark: When switching clock sources, both clocks must be running before the clock source is updated. Table 16. System PLL clock source update enable register (SYSPLLCLKUEN, address 0x4004 8044) bit description Bit Symbol 0 Value ENA Description Reset value Enable system PLL clock source update 0x0 0 31:1 Update clock source - - No change 1 Reserved 0x00 3.5.11 Main clock source select register This register selects the main system clock which can be either any input to the system PLL, the output from the system PLL (sys_pllclkout), or the watchdog or IRC oscillators directly. The main system clock clocks the core, the peripherals, and the memories. The MAINCLKUEN register (see Section 3.5.12) must be toggled from LOW to HIGH for the update to take effect. Remark: When switching clock sources, both clocks must be running before the clock source is updated. Remark: When using the C_CAN controller with baudrates above 100 kbit/s, the system oscillator must be selected. Table 17. Main clock source select register (MAINCLKSEL, address 0x4004 8070) bit description Bit Symbol 1:0 Value SEL Description Reset value Clock source for main clock 0x00 0x0 0x1 WDT oscillator 0x3 - Input clock to system PLL 0x2 31:2 IRC oscillator System PLL clock out - Reserved 0x00 3.5.12 Main clock source update enable register This register updates the clock source of the main clock with the new input clock after the MAINCLKSEL register has been written to. In order for the update to take effect, first write a zero to the MAINCLKUEN register and then write a one to MAINCLKUEN. Remark: When switching clock sources, both clocks must be running before the clock source is updated. UM10398 UM10398 User manual All information provided in this document is subject to legal disclaimers. Rev. 2 - 2 November 2010 © NXP B.V. 2010. All rights reserved. 19 of 407 UM10398 UM10398 NXP Semiconductors Chapter 3: LPC111x/LPC11C1x System configuration Table 18. Main clock source update enable register (MAINCLKUEN, address 0x4004 8074) bit description Bit Symbol 0 ENA Value Description Reset value Enable main clock source update 0x0 0 1 31:1 Update clock source - - No change Reserved 0x00 3.5.13 System AHB clock divider register This register divides the main clock to provide the system clock to the core, memories, and the peripherals. The system clock can be shut down completely by setting the DIV bits to 0x0. Table 19. System AHB clock divider register (SYSAHBCLKDIV, address 0x4004 8078) bit description Bit Symbol Description Reset value 7:0 DIV System AHB clock divider values 0: System clock disabled. 1: Divide by 1. to 255: Divide by 255. 0x01 31:8 - Reserved 0x00 3.5.14 System AHB clock control register The AHBCLKCTRL register enables the clocks to individual system and peripheral blocks. The system clock (sys_ahb_clk[0], bit 0 in the AHBCLKCTRL register) provides the clock for the AHB to APB bridge, the AHB matrix, the ARM Cortex-M0, the Syscon block, and the PMU. This clock cannot be disabled. Table 20. System AHB clock control register (SYSAHBCLKCTRL, address 0x4004 8080) bit description Bit Symbol 0 Value SYS Description Reset value Enables clock for AHB to APB bridge, to the AHB matrix, to the Cortex-M0 FCLK and HCLK, to the SysCon, and to the PMU. This bit is read only. 1 0 1 1 Reserved Enable ROM Enables clock for ROM. 0 1 2 RAM Disable Enable Enables clock for RAM. 0 User manual 1 Disable 1 UM10398 UM10398 1 Enable All information provided in this document is subject to legal disclaimers. Rev. 2 - 2 November 2010 © NXP B.V. 2010. All rights reserved. 20 of 407 UM10398 UM10398 NXP Semiconductors Chapter 3: LPC111x/LPC11C1x System configuration Table 20. System AHB clock control register (SYSAHBCLKCTRL, address 0x4004 8080) bit description .continued Bit Symbol 3 FLASHREG Description Reset value Enables clock for flash register interface. 1 0 Disabled 1 4 Value Enabled FLASHARRAY Enables clock for flash array access. 0 5 Disabled 1 Enabled I2C Enables clock for I2C. 0 1 6 GPIO Enable Enables clock for GPIO. Enable 0 Disable 1 Enable CT16B0 CT16B0 Enables clock for 16-bit counter/timer 0. CT16B1 CT16B1 Enable CT32B0 CT32B0 Enables clock for 32-bit counter/timer 0. 0 Enable CT32B1 CT32B1 Enables clock for 32-bit counter/timer 1. 0 Enable SSP0 Enables clock for SPI0. 0 Enable UART Enables clock for UART. Note that the UART pins must be configured in the IOCON block before the UART clock can be enabled. 0 Enable ADC Enables clock for ADC. 0 Enable - Reserved WDT 0 Enables clock for WDT. 0 0 User manual Disable 1 UM10398 UM10398 0 Disable 1 15 0 Disable 1 14 1 Disable 1 13 0 Disable 1 12 0 Disable 1 11 0 Disable 1 10 0 Enables clock for 16-bit counter/timer 1. 0 9 1 Disable 1 8 0 Disable 0 7 1 Enable All information provided in this document is subject to legal disclaimers. Rev. 2 - 2 November 2010 © NXP B.V. 2010. All rights reserved. 21 of 407 UM10398 UM10398 NXP Semiconductors Chapter 3: LPC111x/LPC11C1x System configuration Table 20. System AHB clock control register (SYSAHBCLKCTRL, address 0x4004 8080) bit description .continued Bit Symbol 16 Value IOCON Description Reset value Enables clock for I/O configuration block. 0 0 1 17 Disable Enable CAN Enables clock for C_CAN 0 18 Disable 1 Enable SSP1 Enables clock for SPI1. 0 Enable - - 0 Disable 1 31:19 0 Reserved 0x00 3.5.15 SPI0 clock divider register This register configures the SPI0 peripheral clock SPI0_PCLK. The SPI0_PCLK can be shut down by setting the DIV bits to 0x0. Table 21. SPI0 clock divider register (SSP0CLKDIV, address 0x4004 8094) bit description Bit Symbol Description Reset value 7:0 DIV SPI0_PCLK clock divider values 0: Disable SPI0_PCLK. 1: Divide by 1. to 255: Divide by 255. 0x00 31:8 - Reserved 0x00 3.5.16 UART clock divider register This register configures the UART peripheral clock UART_PCLK. The UART_PCLK can be shut down by setting the DIV bits to 0x0. Remark: Note that the UART pins must be configured in the IOCON block before the UART clock can be enabled. Table 22. UART clock divider register (UARTCLKDIV, address 0x4004 8098) bit description Bit Symbol Description Reset value 7:0 DIV UART_PCLK clock divider values 0: Disable UART_PCLK. 1: Divide by 1. to 255: Divide by 255. 0x00 31:8 - Reserved 0x00 3.5.17 SPI1 clock divider register This register configures the SPI1 peripheral clock SPI1_PCLK. The SPI1_PCLK can be shut down by setting the DIV bits to 0x0. UM10398 UM10398 User manual All information provided in this document is subject to legal disclaimers. Rev. 2 - 2 November 2010 © NXP B.V. 2010. All rights reserved. 22 of 407 UM10398 UM10398 NXP Semiconductors Chapter 3: LPC111x/LPC11C1x System configuration Table 23. SPI1 clock divider register (SSP1CLKDIV, address 0x4004 809C) bit description Bit Symbol Description Reset value 7:0 DIV SPI1_PCLK clock divider values 0: Disable SPI1_PCLK. 1: Divide by 1. to 255: Divide by 255. 0x00 31:8 - Reserved 0x00 3.5.18 WDT clock source select register This register selects the clock source for the watchdog timer. The WDTCLKUEN register (see Section 3.5.19) must be toggled from LOW to HIGH for the update to take effect. Remark: When switching clock sources, both clocks must be running before the clock source is updated. Table 24. WDT clock source select register (WDTCLKSEL, address 0x4004 80D0) bit description Bit Symbol 1:0 Value SEL Description Reset value WDT clock source 0x00 0x0 Watchdog oscillator 0x3 Reserved - - Main clock 0x2 31:2 IRC oscillator 0x1 Reserved 0x00 3.5.19 WDT clock source update enable register This register updates the clock source of the watchdog timer with the new input clock after the WDTCLKSEL register has been written to. In order for the update to take effect at the input of the watchdog timer, first write a zero to the WDTCLKUEN register and then write a one to WDTCLKUEN. Remark: When switching clock sources, both clocks must be running before the clock source is updated. Table 25. WDT clock source update enable register (WDTCLKUEN, address 0x4004 80D4) bit description Bit Symbol 0 Value ENA Description Reset value Enable WDT clock source update 0x0 0 31:1 - No change 1 Update clock source - Reserved 0x00 3.5.20 WDT clock divider register This register determines the divider values for the watchdog clock wdt_clk. UM10398 UM10398 User manual All information provided in this document is subject to legal disclaimers. Rev. 2 - 2 November 2010 © NXP B.V. 2010. All rights reserved. 23 of 407 UM10398 UM10398 NXP Semiconductors Chapter 3: LPC111x/LPC11C1x System configuration Table 26. WDT clock divider register (WDTCLKDIV, address 0x4004 80D8) bit description Bit Symbol Description Reset value 7:0 DIV WDT clock divider values 0: Disable WDT_PCLK. 1: Divide by 1. to 255: Divide by 255. 0x00 31:8 - Reserved 0x00 3.5.21 CLKOUT clock source select register This register configures the clkout_clk signal to be output on the CLKOUT pin. All three oscillators and the main clock can be selected for the clkout_clk clock. The CLKOUTCLKUEN register (see Section 3.5.22) must be toggled from LOW to HIGH for the update to take effect. Remark: When switching clock sources, both clocks must be running before the clock source is updated. Table 27. CLKOUT clock source select register (CLKOUTCLKSEL, address 0x4004 80E0) bit description Bit Symbol 1:0 Value SEL Description Reset value CLKOUT clock source 0x00 0x0 0x1 Watchdog oscillator 0x3 Main clock - - System oscillator 0x2 31:2 IRC oscillator Reserved 0x00 3.5.22 CLKOUT clock source update enable register This register updates the clock source of the CLKOUT pin with the new clock after the CLKOUTCLKSEL register has been written to. In order for the update to take effect at the input of the CLKOUT pin, first write a zero to the CLKCLKUEN register and then write a one to CLKCLKUEN. Remark: When switching clock sources, both clocks must be running before the clock source is updated. Table 28. CLKOUT clock source update enable register (CLKOUTUEN, address 0x4004 80E4) bit description Bit Symbol 0 Value ENA Description Reset value Enable CLKOUT clock source update 0x0 0 1 31:1 UM10398 UM10398 User manual - No change Update clock source - Reserved All information provided in this document is subject to legal disclaimers. Rev. 2 - 2 November 2010 0x00 © NXP B.V. 2010. All rights reserved. 24 of 407 UM10398 UM10398 NXP Semiconductors Chapter 3: LPC111x/LPC11C1x System configuration 3.5.23 CLKOUT clock divider register This register determines the divider value for the clock output signal on the CLKOUT pin. Table 29. CLKOUT clock divider registers (CLKOUTCLKDIV, address 0x4004 80E8) bit description Bit Symbol 7:0 DIV 31:8 - Value Reset value Clock output divider values 0: Disable CLKOUT. 1: Divide by 1. to 255: Divide by 255. - Description 0x00 Reserved 0x00 3.5.24 POR captured PIO status register 0 The PIOPORCAP0 register captures the state (HIGH or LOW) of the PIO pins of ports 0,1, and 2 (pins PIO2_0 to PIO2_7) at power-on-reset. Each bit represents the reset state of one GPIO pin. This register is a read-only status register. Table 30. POR captured PIO status registers 0 (PIOPORCAP0, address 0x4004 8100) bit description Bit Symbol Description Reset value 11:0 CAPPIO0_n Raw reset status input PIO0_n: PIO0_11 to PIO0_0 User implementation dependent 23:12 CAPPIO1_n Raw reset status input PIO1_n: PIO1_11 to PIO1_0 User implementation dependent 31:24 CAPPIO2_n Raw reset status input PIO2_n: PIO2_7 to PIO2_0 User implementation dependent 3.5.25 POR captured PIO status register 1 The PIOPORCAP1 register captures the state (HIGH or LOW) of the PIO pins of port 2 (PIO2_8 to PIO2_11) and port 3 at power-on-reset. Each bit represents the reset state of one PIO pin. This register is a read-only status register. Table 31. POR captured PIO status registers 1 (PIOPORCAP1, address 0x4004 8104) bit description Bit Symbol Description Reset value 0 CAPPIO2_8 Raw reset status input PIO2_8 User implementation dependent 1 CAPPIO2_9 Raw reset status input PIO2_9 User implementation dependent 2 CAPPIO2_10 Raw reset status input PIO2_10 User implementation dependent 3 User implementation dependent Raw reset status input PIO3_0 User implementation dependent CAPPIO3_1 Raw reset status input PIO3_1 User implementation dependent 6 CAPPIO3_2 Raw reset status input PIO3_2 User implementation dependent 7 CAPPIO3_3 Raw reset status input PIO3_3 User implementation dependent 8 CAPPIO3_4 Raw reset status input PIO3_4 User implementation dependent 9 CAPPIO3_5 Raw reset status input PIO3_5 User implementation dependent 31:10 User manual Raw reset status input PIO2_11 CAPPIO3_0 5 UM10398 UM10398 CAPPIO2_11 4 - Reserved - All information provided in this document is subject to legal disclaimers. Rev. 2 - 2 November 2010 © NXP B.V. 2010. All rights reserved. 25 of 407 UM10398 UM10398 NXP Semiconductors Chapter 3: LPC111x/LPC11C1x System configuration 3.5.26 BOD control register The BOD control register selects four separate threshold values for sending a BOD interrupt to the NVIC and for forced reset. Reset and interrupt threshold values listed in Table 32 are typical values. Table 32. BOD control register (BODCTRL, address 0x4004 8150) bit description Bit Symbol Value Description 1:0 BODRSTLEV Reset value BOD reset level 00 0x0 0x1 Level 1: The reset assertion threshold voltage is 2.06 V; the reset de-assertion threshold voltage is 2.15 V. 0x2 Level 2: The reset assertion threshold voltage is 2.35 V; the reset de-assertion threshold voltage is 2.43 V. 0x3 3:2 Level 0: The reset assertion threshold voltage is 1.46 V; the reset de-assertion threshold voltage is 1.63 V. Level 3: The reset assertion threshold voltage is 2.63 V; the reset de-assertion threshold voltage is 2.71 V. BODINTVAL BOD interrupt level 00 0x0 0x1 Level 1:The interrupt assertion threshold voltage is 2.22 V; the interrupt de-assertion threshold voltage is 2.35 V. 0x2 Level 2: The interrupt assertion threshold voltage is 2.52 V; the interrupt de-assertion threshold voltage is 2.66 V. 0x3 4 Level 0: The interrupt assertion threshold voltage is 1.65 V; the interrupt de-assertion threshold voltage is 1.80 V. Level 3: The interrupt assertion threshold voltage is 2.80 V; the interrupt de-assertion threshold voltage is 2.90 V. BODRSTENA BOD reset enable 0 Enable reset function. - 31:5 - Disable reset function. 1 0 Reserved 0x00 3.5.27 System tick counter calibration register This register determines the value of the SYST_CALIB register (see Table 252). Table 33. System tick timer calibration register (SYSTCKCAL, address 0x4004 8154) bit description Bit Symbol Description Reset value 25:0 CAL System tick timer calibration value 0x04 31:26 - Reserved 0x00 3.5.28 Start logic edge control register 0 The STARTAPRP0 register controls the start logic inputs of ports 0 (PIO0_0 to PIO0_11) and 1 (PIO1_0). This register selects a falling or rising edge on the corresponding PIO input to produce a falling or rising clock edge, respectively, for the start logic (see Section 3.9.2). UM10398 UM10398 User manual All information provided in this document is subject to legal disclaimers. Rev. 2 - 2 November 2010 © NXP B.V. 2010. All rights reserved. 26 of 407 UM10398 UM10398 NXP Semiconductors Chapter 3: LPC111x/LPC11C1x System configuration Every bit in the STARTAPRP0 register controls one port input and is connected to one wake-up interrupt in the NVIC. Bit 0 in the STARTAPRP0 register corresponds to interrupt 0, bit 1 to interrupt 1, etc. (see Table 52), up to a total of 13 interrupts. Remark: Each interrupt connected to a start logic input must be enabled in the NVIC if the corresponding PIO pin is used to wake up the chip from Deep-sleep mode. Table 34. Start logic edge control register 0 (STARTAPRP0, address 0x4004 8200) bit description Bit Symbol Description Reset value 11:0 APRPIO0_n Edge select for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = Falling edge 1 = Rising edge 0x0 12 APRPIO1_0 Edge select for start logic input PIO1_0 0 = Falling edge 1 = Rising edge 0x0 Reserved 0x0 31:13 - 3.5.29 Start logic signal enable register 0 This STARTERP0 register enables or disables the start signal bits in the start logic. The bit assignment is identical to Table 34. Table 35. Start logic signal enable register 0 (STARTERP0, address 0x4004 8204) bit description Bit Symbol Description Reset value 11:0 ERPIO0_n Enable start signal for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = Disabled 1 = Enabled 0x0 12 ERPIO1_0 Enable start signal for start logic input PIO1_0 0 = Disabled 1 = Enabled 0x0 Reserved 0x0 31:13 - 3.5.30 Start logic reset register 0 Writing a one to a bit in the STARTRSRP0CLR register resets the start logic state. The bit assignment is identical to Table 34. The start-up logic uses the input signals to generate a clock edge for registering a start signal. This clock edge (falling or rising) sets the interrupt for waking up from Deep-sleep mode. Therefore, the start-up logic states must be cleared before being used. UM10398 UM10398 User manual All information provided in this document is subject to legal disclaimers. Rev. 2 - 2 November 2010 © NXP B.V. 2010. All rights reserved. 27 of 407 UM10398 UM10398 NXP Semiconductors Chapter 3: LPC111x/LPC11C1x System configuration Table 36. Start logic reset register 0 (STARTRSRP0CLR, address 0x4004 8208) bit description Bit Symbol Description Reset value 11:0 RSRPIO0_n Start signal reset for start logic input PIO0_n:PIO0_11 to PIO0_0 0 = Do nothing. 1 = Writing 1 resets the start signal. n/a 12 RSRPIO1_0 Start signal reset for start logic input PIO1_0 0 = Do nothing. 1 = Writing 1 resets the start signal. n/a 31:13 - Reserved n/a 3.5.31 Start logic status register 0 This register reflects the status of the enabled start signal bits. The bit assignment is identical to Table 34. Each bit (if enabled) reflects the state of the start logic, i.e. whether or not a wake-up signal has been received for a given pin. Table 37. Start logic status register 0 (STARTSRP0, address 0x4004 820C) bit description Bit Symbol Description Reset value 11:0 SRPIO0_n Start signal status for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = No start signal received. 1 = Start signal pending. n/a 12 SRPIO1_0 Start signal status for start logic input PIO1_0 0 = No start signal received. 1 = Start signal pending. n/a 31:13 - Reserved n/a 3.5.32 Deep-sleep mode configuration register This register controls the behavior of the WatchDog (WD) oscillator and the BOD circuit when the device enters Deep-sleep mode. This register must be initialized at least once before entering Deep-sleep mode with one of the four values shown in Table 38: Table 38. Allowed values for PDSLEEPCFG register Configuration WD oscillator on WD oscillator off BOD on PDSLEEPCFG = 0x0000 18B7 PDSLEEPCFG = 0x0000 18F7 BOD off PDSLEEPCFG = 0x0000 18BF PDSLEEPCFG = 0x0000 18FF Remark: Failure to initialize and program this register correctly may result in undefined behavior of the microcontroller. The values listed in Table 38 are the only values allowed for PDSLEEPCFG register. To select the appropriate power configuration for Deep-sleep mode, consider the following: UM10398 UM10398 User manual All information provided in this document is subject to legal disclaimers. Rev. 2 - 2 November 2010 © NXP B.V. 2010. All rights reserved. 28 of 407 UM10398 UM10398 NXP Semiconductors Chapter 3: LPC111x/LPC11C1x System configuration · BOD: Leaving the BOD circuit enabled will protect the part from a low voltage event occurring while the part is in Deep-sleep mode. However, the BOD circuit causes an additional current drain in Deep-sleep mode. · WD oscillator: The watchdog oscillator can be left running in Deep-sleep mode to provide a clock for the watchdog timer or a general purpose timer if they are needed for timing a wake-up event (see Section 3.9.3 for details). In this case, the watchdog oscillator analog output frequency must be set to its lowest value (bits FREQSEL in the WDTOSCCTRL = 0001, see Table 12) and all peripheral clocks other than the timer clock must be disabled in the SYSAHBCLKCTRL register (see Table 20) before entering Deep-sleep mode. The watchdog oscillator, if running, contributes an additional current drain in Deep-sleep mode. Remark: Reserved bits in this register must always be written as indicated. This register must be initialized correctly before entering Deep-sleep mode. Table 39. Deep-sleep configuration register (PDSLEEPCFG, address 0x4004 8230) bit description Bit Symbol 2:0 3 Value Description Reset value NOTUSED Reserved. Always write these bits as 111. 0 BOD_PD BOD power-down control in Deep-sleep mode, see Table 38. 0 0 Powered 1 Powered down 5:4 NOTUSED Reserved. Always write these bits as 11. 0 6 WDTOSC_PD Watchdog oscillator power control in Deep-sleep mode, see Table 38. 0 0 1 Powered Powered down 7 NOTUSED Reserved. Always write this bit as 1. 0 10:8 NOTUSED Reserved. Always write these bits as 000. 0 12:11 NOTUSED Reserved. Always write these bits as 11. 0 31:13 - Reserved 0 0 3.5.33 Wake-up configuration register The bits in this register determine the state the chip enters when it is waking up from Deep-sleep mode. By default, the IRC and flash memory are powered and running and the BOD circuit is enabled when the chip wakes up from Deep-sleep mode. Remark: Reserved bits must be always written as indicated. UM10398 UM10398 User manual All information provided in this document is subject to legal disclaimers. Rev. 2 - 2 November 2010 © NXP B.V. 2010. All rights reserved. 29 of 407 UM10398 UM10398 NXP Semiconductors Chapter 3: LPC111x/LPC11C1x System configuration Table 40. Wake-up configuration register (PDAWAKECFG, address 0x4004 8234) bit description Bit Symbol Value 0 IRCOUT_PD 1 1 IRC_PD Reset value IRC oscillator output wake-up configuration 0 Description 0 Powered Powered down IRC oscillator power-down wake-up configuration 0 Powered 1 3 Powered down 0 2 Powered 1 Powered down FLASH_PD Flash wake-up configuration BOD_PD Powered down ADC_PD ADC wake-up configuration 0 Powered down SYSOSC_PD System oscillator wake-up configuration 0 1 Powered 1 Powered down WDTOSC_PD Watchdog oscillator wake-up configuration 0 1 Powered 1 7 1 Powered 1 6 0 Powered 1 5 0 BOD wake-up configuration 0 4 0 Powered down SYSPLL_PD System PLL wake-up configuration 0 Powered 1 1 Powered down 8 - Reserved. Always write this bit as 1. 1 9 - Reserved. Always write this bit as 0. 0 10 - Reserved. Always write this bit as 1. 1 11 - Reserved. Always write this bit as 1. 1 12 - Reserved. Always write this bit as 0. 0 15:13 - Reserved. Always write these bits as 111. 111 31:16 - Reserved - - 3.5.34 Power-down configuration register The bits in the PDRUNCFG register control the power to the various analog blocks. This register can be written to at any time while the chip is running, and a write will take effect immediately with the exception of the power-down signal to the IRC. To avoid glitches when powering down the IRC, the IRC clock is automatically switched off at a clean point. Therefore, for the IRC a delay is possible before the power-down state takes effect. UM10398 UM10398 User manual All information provided in this document is subject to legal disclaimers. Rev. 2 - 2 November 2010 © NXP B.V. 2010. All rights reserved. 30 of 407 UM10398 UM10398 NXP Semiconductors Chapter 3: LPC111x/LPC11C1x System configuration By default, the IRC and flash memory are powered and running and the BOD circuit is enabled. Remark: Reserved bits must be always written as indicated. Table 41. Power-down configuration register (PDRUNCFG, address 0x4004 8238) bit description Bit Symbol Value 0 IRCOUT_PD Description Reset value IRC oscillator output power-down 0 0 1 1 Powered Powered down IRC_PD IRC oscillator power-down 0 2 Powered 1 Powered down FLASH_PD Flash power-down 0 Powered down BOD_PD BOD power-down 0 Powered down ADC_PD ADC power-down 0 Powered down SYSOSC_PD System oscillator power-down 0 Powered down WDTOSC_PD Watchdog oscillator power-down 0 1 7 1 Powered 1 6 1 Powered 1 5 0 Powered 1 4 0 Powered 1 3 0 SYSPLL_PD 1 Powered Powered down System PLL power-down 0 Powered 1 1 Powered down 8 - Reserved. Always write this bit as 1. 1 9 - Reserved. Always write this bit as 0. 0 10 - Reserved. Always write this bit as 1. 1 11 - Reserved. Always write this bit as 1. 1 12 - Reserved. Always write this bit as 0. 0 15:13 - Reserved. Always write these bits as 111. 111 31:16 - Reserved - - 3.5.35 Device ID register This device ID register is a read-only register and contains the part ID for each LPC111x/LPC11C1x part. This register is also read by the ISP/IAP commands (Section 20.5.11). UM10398 UM10398 User manual All information provided in this document is subject to legal disclaimers. Rev. 2 - 2 November 2010 © NXP B.V. 2010. All rights reserved. 31 of 407 UM10398 UM10398 NXP Semiconductors Chapter 3: LPC111x/LPC11C1x System configuration Table 42. Device ID register (DEVICE_ID, address 0x4004 83F4) bit description Bit Symbol Description Reset value 31:0 DEVICEID Part ID numbers for LPC111x/LPC11C1x parts part-dependent 0x041E 502B = LPC1111FHN33/101 LPC1111FHN33/101 0x2516 902B = LPC1111FHN33/102 LPC1111FHN33/102 0x0416 502B = LPC1111FHN33/201 LPC1111FHN33/201 0x2516 D02B = LPC1111FHN33/202 LPC1111FHN33/202 0x042D 502B = LPC1112FHN33/101 LPC1112FHN33/101 0x2524 D02B = LPC1112FHN33/102 LPC1112FHN33/102 0x0425 502B = LPC1112FHN33/201 LPC1112FHN33/201 0x2524 902B = LPC1112FHN33/202 LPC1112FHN33/202 0x0434 502B = LPC1113FHN33/201 LPC1113FHN33/201 0x2532 902B = LPC1113FHN33/202 LPC1113FHN33/202 0x0434 102B = LPC1113FHN33/301 LPC1113FHN33/301 0x2532 102B = LPC1113FHN33/302 LPC1113FHN33/302 0x0434 102B = LPC1113FBD48/301 LPC1113FBD48/301 0x2532 102B = LPC1113FBD48/302 LPC1113FBD48/302 0x0444 502B = LPC1114FHN33/201 LPC1114FHN33/201 0x2540 902B = LPC1114FHN33/202 LPC1114FHN33/202 0x0444 102B = LPC1114FHN33/301 LPC1114FHN33/301 0x2540 102B = LPC1114FHN33/302 LPC1114FHN33/302 0x0444 102B = LPC1114FBD48/301 LPC1114FBD48/301 0x2540 102B = LPC1114FBD48/302 LPC1114FBD48/302 0x0444 102B = LPC1114FA44/301 LPC1114FA44/301 0x2540 102B = LPC1114FA44/302 LPC1114FA44/302 0x1421 102B = LPC11C12/FBD48/301 LPC11C12/FBD48/301 0x1440 102B = LPC11C14/FBD48/301 LPC11C14/FBD48/301 3.6 Reset Reset has four sources on the LPC111x/LPC11C1x: the RESET pin, Watchdog Reset, Power-On Reset (POR), and Brown Out Detect (BOD). In addition, there is a software reset. The RESET pin is a Schmitt trigger input pin. Assertion of chip Reset by any source, once the operating voltage attains a usable level, starts the IRC causing reset to remain asserted until the external Reset is de-asserted, the oscillator is running, and the flash controller has completed its initialization. On the assertion of a reset source external to the Cortex-M0 CPU (POR, BOD reset, External reset, and Watchdog reset), the following processes are initiated: 1. The IRC starts up. After the IRC-start-up time (maximum of 6 s on power-up), the IRC provides a stable clock output. 2. The boot code in the ROM starts. The boot code performs the boot tasks and may jump to the flash. 3. The flash is powered up. This takes approximately 100 s. Then the flash initialization sequence is started, which takes about 250 cycles. UM10398 UM10398 User manual All information provided in this document is subject to legal disclaimers. Rev. 2 - 2 November 2010 © NXP B.V. 2010. All rights reserved. 32 of 407 UM10398 UM10398 NXP Semiconductors Chapter 3: LPC111x/LPC11C1x System configuration When the internal Reset is removed, the processor begins executing at address 0, which is initially the Reset vector mapped from the boot block. At that point, all of the processor and peripheral registers have been initialized to predetermined values. 3.7 Brown-out detection The LPC111x/LPC11C1x includes four levels for monitoring the voltage on the VDD pin. If this voltage falls below one of the four selected levels, the BOD asserts an interrupt signal to the NVIC. This signal can be enabled for interrupt in the Interrupt Enable Register in the NVIC in order to cause a CPU interrupt; if not, software can monitor the signal by reading the NVIC status register (see Table 52). An additional four threshold levels can be selected to cause a forced reset of the chip (see Table 32). 3.8 Power management The LPC111x/LPC11C1x support a variety of power control features. In Active mode, when the chip is running, power and clocks to selected peripherals can be optimized for power consumption. In addition, there are three special modes of processor power reduction: Sleep mode, Deep-sleep mode, and Deep power-down mode. Remark: The Debug mode is not supported in Sleep, Deep-sleep, or Deep power-down modes. 3.8.1 Active mode In Active mode, the ARM Cortex-M0 core and memories are clocked by the system clock, and peripherals are clocked by the system clock or a dedicated peripheral clock. The chip is in Active mode after reset and the default power configuration is determined by the reset values of the PDRUNCFG and SYSAHBCLKCTRL registers. The power configuration can be changed during run time. 3.8.1.1 Power configuration in Active mode Power consumption in Active mode is determined by the following configuration choices: · The SYSAHBCLKCTRL register controls which memories and peripherals are running (Table 20). · The power to various analog blocks (PLL, oscillators, the ADC, the BOD circuit, and the flash block) can be controlled at any time individually through the PDRUNCFG register (Table 41). · The clock source for the system clock can be selected from the IRC (default), the system oscillator, or the watchdog oscillator (see Figure 3 and related registers). · The system clock frequency can be selected by the SYSPLLCTRL (Table 9) and the SYSAHBCLKDIV register (Table 19). · Selected peripherals (UART, SPI0/1, WDT) use individual peripheral clocks with their own clock dividers. The peripheral clocks can be shut down through the corresponding clock divider registers (Table 21 to Table 23). UM10398 UM10398 User manual All information provided in this document is subject to legal disclaimers. Rev. 2 - 2 November 2010 © NXP B.V. 2010. All rights reserved. 33 of 407 UM10398 UM10398 NXP Semiconductors Chapter 3: LPC111x/LPC11C1x System configuration 3.8.2 Sleep mode In Sleep mode, the system clock to the ARM Cortex-M0 core is stopped, and execution of instructions is suspended until either a reset or an enabled interrupt occurs. Peripheral functions, if selected to be clocked in the SYSAHBCLKCTRL register, continue operation during Sleep mode and may generate interrupts to cause the processor to resume execution. Sleep mode eliminates dynamic power used by the processor itself, memory systems and their related controllers, and internal buses. The processor state and registers, peripheral registers, and internal SRAM values are maintained, and the logic levels of the pins remain static. 3.8.2.1 Power configuration in Sleep mode Power consumption in Sleep mode is configured by the same settings as in Active mode: · The clock remains running. · The system clock frequency remains the same as in Active mode, but the processor is not clocked. · Analog and digital peripherals are selected as in Active mode. 3.8.2.2 Programming Sleep mode The following steps must be performed to enter Sleep mode: 1. The DPDEN bit in the PCON register must be set to zero (Table 47). 2. The SLEEPDEEP bit in the ARM Cortex-M0 SCR register must be set to zero, see (Table 343). 3. Use the ARM Cortex-M0 Wait-For-Interrupt (WFI) instruction. 3.8.2.3 Wake-up from Sleep mode Sleep mode is exited automatically when an interrupt enabled by the NVIC arrives at the processor or a reset occurs. After wake-up due to an interrupt, the microcontroller returns to its original power configuration defined by the contents of the PDRUNCFG and the SYSAHBCLKDIV registers. If a reset occurs, the microcontroller enters the default configuration in Active mode. 3.8.3 Deep-sleep mode In Deep-sleep mode, the system clock to the processor is disabled as in Sleep mode. All analog blocks are powered down, except for the BOD circuit and the watchdog oscillator, which must be selected or deselected during Deep-sleep mode in the PDSLEEPCFG register. Deep-sleep mode eliminates all power used by the flash and analog peripherals and all dynamic power used by the processor itself, memory systems and their related controllers, and internal buses. The processor state and registers, peripheral registers, and internal SRAM values are maintained, and the logic levels of the pins remain static. 3.8.3.1 Power configuration in Deep-sleep mode Power consumption in Deep-sleep mode is determined by the Deep-sleep power configuration setting in the PDSLEEPCFG (Table 39) register: UM10398 UM10398 User manual All information provided in this document is subject to legal disclaimers. Rev. 2 - 2 November 2010 © NXP B.V. 2010. All rights reserved. 34 of 407 UM10398 UM10398 NXP Semiconductors Chapter 3: LPC111x/LPC11C1x System configuration · The only clock source available in Deep-sleep mode is the watchdog oscillator. The watchdog oscillator can be left running in Deep-sleep mode if required for timer-controlled wake-up (see Section 3.9.3). All other clock sources (the IRC and system oscillator) and the system PLL are shut down. The watchdog oscillator analog output frequency must be set to the lowest value of its analog clock output (bits FREQSEL in the WDTOSCCTRL = 0001, see Table 12). · The BOD circuit can be left running in Deep-sleep mode if required by the application. · If the watchdog oscillator is running in Deep-sleep mode, only the watchdog timer or one of the general-purpose timers should be enabled in SYSAHBCLKCTRL register to minimize power consumption. 3.8.3.2 Programming Deep-sleep mode The following steps must be performed to enter Deep-sleep mode: 1. The DPDEN bit in the PCON register must be set to zero (Table 47). 2. Select the power configuration in Deep-sleep mode in the PDSLEEPCFG (Table 39) register. a. If a timer-controlled wake-up is needed, ensure that the watchdog oscillator is powered in the PDRUNCFG register and switch the clock source to WD oscillator in the MAINCLKSEL register (Table 17). b. If no timer-controlled wake-up is needed and the watchdog oscillator is shut down, ensure that the IRC is powered in the PDRUNCFG register and switch the clock source to IRC in the MAINCLKSEL register (Table 17). This ensures that the system clock is shut down glitch-free. 3. Select the power configuration after wake-up in the PDAWAKECFG (Table 40) register. 4. If an external pin is used for wake-up, enable and clear the wake-up pin in the start logic registers (Table 34 to Table 37), and enable the start logic interrupt in the NVIC. 5. In the SYSAHBCLKCTRL register (Table 20), disable all peripherals except counter/timer or WDT if needed. 6. Write one to the SLEEPDEEP bit in the ARM Cortex-M0 SCR register (Table 343). 7. Use the ARM WFI instruction. 3.8.3.3 Wake-up from Deep-sleep mode The microcontroller can wake up from Deep-sleep mode in the following ways: · Signal on an external pin. For this purpose, pins PIO0_0 to PIO0_11 and PIO1_0 can be enabled as inputs to the start logic. The start logic does not require any clocks and generates the interrupt if enabled in the NVIC to wake up from Deep-sleep mode. · Input signal to the start logic created by a match event on one of the general purpose timer external match outputs. The pin holding the timer match function must be enabled as start logic input in the NVIC, the corresponding timer must be enabled in the SYSAHBCLKCTRL register, and the watchdog oscillator must be running in Deep-sleep mode (for details see Section 3.9.3). · Reset from the BOD circuit. In this case, the BOD circuit must be enabled in the PDSLEEPCFG register, and the BOD reset must be enabled in the BODCTRL register (Table 32). UM10398 UM10398 User manual All information provided in this document is subject to legal disclaimers. Rev. 2 - 2 November 2010 © NXP B.V. 2010. All rights reserved. 35 of 407 UM10398 UM10398 NXP Semiconductors Chapter 3: LPC111x/LPC11C1x System configuration · Reset from the watchdog timer. In this case, the watchdog oscillator must be running in Deep-sleep mode (see PDSLEEPCFG register), and the WDT must be enabled in the SYSAHBCLKCTRL register. · A reset signal from the external RESET pin. Remark: If the watchdog oscillator is running in Deep-sleep mode, its frequency determines the wake-up time causing the wake-up time to be longer than waking up with the IRC. 3.8.4 Deep power-down mode In Deep power-down mode, power and clocks are shut off to the entire chip with the exception of the WAKEUP pin. During Deep power-down mode, the contents of the SRAM and registers are not retained except for a small amount of data which can be stored in the five 32-bit general purpose registers of the PMU block. All functional pins are tri-stated in Deep power-down mode except for the WAKEUP pin. 3.8.4.1 Power configuration in Deep power-down mode Deep power-down mode has no configuration options. All clocks, the core, and all peripherals are powered down. Only the WAKEUP pin is powered. 3.8.4.2 Programming Deep power-down mode The following steps must be performed to enter Deep power-down mode: 1. Write one to the DPDEN bit in the PCON register (see Table 47). 2. Store data to be retained in the general purpose registers (Table 48). 3. Write one to the SLEEPDEEP bit in the ARM Cortex-M0 SCR register (Table 343). 4. Ensure that the IRC is powered by setting bits IRCOUT_PD and IRC_PD to zero in the PDRUNCFG register before entering Deep power-down mode. 5. Use the ARM WFI instruction. Remark: The WAKEUP pin must be pulled HIGH externally before entering Deep power-down mode. 3.8.4.3 Wake-up from Deep power-down mode Pulling the WAKEUP pin LOW wakes up the LPC111x/LPC11C1x from Deep power-down, and the chip goes through the entire reset process (Section 3.6). The minimum pulse width for the HIGH-to-LOW transition on the WAKEUP pin is 50 ns. Follow these steps to wake up the chip from Deep power-down mode: 1. A wake-up signal is generated when a HIGH-to-LOW transition occurs externally on the WAKEUP pin with a pulse length of at least 50 ns while the part is in Deep power-down mode. ­ The PMU will turn on the on-chip voltage regulator. When the core voltage reaches the power-on-reset (POR) trip point, a system reset will be triggered and the chip re-boots. UM10398 UM10398 User manual All information provided in this document is subject to legal disclaimers. Rev. 2 - 2 November 2010 © NXP B.V. 2010. All rights reserved. 36 of 407 UM10398 UM10398 NXP Semiconductors Chapter 3: LPC111x/LPC11C1x System configuration ­ All registers except the GPREG0 to GPREG4 will be in their reset state. 2. Once the chip has booted, read the deep power-down flag in the PCON register (Table 47) to verify that the reset was caused by a wake-up event from Deep power-down. 3. Clear the deep power-down flag in the PCON register (Table 47). 4. (Optional) Read the stored data in the general purpose registers (Table 48 and Table 49). 5. Set up the PMU for the next Deep power-down cycle. Remark: The RESET pin has no functionality in Deep power-down mode. 3.9 Deep-sleep mode details 3.9.1 IRC oscillator The IRC is the only oscillator on the LPC111x/LPC11C1x that can always shut down glitch-free. Therefore it is recommended that the user switches the clock source to IRC before the chip enters Deep-sleep mode. 3.9.2 Start logic The Deep-sleep mode is exited when the start logic indicates an interrupt to the ARM core. The port pins PIO0_0 to PIO0_11 and PIO1_1 are connected to the start logic and serve as wake-up pins. The user must program the start logic registers for each input to set the appropriate edge polarity for the corresponding wake-up event. Furthermore, the interrupts corresponding to each input must be enabled in the NVIC. Interrupts 0 to 12 in the NVIC correspond to 13 PIO pins (see Section 3.5.28). The start logic does not require a clock to run because it uses the input signals on the enabled pins to generate a clock edge when enabled. Therefore, the start logic signals should be cleared (see Table 36) before use. The start logic can also be used in Active mode to provide a vectored interrupt using the LPC111x/LPC11C1x's input pins. 3.9.3 Using the general purpose counter/timers to create a self-wake-up event If enabled in Deep-sleep mode through the SYSAHBCLKCFG register, the counter/timers can count clock cycles of the watchdog oscillator and create a match event when the number of cycles equals a preset match value. The match event causes the corresponding match output pin to go HIGH, LOW, or toggle. The state of the match output pin is also monitored by the start logic and can trigger a wake-up interrupt if that pin is enabled in the NVIC and the start logic trigger is configured accordingly in the start logic edge control register (see Table 34). The following steps must be performed to configure the counter/timer and create a timed Deep-sleep self-wake-up event: UM10398 UM10398 User manual All information provided in this document is subject to legal disclaimers. Rev. 2 - 2 November 2010 © NXP B.V. 2010. All rights reserved. 37 of 407 UM10398 UM10398 NXP Semiconductors Chapter 3: LPC111x/LPC11C1x System configuration 1. Configure the port pin as match output in the IOCONFIG block. Select from pins PIO0_1 or PIO0_8 to PIO0_11, which are inputs to the start logic and also hold a match output function. 2. In the corresponding counter/timer, set the match value, and configure the match output for the selected pin. 3. Select the watchdog oscillator to run in Deep-sleep mode in the PDSLEEPCFG register. 4. Switch the clock source to the watchdog oscillator in the MAINCLKSEL register (Table 17) and ensure the watchdog oscillator is powered in the PDRUNCFG register. 5. Enable the pin, configure its edge detect function, and reset the start logic in the start logic registers (Table 34 to Table 37), and enable the interrupt in the NVIC. 6. Disable all other peripherals in the SYSAHBCLKCTRL register. 7. Ensure that the DPDEN bit in the PCON register is set to zero (Table 47). 8. Write one to the SLEEPDEEP bit in the ARM Cortex-M0 SCR register (Table 343). 9. Start the counter/timer. 10. Use the ARM WFI instruction to enter Deep-sleep mode. 3.10 System PLL functional description The LPC111x/LPC11C1x uses the system PLL to create the clocks for the core and peripherals. irc_osc_clk FCLKIN sys_osc_clk pd FCCO PSEL PFD 2 SYSPLLCLKSEL pd LOCK DETECT LOCK cd /2P FCLKOUT analog section pd cd /M 5 MSEL Fig 4. System PLL block diagram The block diagram of this PLL is shown in Figure 4. The input frequency range is 10 MHz to 25 MHz. The input clock is fed directly to the Phase-Frequency Detector (PFD). This block compares the phase and frequency of its inputs, and generates a control signal when phase and/ or frequency do not match. The loop filter filters these control signals and drives the current controlled oscillator (CCO), which generates the main clock and optionally two additional phases. The CCO frequency range is 156 MHz to UM10398 UM10398 User manual All information provided in this document is subject to legal disclaimers. Rev. 2 - 2 November 2010 © NXP B.V. 2010. All rights reserved. 38 of 407 UM10398 UM10398 NXP Semiconductors Chapter 3: LPC111x/LPC11C1x System configuration 320 MHz.These clocks are either divided by 2×P by the programmable post divider to create the output clock(s), or are sent directly to the output(s). The main output clock is then divided by M by the programmable feedback divider to generate the feedback clock. The output signal of the phase-frequency detector is also monitored by the lock detector, to signal when the PLL has locked on to the input clock. Remark: The divider values for P and M must be selected so that the PLL output clock frequency FCLKOUT is lower than 100 MHz. 3.10.1 Lock detector The lock detector measures the phase difference between the rising edges of the input and feedback clocks. Only when this difference is smaller than the so called "lock criterion" for more than eight consecutive input clock periods, the lock output switches from low to high. A single too large phase difference immediately resets the counter and causes the lock signal to drop (if it was high). Requiring eight phase measurements in a row to be below a certain figure ensures that the lock detector will not indicate lock until both the phase and frequency of the input and feedback clocks are very well aligned. This effectively prevents false lock indications, and thus ensures a glitch free lock signal. 3.10.2 Power-down control To reduce the power consumption when the PLL clock is not needed, a Power-down mode has been incorporated. This mode is enabled by setting the SYSPLL_PD bits to one in the Power-down configuration register (Table 41). In this mode, the internal current reference will be turned off, the oscillator and the phase-frequency detector will be stopped and the dividers will enter a reset state. While in Power-down mode, the lock output will be low to indicate that the PLL is not in lock. When the Power-down mode is terminated by setting the SYSPLL_PD bits to zero, the PLL will resume its normal operation and will make the lock signal high once it has regained lock on the input clock. 3.10.3 Divider ratio programming Post divider The division ratio of the post divider is controlled by the PSEL bits. The division ratio is two times the value of P selected by PSEL bits as shown in Table 9. This guarantees an output clock with a 50% duty cycle. Feedback divider The feedback divider's division ratio is controlled by the MSEL bits. The division ratio between the PLL's output clock and the input clock is the decimal value on MSEL bits plus one, as specified in Table 9. Changing the divider values Changing the divider ratio while the PLL is running is not recommended. As there is no way to synchronize the change of the MSEL and PSEL values with the dividers, the risk exists that the counter will read in an undefined value, which could lead to unwanted spikes or drops in the frequency of the output clock. The recommended way of changing between divider settings is to power down the PLL, adjust the divider settings and then let the PLL start up again. UM10398 UM10398 User manual All information provided in this document is subject to legal disclaimers. Rev. 2 - 2 November 2010 © NXP B.V. 2010. All rights reserved. 39 of 407 UM10398 UM10398 NXP Semiconductors Chapter 3: LPC111x/LPC11C1x System configuration 3.10.4 Frequency selection The PLL frequency equations use the following parameters (also see Figure 3): Table 43. PLL frequency parameters Parameter System PLL FCLKIN Frequency of sys_pllclkin (input clock to the system PLL) from the SYSPLLCLKSEL multiplexer (see Section 3.5.9). FCCO Frequency of the Current Controlled Oscillator (CCO); 156 to 320 MHz. FCLKOUT Frequency of sys_pllclkout. FCLKOUT must be < 100 MHz. P System PLL post divider ratio; PSEL bits in SYSPLLCTRL (see Section 3.5.3). M System PLL feedback divider register; MSEL bits in SYSPLLCTRL (see Section 3.5.3). 3.10.4.1 Normal mode In normal mode the post divider is enabled, giving a 50% duty cycle clock with the following frequency relations: (1) FCLKOUT = M × FCLKIN = ( FCCO ) / ( 2 × P ) To select the appropriate values for M and P, it is recommended to follow these steps: 1. Specify the input clock frequency FCLKIN. 2. Calculate M to obtain the desired output frequency FCLKOUT with M = FCLKOUT / FCLKIN. 3. Find a value so that FCCO = 2 × P × FCLKOUT. 4. Verify that all frequencies and divider values conform to the limits specified in Table 9. 5. Ensure that FCLKOUT < 100 MHz. Table 44 shows how to configure the PLL for a 12 MHz crystal oscillator using the SYSPLLCTRL register (Table 9). The main clock is equivalent to the system clock if the system clock divider SYSAHBCLKDIV is set to one (see Table 19). Table 44. PLL configuration examples PLL input clock sys_pllclkin (FCLKIN) Main clock (FCLKOUT) MSEL bits M divider PSEL bits Table 9 value Table 9 P divider value FCCO frequency 12 MHz 48 MHz 00011 4 01 2 192 MHz 12 MHz 36 MHz 00010 3 10 4 288 MHz 12 MHz 24 MHz 00001 2 10 4 192 MHz 3.10.4.2 Power-down mode In this mode, the internal current reference is turned off, the oscillator and the phase-frequency detector are stopped, and the dividers enter a reset state. While in Power-down mode, the lock output is be LOW to indicate that the PLL is not in lock. When UM10398 UM10398 User manual All information provided in this document is subject to legal disclaimers. Rev. 2 - 2 November 2010 © NXP B.V. 2010. All rights reserved. 40 of 407 UM10398 UM10398 NXP Semiconductors Chapter 3: LPC111x/LPC11C1x System configuration the Power-down mode is terminated by setting the SYSPLL_PD bit to zero in the Power-down configuration register (Table 41), the PLL resumes its normal operation and asserts the lock signal HIGH once it has regained lock on the input clock. 3.11 Flash memory access Depending on the system clock frequency, access to the flash memory can be configured with various access times by writing to the FLASHCFG register at address 0x4003 C010. This register is part of the flash configuration block (see Figure 2). Remark: Improper setting of this register may result in incorrect operation of the LPC111x/LPC11C1x flash memory. Table 45. Flash configuration register (FLASHCFG, address 0x4003 C010) bit description Bit Symbol Value Description 1:0 FLASHTIM Reset value Flash memory access time. FLASHTIM +1 is equal to the number of system clocks used for flash access. 10 00 01 User manual 3 system clocks flash access time (for system clock frequencies of up to 50 MHz). 11 UM10398 UM10398 2 system clocks flash access time (for system clock frequencies of up to 40 MHz). 10 31:2 - 1 system clock flash access time (for system clock frequencies of up to 20 MHz). Reserved. - Reserved. User software must not change the value of these bits. Bits 31:2 must be written back exactly as read. All information provided in this document is subject to legal disclaimers. Rev. 2 - 2 November 2010 © NXP B.V. 2010. All rights reserved. 41 of 407 UM10398 UM10398 Chapter 4: LPC111x/LPC11C1x PMU (Power Management Unit) Rev. 2 - 2 November 2010 User manual 4.1 How to read this chapter Remark: For parts LPC111x/102/202/302, also refer to Chapter 5 for power control. 4.2 Introduction The PMU controls the Deep power-down mode. Four general purpose register in the PMU can be used to retain data during Deep power-down mode. 4.3 Register description Table 46. Register overview: PMU (base address 0x4003 8000) Name Access Address offset Description Reset value PCON R/W 0x000 Power control register 0x0 GPREG0 R/W 0x004 General purpose register 0 0x0 GPREG1 R/W 0x008 General purpose register 1 0x0 GPREG2 R/W 0x00C General purpose register 2 0x0 GPREG3 R/W 0x010 General purpose register 3 0x0 GPREG4 R/W 0x014 General purpose register 4 0x0 4.3.1 Power control register The power control register selects whether one of the ARM Cortex-M0 controlled power-down modes (Sleep mode or Deep-sleep mode) or the Deep power-down mode is entered and provides the flags for Sleep or Deep-sleep modes and Deep power-down modes respectively. See Section 3.8 for details on how to enter the power-down modes. Table 47. Bit Power control register (PCON, address 0x4003 8000) bit description Symbol Value 0 - - 1 DPDEN Description Reset value Reserved. Do not write 1 to this bit. 0x0 Deep power-down mode enable 0 0 1 7:2 UM10398 UM10398 User manual - ARM WFI will enter Sleep or Deep-sleep mode (clock to ARM Cortex-M0 core turned off). ARM WFI will enter Deep-power down mode (ARM Cortex-M0 core powered-down). - Reserved. Do not write ones to this bit. All information provided in this document is subject to legal disclaimers. Rev. 2 - 2 November 2010 0x0 © NXP B.V. 2010. All rights reserved. 42 of 407 UM10398 UM10398 NXP Semiconductors Chapter 4: LPC111x/LPC11C1x PMU (Power Management Unit) Table 47. Power control register (PCON, address 0x4003 8000) bit description .continued Bit Symbol Value 8 SLEEPFLAG Description Reset value Sleep mode flag 0 0 1 0x0 Deep power-down flag 0x0 Read: Deep power-down mode not entered. Write: No effect. 0x0 1 Read: Deep power-down mode entered. Write: Clear the Deep power-down flag. 0x0 - 11 Reserved. Do not write ones to this bit. 0 - Read: Sleep/Deep-sleep or Deep power-down mode entered. Write: Writing a 1 clears the SLEEPFLAG bit to 0. - 10:9 Read: No power-down mode entered. LPC111x/LPC11C1x is in Active mode. Write: No effect. Reserved. Do not write ones to this bit. 0x0 DPDFLAG 31:12 - 4.3.2 General purpose registers 0 to 3 The general purpose registers retain data through the Deep power-down mode when power is still applied to the VDD pin but the chip has entered Deep power-down mode. Only a "cold" boot when all power has been completely removed from the chip will reset the general purpose registers. Table 48. General purpose registers 0 to 3 (GPREG0 - GPREG3, address 0x4003 8004 to 0x4003 8010) bit description Bit Symbol Description Reset value 31:0 GPDATA Data retained during Deep power-down mode. 0x0 4.3.3 General purpose register 4 The general purpose register 4 retains data through the Deep power-down mode when power is still applied to the VDD pin but the chip has entered Deep power-down mode. Only a "cold" boot, when all power has been completely removed from the chip, will reset the general purpose registers. Remark: If there is a possibility that the external voltage applied on pin VDD drops below 2.2 V during Deep power-down, the hysteresis of the WAKEUP input pin has to be disabled in this register before entering Deep power-down mode in order for the chip to wake up. Table 49. General purpose register 4 (GPREG4, address 0x4003 8014) bit description Bit User manual Value Description Reset value 9:0 UM10398 UM10398 Symbol - - Reserved. Do not write ones to this bit. 0x0 All information provided in this document is subject to legal disclaimers. Rev. 2 - 2 November 2010 © NXP B.V. 2010. All rights reserved. 43 of 407 UM10398 UM10398 NXP Semiconductors Chapter 4: LPC111x/LPC11C1x PMU (Power Management Unit) Table 49. General purpose register 4 (GPREG4, address 0x4003 8014) bit description Bit Symbol Value 10 WAKEUPHYS Description Reset value WAKEUP pin hysteresis enable 0x0 1 31:11 GPDATA Hysteresis for WAKEUP pin enabled. 0 Hysteresis for WAKUP pin disabled. Data retained during Deep power-down mode. 0x0 4.4 Functional description For details of entering and exiting Deep power-down mode, see Section 3.8.4. UM10398 UM10398 User manual All information provided in this document is subject to legal disclaimers. Rev. 2 - 2 November 2010 © NXP B.V. 2010. All rights reserved. 44 of 407 UM10398 UM10398 Chapter 5: LPC111x/102/202/302 Power profiles Rev. 2 - 2 November 2010 User manual 5.1 How to read this chapter The power profiles are available for parts LPC111x/102/202/302 only (LPC1100L LPC1100L series). 5.2 Features · Includes ROM-based application services · Power Management services · Clocking services 5.3 Description This chapter describes calls that applications can make to code that is included in on-chip ROM to facilitate power management and clocking setup. 5.4 Definitions The following elements have to be defined in an application that uses the power profiles: typedef struct _PWRD { void (*set_pll)(unsigned int cmd[], unsigned int resp[]); void (*set_power)(unsigned int cmd[], unsigned int resp[]); } PWRD; typedef struct _ROM { const PWRD * pWRD; } ROM; ROM * rom = (ROM *) 0x1FFF1FF8; unsigned int command[4], result[2]; 5.5 Clocking routine 5.5.1 set_pll This routine sets up the system PLL according to the calling arguments. If the expected clock can be obtained by simply dividing the system PLL input, set_pll bypasses the PLL to lower system power consumption. IMPORTANT: Before this routine is invoked, the PLL clock source (IRC/system oscillator) must be selected (Table 15), the main clock source must be set to the input clock to the system PLL (Table 17) and the system/AHB clock divider must be set to 1 (Table 19). UM10398 UM10398 User manual All information provided in this document is subject to legal disclaimers. Rev. 2 - 2 November 2010 © NXP B.V. 2010. All rights reserved. 45 of 407 UM10398 UM10398 NXP Semiconductors Chapter 5: LPC111x/102/202/302 Power profiles set_pll attempts to find a PLL setup that matches the calling parameters. Once a combination of a feedback divider value (SYSPLLCTRL, M), a post divider ratio (SYSPLLCTRL, P) and the system/AHB clock divider (SYSAHBCLKDIV) is found, set_pll applies the selected values and switches the main clock source selection to the system PLL clock out (if necessary). The routine returns a result code that indicates if the system PLL was successfully set (PLL_CMD_SUCCESS) or not (in which case the result code identifies what went wrong). The current system frequency value is also returned. The application should use this information to adjust other clocks in the device (the SSP, UART, and WDT clocks, and/or clockout). Table 50. set_pll routine Routine set_pll Input Param0: system PLL input frequency (in kHz) Param1: expected system clock (in kHz) Param2: mode (CPU_FREQ_EQU, CPU_FREQ_LTE, CPU_FREQ_GTE, CPU_FREQ_APPROX) Param3: system PLL lock timeout Result Result0: PLL_CMD_SUCCESS | PLL_INVALID_FREQ | PLL_INVALID_MODE | PLL_FREQ_NOT_FOUND | PLL_NOT_LOCKED Result1: system clock (in kHz) The following definitions are needed when making set_pll power routine calls: /* set_pll #define #define #define #define /* set_pll #define #define #define #define #define mode options */ CPU_FREQ_EQU CPU_FREQ_LTE CPU_FREQ_GTE CPU_FREQ_APPROX result0 options */ PLL_CMD_SUCCESS PLL_INVALID_FREQ PLL_INVALID_MODE PLL_FREQ_NOT_FOUND PLL_NOT_LOCKED 0 1 2 3 0 1 2 3 4 5.5.1.1 System PLL input frequency and expected system clock set_pll looks for a setup in which the system PLL clock does not exceed 50 MHz. It easily finds a solution when the ratio between the expected system clock and the system PLL input frequency is an integer value, but it can also find solutions in other cases. The system PLL input frequency (Param0) must be between 10000 to 25000 kHz (10 MHz to 25 MHz) inclusive. The expected system clock (Param1) must be between 1 and 50000 kHz inclusive. If either of these requirements is not met, set_pll returns PLL_INVALID_FREQ and returns Param0 as Result1 since the PLL setting is unchanged. UM10398 UM10398 User manual All information provided in this document is subject to legal disclaimers. Rev. 2 - 2 November 2010 © NXP B.V. 2010. All rights reserved. 46 of 407 UM10398 UM10398 NXP Semiconductors Chapter 5: LPC111x/102/202/302 Power profiles 5.5.1.2 Mode The first priority of set_pll is to find a setup that generates the system clock at exactly the rate specified in Param1. If it is unlikely that an exact match can be found, input parameter mode (Param2) should be used to specify if the actual system clock can be less than or equal, greater than or equal or approximately the value specified as the expected system clock (Param1). A call specifying CPU_FREQ_EQU will only succeed if the PLL can output exactly the frequency requested in Param1. CPU_FREQ_LTE can be used if the requested frequency should not be exceeded (such as overall current consumption and/or power budget reasons). CPU_FREQ_GTE helps applications that need a minimum level of CPU processing capabilities. CPU_FREQ_APPROX results in a system clock that is as clos