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TTL-LOGIC-DATABOOK Texas Instruments TTL-LOGIC-DATABOOK visit Texas Instruments
SN74LS138NSRG4 Texas Instruments 3-line to 8-line decoder / demultiplexer 16-SO 0 to 70 visit Texas Instruments
SN74LS138DG4 Texas Instruments 3-line to 8-line decoder / demultiplexer 16-SOIC 0 to 70 visit Texas Instruments
SN74LS138DR Texas Instruments 3-line to 8-line decoder / demultiplexer 16-SOIC 0 to 70 visit Texas Instruments Buy
SN74LS138DRE4 Texas Instruments 3-line to 8-line decoder / demultiplexer 16-SOIC 0 to 70 visit Texas Instruments
SN74LS138DRG4 Texas Instruments 3-line to 8-line decoder / demultiplexer 16-SOIC 0 to 70 visit Texas Instruments

LOGIC OF 74LS138

Catalog Datasheet MFG & Type PDF Document Tags

pin diagram of ic 74ls138

Abstract: 74LS138 pin configuration Signetics 74LS138, S138 Decoders/Demultiplexers 1-Of-8 Decoder/Demultiplexer Product Specification Logic Products FEATURES · Demultiplexing capability · Multiple input enable for easy expansion · Ideal for memory chip select decoding · Direct replacement for Intel 3205 TYPE 74LS138 74S138 , Decoders/Demultiplexers 74LS138, S138 LOGIC DIAGRAM *2 A1 *© *1 *2 63 LD01M0S ( ) - Pin number , 5-231 Signetics Logic Products Product Specification Decoders/Demultiplexers 74LS138, S138
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pin diagram of ic 74ls138 74LS138 pin configuration ic 74ls138 74LS138 pin diagram 74ls138 function LOGIC OF 74LS138 N74S13BN N74LS138N N74LS138D N74S138D 1N916 1N3064

CI 74LS138

Abstract: 74LS138 pin configuration HIGH or active LOW state. 74LS138, S138 Decoders/Demultiplexers 1-Of-8 Decoder/Demultiplexer Product , Signetics Logic Products FEATURES â'¢ Demultiplexing capability â'¢ Multiple input enable , HIGH. This multiple enable function allows easy parallel expansion of the device to a 1 -of-32 (5 lines , output demultiplexer by using one of the active LOW Enable inputs as the Data input and the remaining , LOGIC SYMBOL *oU m vcc *i E ü]ö0 *2 Å' 230, ïiÅ' 13] ô2 ï2 (t «JSa e3[I ID 54 ôvq
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CI 74LS138 TTL 74ls138 74 LS 138 DECODER intel 3205 74l5138 of 74LS138 3 to 8 decoder N74S138N

LOGIC OF 74LS138

Abstract: pin for 74LS138 Signetics 74LS138, S138 Decoders/Demultiplexers 1-Of-8 Decoder/Demultiplexer Product Specification Logic Products FEATURES â'¢ Demultiplexing capability â'¢ Multiple input enable for easy , Decoders/Demultiplexers 74LS138, S138 LOGIC DIAGRAM a2 a, aq e, e2 e3 LD01à ( ) = Pin number Vcc - P , . This multiple enable function allows easy parallel expansion of the device to a 1-of-32 (5 lines to 32 , demultiplexer by using one of the active LOW Enable inputs as the Data input and the remaining Enable inputs as
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pin for 74LS138 74LS138 3 to 8 decoder notes 74LS138 pins 74LS138 3 to 8 decoder Pin 74l513 74LS

LOGIC OF 74LS138

Abstract: 74LS138 pin configuration Signetics 74LS138, S138 Decoders/Demultiplexers 1-Of-8 Decoder/Demultiplexer Product Specification Logic Products FEATURES · Demultiplexing capability · Multiple input enable for easy expansion · Ideal for memory chip select decoding · Direct replacement for Intel 3205 TYPE 74LS138 74S138 , Decoders/Demultiplexers 74LS138, S138 LOGIC DIAGRAM A2 A0 Ei E2 E3 L C O IS fe O S ( } = Pin , and E3 is HIGH. This multiple enable function al lows easy parallel expansion of the de vice to a 1-of
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74LS138 3 to pin configuration

FUNCTIONAL APPLICATION OF 74LS138

Abstract: 74LS138 3 to 8 decoder Pin input function is in the disable state, all eight Y outputs are HIGH regardless of the A, B and C select inputs. The Am54LS/74LS138 is a standard performance version of the Am25LS138. See appropriate , Am25LS138 â'¢ Am54LS/74LS138 3-Line To 8-Line Decoder/Demultiplexer DISTINCTIVE , â'" 440|UA source current â'¢ 100% product assurance screening to MIL-STD-883 requirements LOGIC , that are decoded to one of eight Y outputs. One active-HIGH and two active-LOW enables can be used for
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FUNCTIONAL APPLICATION OF 74LS138 LOGIC DESCRIPTION OF 74LS138 74ls138 3-8 74LS138 application note decoder 1 to 16 LS 74LS138 25LS138 54LS/74LS138 LS/54 LS/74LS138 54LS/74LS

74ls138 truth table

Abstract: 74LS138 (g) MOTOROLA 1-0F-8 DECODER/ DEMULTIPLEXER The LSTTL/MSI SN54/74LS138 is a high speed 1-of , AND LS TTL DATA SN54/74LS138 FUNCTIONAL DESCRIPTION The LS138 is a high speed 1-of-8 Decoder , decoding. The multiple input enables allow parallel ex pansion to a 1-of-24 decoder using just three LS138 devices or to a 1-of-32 decoder using four LS138s and one inverter. The LS138 is fabricated with the , Dissipation of 32 mW Active Low Mutually Exclusive Outputs Input Clamp Diodes Limit High Speed Termination
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74ls138 truth table connection for 74LS138 demultiplexer 3 to 8 truth table 74ls138 demultiplexer Truth table of 1 to 16 demultiplexer SN5474LS138 SN54/74LS138 751B-03 SN54LSXXXJ SN74LSXXXN SN74LSXXXD

74LS138

Abstract: 74LS138 3 to 8 decoder Pin SN54/74LS138 1-OF-8 DECODER/ DEMULTIPLEXER The LSTTL / MSI SN54 / 74LS138 is a high speed 1-of , decoding. The multiple input enables allow parallel expansion to a 1-of-24 decoder using just three LS138 devices or to a 1-of-32 decoder using four LS138s and one inverter. The LS138 is fabricated with the , . · · · · · 1-OF-8 DECODER / DEMULTIPLEXER LOW POWER SCHOTTKY Demultiplexing Capability Multiple Input Enable for Easy Expansion Typical Power Dissipation of 32 mW Active Low Mutually Exclusive
Motorola
Original
motorola 74ls138 74LS138 DATASHEET 74LS138 1 to 8 decoder notes demultiplexer 74LS138

74LS00

Abstract: 74LS00 TTL such chip is the 74LS138 3-to-8 decoder which is capable of handling four HCTL-1100s. Read , subroutine overhead. The HCTL-1100 bus interface circuit is capable of supporting four HCTL-1100s with no additional logic. If an I/O port based design requires more than one HCTL-1100, the interface The choice of which interface is most appropriate for your application should be based on whether or not your , glue logic. Bus Interface The I/O routines are slightly more complicated for the I/O interface than
Hewlett-Packard
Original
HCTL1100 CS1100 RD1100 WR1100 74LS00 74LS00 TTL TTL 74ls00 3 to 8 line decoder using 8051 8051s M-015 HCTL-1100/8051 OE1100 6000H

3 to 8 line decoder using 8051

Abstract: 74LS00 circuit is capable of supporting four HCTL-1100s with no additional logic. If an I/ O port based design , chip could be used. One such chip is the 74LS138 3-to-8 decoder which is capable of handling four , -1100 and the second approach uses the 8051's I/O ports to communicate with the HCTL-1100. The choice of , port interface. The I/O interface requires no additional glue logic. The I/O routines are slightly , . These lines would control OE (Output Enable) and CS (Chip Select) for each of the individual HCTL
Avago Technologies
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74LS00 DATA HCTL-1100 M-015 HCTL-1100s 74LS00 application 8051 reset circuit m015 hctl 5964-3776E

block diagram of 74LS138 3 to 8 decoder

Abstract: block diagram of 74LS138 1 line to 16 line GD54/74LS138 3-TO-8-LINE DECODERS/DEMULTIPLEXERS Feature â'¢ Designed Specifically for High , used to minimize the effects of system decoding. When employed with high-speed memories utilizing a fast enable circuit the delay times of this decoder and the enable time of the memory are usually less than the typical access times of the memory. This means that the effective system delay introduced by , Diagram and Logic Absolute Maximum Ratings â'¢ Supply voltage, Vcc
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block diagram of 74LS138 3 to 8 decoder block diagram of 74LS138 1 line to 16 line 74LS138 3 to 8 16-LINE 54LS decorder 3 line to 8 line GD54/74LS138

and gate 74LS138

Abstract: SP74HCT138N with 74LS138 â  SPI CMOS technology â  Full TTL interface capability â  High noise immunity â , process: a silicon gate (with oxide isolation) complementary MOS technology. This provides the features of , pin compatibility with the 74LS138. Speeds are comparable to the low power Schottky device family , '"1 ^ â'" 770 [19 5581 MAX T " 7WWÃ O LOGIC DIAGRAM FUNCTION TABLE â¡ ATA OUTPUTS INPUTS , an appropriate logic voltage level (either Vcc or GND). Symbol Parameter Conditions TA = 25Â
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SP74HCT138 SP74HCT138N SP74HCT138J and gate 74LS138 74LS138 pin SP74HCT

l381

Abstract: 74ls138 function 74LS138 â  SPI CMOS technology â  Full TTL interface capability â  High noise immunity â  Low , silicon gate {with oxide isolation) complementary MOS technology. This provides the features of , pin compatibility with the 74LS138. Speeds are comparable to the low power Schottky device family , '"\ LOGIC DIAGRAM FUNCTION TABLE DATA OUTPUTS INPUTS OUTPUTS ENABLE SELECT G1 , appropriate logic voltage level (either Vcc or GND). Parameter Conditions SP74SC138 Unit Min. Typ. Max
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SP74SC138N SP74SC138F l381 pin diagram demultiplexer 74LS138 400//A

D133

Abstract: 74LS42 Delay ns (Typ) Power Dissipation mW (Typ) Fan-Out (UL)* Logic/Connection Diagram Package(s) 1 1 -of , D135 4L,6B,9B 5 1 -of-8 54LS/74LS42 3 1 8 â'" 17 17 35 5.0 D135 4L,6B,9B 6 1-of-8 54LS/74LS138 3 3 8 , FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL-TTL D130 54/74190, 74LS190 54/74191, 74LS191 0131 , 1 23456 79 10 11 Vcc = Pin 16 GND = Pin 8 D136 54S/74S138, 54LS/74LS138 1 2 3 4 5C â Iii- e , ) Enable Delay ns (Typ) Data Delay ns (Typ) Power Dissipation mW (Typ) Fan-Out (UL)(2) Logic/Connection
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93L21 93L01 93L11 D133 74LS42 D135 74ls139 TTL 9334 7442 pin diagram 54/74S139 54LS/74LS139 54LS/74LS155 54LS/74LS156

74LS138 3 to 8 decoder notes

Abstract: 74LS138 DATASHEET SN54/74LS138 1-OF-8 DECODER/ DEMULTIPLEXER The LSTTL / MSI SN54 / 74LS138 is a high speed 1-of , /74LS138 FUNCTIONAL DESCRIPTION The LS138 is a high speed 1-of-8 Decoder/Demultiplexer fabricated with , decoding. The multiple input enables allow parallel expansion to a 1-of-24 decoder using just three LS138 devices or to a 1-of-32 decoder using four LS138s and one inverter. The LS138 is fabricated with the , . · · · · · 1-OF-8 DECODER/ DEMULTIPLEXER LOW POWER SCHOTTKY Demultiplexing Capability
Motorola
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74LS138 data sheet LS138 Motorola 74LS138 decoder LS04

74LS190 PIN diagram

Abstract: ttl 7442 (UL)* Logic/Connection Diagram Package(s) 1 1 -of-8 93L34 3 1 8 â'" 46 30 70 5.0 D134 4L,7B,9B 2 1-of-8 S4LS/74LS2S9 3 1 8 â'" 30 19 60 5.0 D134 4L,6B,9B 3 1 -of-8 54/7445 3 1 8 30 40 40 215 80mA D135 4L,7B , 5.0 D135 4L,6B,9B 6 1-of-8 54LS/74LS138 3 3 8 â'" 22 21 34 5.0 D136 4L,6B,9B 7 1-of-8 54S/74S138 3 3 , FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL-TTL D130 54/74190, 74LS190 54/74191, 74LS191 0131 , 1 23456 79 10 11 Vcc = Pin 16 GND = Pin 8 D136 54S/74S138, 54LS/74LS138 1 2 3 4 5C â Iii- e
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74LS190 PIN diagram ttl 7442 D134 74145 7443 ttl PIN 74LS42 54LS/74LS259 54LS/74LS145 93S138 93S137

74191 8 bit

Abstract: 7443 Flip-Flop (UL)* Logic/Connection Diagram Package(s) 1 1 -of-8 93L34 3 1 8 â'" 46 30 70 5.0 D134 4L,7B,9B 2 1-of-8 S4LS/74LS2S9 3 1 8 â'" 30 19 60 5.0 D134 4L,6B,9B 3 1 -of-8 54/7445 3 1 8 30 40 40 215 80mA D135 4L,7B , 5.0 D135 4L,6B,9B 6 1-of-8 54LS/74LS138 3 3 8 â'" 22 21 34 5.0 D136 4L,6B,9B 7 1-of-8 54S/74S138 3 3 , FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL-TTL D130 54/74190, 74LS190 54/74191, 74LS191 0131 , 1 23456 79 10 11 Vcc = Pin 16 GND = Pin 8 D136 54S/74S138, 54LS/74LS138 1 2 3 4 5C â Iii- e
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74191 8 bit 7443 Flip-Flop 7443 d Flip-Flop 9B23 74155 D130 54LS/74LS298 93L08 54LS/74LS256 54S/74S174 54LS/74LS174

sn74ls138n

Abstract: LS138 texas -1-260C-UNLIM 0 to 70 74LS138 SN74LS138NSR ACTIVE SO NS 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 74LS138 SN74LS138NSRE4 ACTIVE SO NS 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 74LS138 , -1-260C-UNLIM 0 to 70 74LS138 SN74LS138NSRG4 ACTIVE SO NS 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 74LS138 SN74LS138NSRG4 ACTIVE SO NS 16
Texas Instruments
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sn74ls138n LS138 texas SNJ54LS 138FK 7600501EA SNJ54LS138J 7600501FA SNJ54LS138W
Abstract: SN74LS138N SN74LS138N 74LS138 74LS138 74LS138 74LS138 74LS138 74LS138 S138A S138A S138A SN74S138AN , discontinued the production of the device. Addendum-Page 5 PACKAGE OPTION ADDENDUM www.ti.com 25 , Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do , is indented then it is a continuation of the previous line and the two combined represent the entire , page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge Texas Instruments
Original
SNJ54S 7604101EA SNJ54S138J 7604101FA SNJ54S138W JM38510/

transistor d133

Abstract: Decoder BCD 7 seg ns (Typ) Power Dissipation mW (Typ) Fan-Out (UL)* Logic/Connection Diagram Package(s) 1 1 -of , D135 4L,6B,9B 5 1 -of-8 54LS/74LS42 3 1 8 â'" 17 17 35 5.0 D135 4L,6B,9B 6 1-of-8 54LS/74LS138 3 3 8 , FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL-TTL D130 54/74190, 74LS190 54/74191, 74LS191 0131 , 1 23456 79 10 11 Vcc = Pin 16 GND = Pin 8 D136 54S/74S138, 54LS/74LS138 1 2 3 4 5C â Iii- e , 0 â > Q 01 o _i 'in "3T Ol n je o
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transistor d133 Decoder BCD 7 seg transistor 6B 7-seg ANODE COMMON 75491 7SEG COM ANODE 9317B 9317C 54LS/74LS47 54LS/74LS48 54LS/74LS49

pin diagram of ic 74ls138

Abstract: connection diagram of ic 74ls138 Performance SN 5 4 LS 1 38 , S N 54S 138 . . . J OR W PACKAG E SN 74LS138, SN 74S138A . D OR N P A C K A G , to minimize the effects of system decoding. When employed with high speed memories utilizing a fast enable circuit, the delay times of these decoders and the enable time of the memory are usually less than the typical access time of the memory. Th is means that the effective system delay introduced by the , of eight lines dependent on the conditions at the three binary select inputs and the three enable
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SN54LS13B connection diagram of ic 74ls138 74LS138 function table sn54ls138 SN54S138 SN74LS138 SN74S13BA SN74S138A 54S138
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