LMX2512LQ0967 LMX2512LQ0967FPEBI LMX2512 LMX2502/12 LVCO-4279U LP3985IM5-2 - Datasheet Archive

 

EVALUATION BOARD OPERATING INSTRUCTIONS National Semiconductor Corporation Wireless Communications, RF Products Group 2900

 

LMX2512LQ0967 LMX2512LQ0967 EVALUATION BOARD OPERATING INSTRUCTIONS National Semiconductor Corporation Wireless Communications, RF Products Group 2900 Semiconductor Dr. Santa Clara, CA, 95052-8090 LMX2512LQ0967FPEBI LMX2512LQ0967FPEBI Rev 02.21.03 Table of Contents 1 2 General Description. 1 Setup . 1 2.1.1 Recommended Test Equipment . 1 2.1.2 Connection and Setup . 1 3 Measurement Considerations . 2 3.1 Phase Noise Measurement . 2 3.2 Loop Filter Bandwidth Measurement . 3 3.3 Reference Spur Measurement Using a Spectrum Analyzer. 3 3.4 Lock Time Measurement Using a Modulation Domain Analyzer. 3 4 Evaluation Board and CodeLoader Configuration . 4 4.1 CodeLoader Control Settings . 4 4.2 IF PLL Loop Filter Parameters. 6 5 Typical Performance Measurements . 6 5.1 Evaluation Conditions . 6 5.2 Typical Performance Criteria . 7 5.3 RF PLL Typical Performance Measurements. 7 5.4 IF PLL Typical Performance Measurements . 11 APPENDIX A: Evaluation Board ­ Schematic. 13 APPENDIX B: Evaluation Board ­ Build Diagram. 14 APPENDIX C: Evaluation Board ­ Bill of Materials. 15 APPENDIX D: Evaluation Board ­ Board Layout. 18 APPENDIX E: CodeLoader Software Setup . 20 LMX2512LQ0967 LMX2512LQ0967 EVALUATION BOARD OPERATING INSTRUCTIONS 1 General Description The LMX2512 LMX2512 Evaluation Board simplifies evaluation of the LMX2512 LMX2512 Dual PLL with integrated RF VCO. The board allows for the evaluation of many RF and IF PLL performance parameters with various control settings including: phase noise, lock time and spurious. The CodeLoader software gives the user a simple means of programming the IC's control registers. The board has sufficient flexibility to allow the user to place an additional on-board supply regulator and TCXO. The evaluation board circuitry consists of an LMX2512LQ0967 LMX2512LQ0967 device, an IF VCO and a discrete IF loop filter. SMA flange mount connectors provide for the RF VCO (RF_OUT), IF VCO (IF_OUT) and RF lock detect (LD) outputs, the reference frequency (OSC_IN) input and the power (VDD_5V) connection. A MICROWIRE cable assembly is bundled with the evaluation board for connecting to a PC through the parallel printer port. By means of serial port emulation, the CodeLoader software facilitates the LMX2512LQ0967 LMX2512LQ0967 internal register programming for evaluation and measurement. 2 Setup The fully assembled LMX2512 LMX2512 Evaluation Board is factory tested. Follow the instructions below to set up the hardware platform for the measurement of interest. 2.1.1 · · · · 2.1.2 Recommended Test Equipment Spectrum analyzer with operating frequency range > 2 GHz Modulation domain analyzer Low noise signal source adjusted to desired reference frequency DC power supply with adjustable voltage output Connection and Setup 1. Connect the RF_OUT or IF_OUT output port to the input of the spectrum analyzer for phase noise and reference spur measurement or to the input of the modulation domain analyzer for lock time measurement. Connect the unused port to a suitable 50-ohm termination. 2. Connect an RF signal generator or TCXO to the OSC_IN port of the evaluation board. Set the RF frequency to the desired reference frequency, 19.68 MHz for the default case. Set the RF level to 1 dBm (~0.7 Vpp). 3. Plug the DB25 connector end of the cable assembly to the parallel port of the PC. Connect the other end of the cable to the on-board 10 Pin Header (uWire) with the strip on the cable at the end opposite the end with the uWire label. Refer to Appendix E for more details. Alternatively, refer to the CodeLoader Operating Instructions from National Semiconductor's Wireless Communications website: wireless.national.com. LMX2512LQ0967 LMX2512LQ0967 February 21, 2003 1 LMX2512LQ0967 LMX2512LQ0967 EVALUATION BOARD OPERATING INSTRUCTIONS 4. Verify that jumper blocks JP1 and JP2 contain a full compliment of shunts. JP1 connects the 5.0 V supply input (VDD_5V) to the on board regulator. For convenience, an additional regulator circuit and TCXO are included on the layout but not placed. JP2 connects the 2.8 V regulated supply to various supply pins on the LMX2512 LMX2512 and the IF VCO. 5. Turn the DC power supply ON and adjust the voltage output to 5.0 V. Turn the DC power supply OFF. 6. Connect the DC power supply output to the VDD_5V port of the evaluation board. Turn the DC power supply ON. 7. Run the CodeLoader software for LMX2512 LMX2512 register programming. Ensure proper port setup and that the reference frequency matches the CodeLoader programming in the Bits/Pins and RF and IF PLL tabs. Refer to Appendix E for more details. 3 3.1 Measurement Considerations Phase Noise Measurement Measure the phase noise characteristics of the PLL with spectrum analyzer or a VCO/PLL analyzer. The phase noise plots in these instructions are from a VCO analyzer and give an overall picture of the phase noise of the LMX2512LQ0967 LMX2512LQ0967. The VCO analyzer provides plots of the phase noise over a span of offset frequencies giving the designer a more complete indication of a device's overall phase noise performance. For phase noise measurements at fixed offset frequencies, use an analyzer with a noise floor below the level of measurement interest. Since they are more readily available, below is an explanation of this test technique using a spectrum analyzer. Tune the spectrum analyzer to the desired center frequency with the span adjusted to include the appropriate offset frequency. Using the delta marker, the difference between the carrier and the noise level at the desired offset frequency is measured. The video averaging feature of the spectrum analyzer should used to better determine the noise level. The phase noise is a 1 Hz normalized bandwidth measurement expressed in dBc/Hz. Most modern spectrum analyzers have a feature that automatically normalizes the phase noise measurements to a 1 Hz bandwidth. This feature gives greater measurement accuracy. For spectrum analyzers without this feature, the normalized phase noise is equal to the noise level relative to the carrier minus 10 * log10 [Resolution Bandwidth]. For accurate close-in phase noise measurements, the offset frequency selected should be inside the loop bandwidth on the flat portion of the curve. With either measurement method, VCO analyzer or spectrum analyzer, care should be taken to ensure the noise floor of the instrument does not limit the phase noise measurement. LMX2512LQ0967 LMX2512LQ0967 February 21, 2003 2 LMX2512LQ0967 LMX2512LQ0967 EVALUATION BOARD OPERATING INSTRUCTIONS 3.2 Loop Filter Bandwidth Measurement The loop bandwidth is the bandwidth of the closed loop PLL system. It is by definition, the frequency that makes the forward loop gain equal to zero. The spectrum analyzer span is set to view the characteristic rising, peaking, and falling of the phase noise. Measurement of the loop bandwidth is rather complex. It is simpler to measure the 0 dB bandwidth. Although, not the same, the 0 dB bandwidth is a sufficient estimate of the loop filter bandwidth. The 0 dB bandwidth is defined as the frequency where the phase noise falls back to the level of the close-in value after rising to its peak value. The value measured is typically greater than the true loop filter bandwidth. For this evaluation, the 0 dB bandwidth is measured. 3.3 Reference Spur Measurement Using a Spectrum Analyzer The reference spurs can be seen on a spectrum analyzer and are measured in dBc. The spectrum analyzer is set to the desired center frequency with a span which allows the reference sidebands to be viewed. The spurious level is the difference between the level of the VCO output frequency tone and the level of the spur at an offset equal to the carrier frequency +/- the comparison frequency. For a more accurate account of a device's spurious performance, the reference spurs across the VCO's frequency band should be determined. The worst-case spur is typically defined as the PLL's spur performance. 3.4 Lock Time Measurement Using a Modulation Domain Analyzer The modulation domain analyzer measures the switching speed, or lock time, using a frequency versus time plot. Set the center frequency of the modulation domain analyzer to the final (settling) frequency. Use a wide span allows viewing of the entire positive or negative switching waveform. Use a narrower span to evaluate the settling waveform within +/- 1 kHz. A trigger condition, typically a latch enable pulse, specifies the event that will cause the modulation domain analyzer to capture and display the measurement results. The lock time is the time difference between the point the frequency starts to change (T1), and the point the VCO frequency settles to within +/- 1 kHz of the final value (T2), (i.e. lock time = T2 ­ T1). Use the BurstMode tab of the CodeLoader software to program the device to toggle between a desired minimum and maximum frequency. It is necessary to include a sufficient delay, such as 100000, after each programming command. For more detail, refer to the BurstMode Tab section in the CodeLoader Operating Instructions from National Semiconductor's Wireless Communications website: wireless.national.com. LMX2512LQ0967 LMX2512LQ0967 February 21, 2003 3 LMX2512LQ0967 LMX2512LQ0967 EVALUATION BOARD OPERATING INSTRUCTIONS 4 4.1 Evaluation Board and CodeLoader Configuration CodeLoader Control Settings Table 4.1.1 summarizes the settings of the programming registers used in creating the plots in the following section. To aid in setting up the correct configuration, the Mode pull down menu contains a default state for CodeLoader. The default mode will set the bits to a known working state. Use this mode to reset the configuration of the registers. The LMX2502/12 LMX2502/12 datasheet provides additional details about the controls. Note on SPI_DEF control: With SPI_DEF set to 1, the initial startup of the LMX2512LQ0967 LMX2512LQ0967 requires only the Default words (R0 ­ R3). After startup, only word R0 is required to change the RF frequency. Setting SPI_DEF to 0 allows words R4 through R6 to be loaded into the registers. The LMX2512LQ0967 LMX2512LQ0967 operates using one of three default IF frequencies depending on the application and frequency plan. With the SPI_DEF bit set to 1, the IF N and R counter values from the IF PLL tab are ignored, and the appropriate default values are used based on the selected reference (OSC_FREQ) and IF frequency (IF_FREQ) from the Bits/Pins tab. If a nondefault IF frequency is desired, the SPI_DEF bit must be set to 0 and the desired IF frequency can be entered using the IF PLL tab. Note on Reference Frequency Controls: The Bits/Pins, RF PLL and IF PLL tabs contain reference oscillator controls. For SPI_DEF = 1, the IF PLL uses the OSC_FREQ and IF_FREQ controls on the Bits/Pins tab to determine the counter values. For SPI_DEF = 0, the IF PLL uses reference frequency control on the IF PLL tab to determine the N counter values (IF_A, IF_B) based on the IF VCO frequency entered. The RF PLL uses reference frequency control on the RF PLL tab to determine the N counter values (RF_A, RF_B, RF_FN) based on the RF VCO frequency entered. These reference frequency controls are independent, and to obtain predictable device behavior, set them to the same reference frequency. LMX2512LQ0967 LMX2512LQ0967 February 21, 2003 4 LMX2512LQ0967 LMX2512LQ0967 EVALUATION BOARD OPERATING INSTRUCTIONS Table 4.1.1 CodeLoader Default Control Settings Control Register Name Bits/Pins Tab RF PLL Controls RF_EN OB_CRL SPUR_RDT VCO_CUR IF PLL Controls IF_EN SPI_DEF IF_FREQ IF_CUR Misc Controls OSC_FREQ RF_LD Bandwidth Controls BW_EN BW_DUR BW_CONT Program Pins CE TRIGGER RF PLL Tab Reference Oscillator Fractional Compensation Fractional Denominator VCO LMX2512LQ0967 LMX2512LQ0967 Setting High (Checked) 11 (Maximum) 10 Cont-Recommended 11 (Max-Recommended) High (Checked) High (Checked) 440.76 MHz 300 uA 19.68 MHz Hard Zero High (Checked) 00 (Min-Recommended) 00 (Max-Recommended) High (Checked) Low (Not Checked) 19.68 MHz 253 1968 966.85 MHz February 21, 2003 5 LMX2512LQ0967 LMX2512LQ0967 EVALUATION BOARD OPERATING INSTRUCTIONS 4.2 IF PLL Loop Filter Parameters Settings For Operation Charge Pump Gain (K) 0 K 36 k 330 pF Open Open 3300 pF Comparison Frequency (Fcomp) 120 kHz Output Frequency (Fout) (435 ­ 465) MHz VCO Supply VCO 0 300 µA 2.8 V Other Information VCO Used Varil LVCO-4279U LVCO-4279U VCO Gain 20 MHz/V Figure 4.2.1 IF loop filter parameters 5 Typical Performance Measurements The LMX2512 LMX2512 Evaluation Board typical performance criteria is shown below: 5.1 Evaluation Conditions Table 5.1.1 Test Conditions Operating Voltage 2.8 V from regulator output Reference Frequency 19.68 MHz RF VCO Tuning Range (954 ­ 980) MHz RF Comparison Frequency 19.68 MHz IF VCO Tuning Range (435 ­ 465) MHz IF Comparison Frequency 120 kHz LMX2512LQ0967 LMX2512LQ0967 February 21, 2003 6 LMX2512LQ0967 LMX2512LQ0967 EVALUATION BOARD OPERATING INSTRUCTIONS 5.2 Typical Performance Criteria Table 5.2.1 Typical Performance Criteria RF PLL Phase Noise < -112 dBc/Hz at 100 kHz Offset RF PLL Reference Spur < -75 dBc at 19.68 MHz Offset RF PLL Lock Time < 800 µs (Within +/- 1 kHz Settling Frequency) IF PLL Phase Noise < -80 dBc/Hz at 1 kHz Offset IF PLL Reference Spur < -80 dBc at 120 kHz Offset Remark: Computer monitors and other lab equipment can cause noise spikes. If noise spikes are present on the signal, try turning off the monitor or other equipment to verify that they are not the cause. In addition, noise may be getting onto the signal through the cable that connects to the parallel port of the computer. 5.3 RF PLL Typical Performance Measurements Figure 5.3.1 RF VCO phase noise and loop bandwidth (low channel ­ 955.02 MHz) LMX2512LQ0967 LMX2512LQ0967 February 21, 2003 7 LMX2512LQ0967 LMX2512LQ0967 EVALUATION BOARD OPERATING INSTRUCTIONS Figure 5.3.2 RF VCO phase noise and loop bandwidth (mid channel ­ 966.85 MHz) Figure 5.3.3 RF VCO phase noise and loop bandwidth (high channel ­ 978.75 MHz) LMX2512LQ0967 LMX2512LQ0967 February 21, 2003 8 LMX2512LQ0967 LMX2512LQ0967 EVALUATION BOARD OPERATING INSTRUCTIONS Figure 5.3.4 RF PLL negative frequency switching waveform Lock time = 567 µs Figure 5.3.5 Lock time from 978.75 MHz to 955.02 MHz LMX2512LQ0967 LMX2512LQ0967 February 21, 2003 9 LMX2512LQ0967 LMX2512LQ0967 EVALUATION BOARD OPERATING INSTRUCTIONS Figure 5.3.6 RF PLL positive frequency switching waveform Lock time = 578 µs Figure 5.3.7 Lock time from 955.02 MHz to 978.75 MHz LMX2512LQ0967 LMX2512LQ0967 February 21, 2003 10 LMX2512LQ0967 LMX2512LQ0967 EVALUATION BOARD OPERATING INSTRUCTIONS 5.4 IF PLL Typical Performance Measurements Figure 5.4.1 IF VCO phase noise and loop bandwidth Figure 5.4.2 IF PLL reference spurs at 120kHz offset (spur level