LMH0341/0041/0071/0051 LMH0341 259MSMPTE 259M-CSMPTE 292MSMPTE LMH0341LMH0041 - Datasheet Archive

 

LMH0341/0041/0071/0051 SDI FPGA SER/DES 5 LVDS FPGA FPGA LMH0341 DVB-ASISMPTE 259MSMPTE 292M SMPTE 424M 5

 

LMH0341/0041/0071/0051 LMH0341/0041/0071/0051 SDI FPGA SER/DES 5 LVDS FPGA FPGA LMH0341 LMH0341 DVB-ASISMPTE 259MSMPTE 259MSMPTE 292M SMPTE 424M 5 Raw Table 1 SMPTE 259M-CSMPTE 259M-CSMPTE 292MSMPTE 292MSMPTE 424M DVB-ASI (Table 1 ) (typ): 590mW ( 3G ) 0.6UI LMH0341 LMH0341 FPGA 5 LVDS LVDS SMBus VCO LMH0341 LMH0341 CDR FPGA LMH0341LMH0041 LMH0341LMH0041 LMH0071 LMH0071 SMPTE Table 1 5 LVDS VCO 3.3V SMBus 48 LLP SER/DES FPGA IP SER/DES 48 LLP - 40 85 SDI DVR 20081020 TRI-STATE® © National Semiconductor Corporation DS300172-12-JP DS300172-12-JP LMH0341LMH0041LMH0071LMH0051 LMH0341LMH0041LMH0071LMH0051 ds300170 24060 20070403 Mark Sauerwald LVDS 3GbpsHDSDDVB-ASI SDI 1 LMH0341/LMH0041/LMH0071/LMH0051 LMH0341/LMH0041/LMH0071/LMH0051 LMH0341/LMH0041/LMH0071/LMH0051 LMH0341/LMH0041/LMH0071/LMH0051 LVDS 3GbpsHDSDDVB-ASI SDI 2008 10 LMH0341/LMH0041/LMH0071/LMH0051 LMH0341/LMH0041/LMH0071/LMH0051 I/O LVDS RX[4:0] RX[4:0] - LVDS LVDS 5 DDR RXCLK RXCLK - LVDS LVDS DDR RXIN0 RXIN0 - 0 RXIN1 RXIN1 - 1 TXOUT CML TXOUT - CML SMBus SDA LVCMOS SMBus SCK LVCMOS SMBus SMB_CS LVCMOS SMBus High RESET LVCMOS H L LOCK LVCMOS PLL H L PLL DVB_ASI LVCMOS DVB_ASI H DVB_ASI L Loopthru_EN LVCMOS H L RX_MUX_SEL LVCMOS H RXIN1 L RXIN0 GPIO[2:0] LVCMOS RSVD_H LVCMOS www.national.com/jpn/ ­ High 5k VDD3V3 2 I/O RSET 800mV 7.87k (SMPTE) LF_CP LF_REF DNC VDD3V3 3.3V VDDPLL 3.3V PLL VDD2V5 2.5V GND ­ DAP ( ) GND GND TABLE 1. Feature Table 3 www.national.com/jpn/ LMH0341/LMH0041/LMH0071/LMH0051 LMH0341/LMH0041/LMH0071/LMH0051 ( ) LMH0341/LMH0041/LMH0071/LMH0051 LMH0341/LMH0041/LMH0071/LMH0051 (Note 1) LVDS (VDD3V3) - 0.3V 4.0V - 4 260 (VDD2V5) - 0.3V 3.0V LVCMOS - 0.3V (VDD3V3 0.3V) - - - JA 26 /W LVCMOS - 0.3V (VDD3V3 0.3V) SMBus - 0.3V 3.6V ESD - 1.5k100pF www.national.com/jpn/ 4 0.3V 3.6V 150 - 65 150 ± 8KV LMH0341/LMH0041/LMH0071/LMH0051 LMH0341/LMH0041/LMH0071/LMH0051 (Note 2) DVB_ASIRESET LOCKGPIO RX_MUX_SELLoopthru_EN (Note 2) 5 www.national.com/jpn/ LMH0341/LMH0041/LMH0071/LMH0051 LMH0341/LMH0041/LMH0071/LMH0051 SDI (Note 2) www.national.com/jpn/ 6 LMH0341/LMH0041/LMH0071/LMH0051 LMH0341/LMH0041/LMH0071/LMH0051 LVDS (Note 2) LVDS (Note 2) FIGURE 1. LVDS Switching Times 7 www.national.com/jpn/ LMH0341/LMH0041/LMH0071/LMH0051 LMH0341/LMH0041/LMH0071/LMH0051 SMBus (Note 2) SMBus (Note 2) FIGURE 2. SMBus Timing Parameters www.national.com/jpn/ 8 LMH0341/LMH0041/LMH0071/LMH0051 LMH0341/LMH0041/LMH0071/LMH0051 SDI (LMH0341 LMH0341 / LMH0041 LMH0041 / LMH0071 LMH0071) (Note 2) Note 1: Note 2: VDD 3.3VTA 25 Note 3: - Note 4: 1 400pF Note 5: Note 6: SMPTE RP184 RP184 Note 7: Note 8: 2.97Gbps1.485Gbps 270Mbps 270Mbps Note 9: LMH0341 LMH0341 FIGURE 3. Receiver (LVDS Interface) Propagation Delay 9 www.national.com/jpn/ LMH0341/LMH0041/LMH0071/LMH0051 LMH0341/LMH0041/LMH0071/LMH0051 LVDS DES ANSI/TIA/EIA-644 ANSI/TIA/EIA-644 LVDS LVDS FPGA 100 FPGA 25cm DES DES SER FPGA 5 10 ( 20 ) DES DVB ASISMPTE 259M-CSMPTE 259M-CSMPTE 292M SMPTE 424M IP IP IP DES LVDS 0x27h LVDS DES LVDS FPGA LVDS 0x28h RXCLK DDR DDR/2 DES 2.5V 3.3V 4.7 F 0.1 F 0.1 F GND 3.3V VDDPLL 22 F DES PLL PLL 26 27 30MHz 50MHz RF GND GND DVB-ASI DVB-ASI DVB-ASI High DVB-ASI 8b/10b 8b/10b (4bit) RX0-RX3 RX4 FIFO RX0-RX3 RX4 High RXCLK RXCLK DES SDI 2 RX_MUX_SEL 1 SDI HD-SDI SD-SDI LMH0044 LMH0044 LMH0044 LMH0044 LMH0041 LMH0041 RXIN LMH0344 LMH0344 LMH0044 LMH0044 3Gbps LMH0341 LMH0341 3.3V 2.5V PLL RXIN0 3 1 1 Reset Low High 3 Soft Reset SMBus www.national.com/jpn/ 10 FIGURE 5. Simplified SDI Output Circuit FIGURE 4. Simplified SDI Input Circuit SMPTE 424M (3Gbps ) SDI 0.2UI 0.3UI DES Figure 6 2.97Gbps LMH0341 LMH0341 DES SMPTE 10MHz RXCLK 2 0 LMH0341 LMH0341 3dB LMH0341 LMH0341 Figure 8 2.97Gbps 0.5UI LMH0341 LMH0341 SDI DES 2:1 1 2 DES PLL ( )PLL LOCK High 5ms ( 270Mbps 1.485Gbps ) IP SDI 75 VDD2V5 75 2 SMPTE 259MSMPTE 259MSMPTE 292M SMPTE 424M / SMPTE SDI (ORL) 11 www.national.com/jpn/ LMH0341/LMH0041/LMH0071/LMH0051 LMH0341/LMH0041/LMH0071/LMH0051 ( ) LMH0341/LMH0041/LMH0071/LMH0051 LMH0341/LMH0041/LMH0071/LMH0051 (SMBus) 2 SMBus SMBus 3 SMBus SMBus CS SDA SCK CS SCLSDA High DES SMBus DES ( ) SMBus SCK High SDA START/STOP/IDLE - SMBus 3 FIGURE 6. Jitter Tolerance Curve START SCK High SDA High Low START STOP SCK High SDA Low High STOP IDLE STOP tBUF SCK SDA High HightHIGH IDLE SMBus DES SMBus START MSB 1 (8 ) 9 ACK ACK ACK "0" NACK "1" SCL Low (ACK) SDA FIGURE 7. Jitter Transfer Curve Parameters SMBus DES 3 7 DES (LSB) "0" 2 3 STOP SMBus LSB "0" START LSB "1" DES SDA ACK "1" NACK "0" DES FIGURE 8. Jitter Transfer Curve SMBus (SMBus) 2.0 SMBus 2.0 ARP (Address Resolution Protocol) 3.3V 5V (1 ) SMB_CS www.national.com/jpn/ 12 LMH0341/LMH0041/LMH0071/LMH0051 LMH0341/LMH0041/LMH0071/LMH0051 ( ) FIGURE 9. SMBus Configuration 1 - Host to single device FIGURE 10. SMBus Configuration 2 - Host to multiple devices with SMB_CS signals FIGURE 11. SMBus Configuration 3 - Host to multiple devices with multiple SMBus Interfaces 13 www.national.com/jpn/ LMH0341/LMH0041/LMH0071/LMH0051 LMH0341/LMH0041/LMH0071/LMH0051 ( ) (GPIO) DES 3 PCLK GPIO TRI-STATE® ( ) GPIO 4 GPIO 3 GPIO LMH0040 LMH0040 FIGURE 12. Simplified LVCMOS Input Circuit GPIO0 SMBus SMBus 0 GPIO1 SMBus SMBus 1 PLL GPIO2 SMBus FIGURE 13. Simplified LVCMOS Output Circuit SMBus GPIO LVDS TX 1/20 DES GPIO CDR 1/20 2 3 / 0 GPIO0 0 GPIO0 Low RX_MUX_SEL 0 1 00: 01: 10: 11: GPIO CD SMBus DES LOCK DES FPGA 1 GPIO "0" LSB GPIO "0" GPIO0 0 02h 00010010b www.national.com/jpn/ 14 PCB DES LMH0044 LMH0044 DES FPGA DES DES DES DES 2 DES DESBNC SDI BNC FIGURE 14. Evaluation Board Loopthrough Output Return Loss SMPTE DES SMPTE DES 75 75 DES Figure 15 3Gbps LMH0341 LMH0341 SMPTE LMH0041 LMH0041 LMH0071 LMH0071 DES FPGA RX 5 LVDS LVDS 1 1 FPGA 100 FPGA LVDS (RXCLK) FPGADES PCB 25cm (10 ) 6 SMBus FPGA DES SMBus SCK SDA SMB_CS FPGA GPO FPGA / PCB 1 GPIO DVB_ASI RESET LOCK DES NC ( ) LMH0341 LMH0341 GPIO_1 RXIN_1 LMH0340 LMH0340 RXIN_1 RXIN_0 PCB 1 2 GND 15 www.national.com/jpn/ LMH0341/LMH0041/LMH0071/LMH0051 LMH0341/LMH0041/LMH0071/LMH0051 LMH0341/LMH0041/LMH0071/LMH0051 LMH0341/LMH0041/LMH0071/LMH0051 PLL SER LF_CP LF_REF 30nF ( ) DES SMPTE 75 75 2.5V SMPTE 6.8nH 75 4.7 F AC AC SMPTE NRZI 1:2 RSET 800mV 7.87k RSVD_H 5k 3.3V High DVB_ASI 3 ( ) 2 3.3V 2.5V PLL 3.3V SER DAP FIGURE 15. Typical SMPTE Application Circuit www.national.com/jpn/ 16 LMH0341/LMH0041/LMH0071/LMH0051 LMH0341/LMH0041/LMH0071/LMH0051 ( ) FIGURE 16. Typical CML Application Circuit (LMH0051 LMH0051) 17 www.national.com/jpn/ LMH0341/LMH0041/LMH0071/LMH0051 LMH0341/LMH0041/LMH0071/LMH0051 DES ADD 'h 00 device_identification MSB 7 SMBus 0x58h LSB "0" 1 058h 'B0h 7:1 01 reset device_id 0 058h SMBus ID 0 0 GPIO_0 Configuration r/w 0x01h LSB "1" 0x00h 0x00h 7:1 02 R/W sw_rst r/w 0'b GPIO_0 TRI-STATE (bit[0] "0") (bit[1] "0") 7:4 0000'b GPIO_0_ren[1:0] r/w 01'b 00: 01: 10: 11: 1 GPIO_0_sleepz r/w 0'b 0: 1: 0 GPIO_1 Configuration r/w 3:2 03 GPIO_0_mode[3:0] 0000: GPout 0001: 0 : GPout0 enable r/w 1'b 0: TRI-STATE 1: GPIO_1 TRI-STATE (bit[0] "0") (bit[1] "0") 7:4 r/w 0000'b 3:2 GPIO_0_ren[1:0] r/w 01'b 00: 01: 10: 11: 1 GPIO_0_sleepz r/w 0'b 0: 1: 0 www.national.com/jpn/ GPIO_0_mode[3:0] GPout0 enable r/w 1'b 0: TRI-STATE 1: 18 0000: POR 0001: GP_OUT[1] 0010: 1 0011: cdr_lock : ADD 'h 04 GPIO_2 TRI-STATE (bit[0] "0") (bit[1] "0") GPIO_2 Configuration R/W 7:4 0000'b GPIO_0_ren[1:0] r/w 01'b 00: 01: 10: 11: 1 GPIO_0_sleepz r/w 0'b 0: 1: 0 GP Input r/w 3:2 05 GPIO_0_mode[3:0] 0000: GPout [2] 0001: 0010: LVDS TX CLK 0011: CDR_CLK : GPout0 enable r/w 1'b 0: TRI-STATE 1: GPIO 7:3 2 GP Output GPIO 2 r GPIO 1 0 06 r 1 r GPIO 0 GPIO GPIO 7:3 2 r/w GPIO 2 1 r/w GPIO 1 0 r/w GPIO 0 07­0C 0D DVB_ASI Idle_A DVB_ASI K28.5 7:0 0E r/w 83 [7:0] r/w 2 [9:8] DVB_ASI Idle_B DVB_ASI MSBs 7:2 1:0 0F­1C 1D Variant DES 8 7:6 r 5 Loop through enable r Loopthru_EN 4:3 mode r 2 00,01,10: 11: DVB_ASI 2 1:0 1E-1F Variant r 00: LMH0341 LMH0341 01: LMH0041/LMH0051 LMH0041/LMH0051 10: LMH0071 LMH0071 11: 19 www.national.com/jpn/ LMH0341/LMH0041/LMH0071/LMH0051 LMH0341/LMH0041/LMH0071/LMH0051 DES ( ) LMH0341/LMH0041/LMH0071/LMH0051 LMH0341/LMH0041/LMH0071/LMH0051 DES ( ) ADD 'h 20 Control R/W Data Order r/w 0 0: LSB 1: MSB Reset Channel r/w 0 "1" 0 DVB_ASI 1 21 7:3 2 Digital Powerdown r/w 0 "1" DVB_ASI 7:5 4 RX_MUX_SEL 3:2 1:0 DVB_ASI r/w 0 r/w 0 22 RX_MUX_SEL 00,01,10: 11:DVB_ASI 22 Override SMBus DVB_ASI 7:5 4 DVB_ASI Override r/w 0 "1" 21 "0" RX_MUX_SEL "1" 21 DVB_ASI "0" DVB_ASI "1" 21 LVDS Control 1 0 27 RX_MUX Control Override 3:1 23­26 LVDS LVDS 7 r/w 0 "0" LVDS VOD "1" VOD 6 LVDS Control r/w 0 "1" SMBus LVDS 5 RXCLK Enable r/w 0 RXCLK 4 RX4 Enable r/w 0 RX4 3 RX3 Enable r/w 0 RX3 2 RX2 Enable r/w 0 RX2 1 RX1 Enable r/w 0 RX1 0 www.national.com/jpn/ LVDS_VOD RX0 Enable r/w 0 RX0 20 ADD 'h 28 LVDS Control 2 LVDS R/W 7 6 0 LVDS RXCLK Rate r/w 1 1: RXCLK DDR 0: RXCLI DDR/2 RXCLK Invert r/w 0 RXCLK 3:2 LVDS Clock delay r/w 10'b 1:0 LSB 100ps RXCLK Event Configuration r/w 4 2B LVDS Reset 5 29­2A PLL r/w 0 0: CDR RXCLK 1: Reset CDR Error Count r/w 0 CDR 1 Reset Link Error Count r/w 0 0 enable count r/w 0 Error Monitor Event Count Select 2 2D 3 2C 7:4 7:5 r/w 0 8b10b error disable r/w 0 8b/10b LOCK 2 clear event count r/w 0 1 select error count r/w 0 0: 1: 0 Error Threshold Accumulate Error Count 3 2E 4 Normal Error Disable r/w 0 NORMAL 0x10h RXOUT LSBs 7:0 2F Error Threshold Error Threshold r/w MSBs Error Threshold r/w 21 00 RXOUT www.national.com/jpn/ LMH0341/LMH0041/LMH0071/LMH0051 LMH0341/LMH0041/LMH0071/LMH0051 DES ( ) LMH0341/LMH0041/LMH0071/LMH0051 LMH0341/LMH0041/LMH0071/LMH0051 DES ( ) ADD 'h 30­3A 3B Data Rate R/W PLL 7 6:4 Freq Range r 111 001: 270Mbps 011: 1.485Gbps 110: 2.97Gbps 111: 3:0 3C CDR Lock Status 7:4 3 1: CDR 0: CDR Signal Detect Ch 1 r 1: 1 Signal Detect Ch 0 r 1: 0 Event Status r 2 3D CDR Lock 7:0 3E Error Status 1 Error Status 2 0 Data Error Count 1 r/w 0 -LSB 0 -MSB MSB 7:0 www.national.com/jpn/ r/w LSB 7:0 3F event count Data Error Count 2 r/w 22 LMH0341/LMH0041/LMH0071/LMH0051 LMH0341/LMH0041/LMH0071/LMH0051 FIGURE 17. Connection Diagram for LMH0341 LMH0341 / LMH0041 LMH0041 / LMH0071 LMH0071 23 www.national.com/jpn/ LMH0341/LMH0041/LMH0071/LMH0051 LMH0341/LMH0041/LMH0071/LMH0051 ( ) FIGURE 18. Connection Diagram for LMH0051 LMH0051 www.national.com/jpn/ 24 LMH0341/LMH0041/LMH0071/LMH0051 LMH0341/LMH0041/LMH0071/LMH0051 www.national.com/jpn/ 25 LMH0341/LMH0041/LMH0071/LMH0051 LMH0341/LMH0041/LMH0071/LMH0051 millimeters 48-Lead QFN Plastic Quad Package NS Package Number SQA48A SQA48A www.national.com/jpn/ 26 (CEO) (GENERAL COUNSEL) a (b) National Semiconductor Copyright © 2009 National Semiconductor Corporation www.national.com 135-0042 2-17-16 / TEL.(03)5639-7300 www.national.com/jpn/ LMH0341/LMH0041/LMH0071/LMH0051 LMH0341/LMH0041/LMH0071/LMH0051 LVDS 3GbpsHDSDDVB-ASI SDI