LMC6061 LMC6081 LMC6062 LMC6064 DS011422-1 DS011422-15 DS011422 LMC6061AM - Datasheet Archive
Precision CMOS Single Micropower Operational Amplifier General Description The LMC6061 is a precision single low offset voltage,
LMC6061 LMC6061 Precision CMOS Single Micropower Operational Amplifier General Description The LMC6061 LMC6061 is a precision single low offset voltage, micropower operational amplifier, capable of precision single supply operation. Performance characteristics include ultra low input bias current, high voltage gain, rail-to-rail output swing, and an input common mode voltage range that includes ground. These features, plus its low power consumption, make the LMC6061 LMC6061 ideally suited for battery powered applications. Other applications using the LMC6061 LMC6061 include precision full-wave rectifiers, integrators, references, sample-and-hold circuits, and true instrumentation amplifiers. This device is built with National's advanced double-Poly Silicon-Gate CMOS process. For designs that require higher speed, see the LMC6081 LMC6081 precision single operational amplifier. For a dual or quad operational amplifier with similar features, see the LMC6062 LMC6062 or LMC6064 LMC6064 respectively. PATENT PENDING n n n n n n n n Low offset voltage: 100 µV Ultra low supply current: 20 µA Operates from 4.5V to 15V single supply Ultra low input bias current: 10 fA Output swing within 10 mV of supply rail, 100k load Input common-mode range includes V- High voltage gain: 140 dB Improved latchup immunity Applications n n n n n n n Instrumentation amplifier Photodiode and infrared detector preamplifier Transducer amplifiers Hand-held analytic instruments Medical instrumentation D/A converter Charge amplifier for piezoelectric transducers Features (Typical Unless Otherwise Noted) Connection Diagram Distribution of LMC6061 LMC6061 Input Offset Voltage (TA = +25°C) 8-Pin DIP/SO DS011422-1 DS011422-1 Top View DS011422-15 DS011422-15 © 2000 National Semiconductor Corporation DS011422 DS011422 www.national.com LMC6061 LMC6061 Precision CMOS Single Micropower Operational Amplifier August 2000 LMC6061 LMC6061 Absolute Maximum Ratings (Note 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. ± Supply Voltage Differential Input Voltage Voltage at Input/Output Pin 40 mA (Note 3) Operating Ratings (Note 1) (V+) +0.3V, (V-) -0.3V 16V (Note 10) (Note 2) 260°C Supply Voltage (V+ - V-) Output Short Circuit to V+ Output Short Circuit to V- Lead Temperature (Soldering, 10 sec.) Storage Temp. Range Junction Temperature ESD Tolerance (Note 4) ± 10 mA ± 30 mA Current at Input Pin Current at Output Pin Current at Power Supply Pin Power Dissipation Temperature Range LMC6061AM LMC6061AM LMC6061AI LMC6061AI, LMC6082I LMC6082I Supply Voltage Thermal Resistance (JA) (Note 11) N Package, 8-Pin Molded DIP M Package, 8-Pin Surface Mount Power Dissipation -65°C to +150°C 150°C 2 kV -55°C TJ +125°C -40°C TJ +85°C 4.5V V+ 15.5V 115°C/W 193°C/W (Note 9) DC Electrical Characteristics Unless otherwise specified, all limits guaranteed for TJ = 25°C. Boldface limits apply at the temperature extremes. V+ = 5V, V- = 0V, VCM = 1.5V, VO = 2.5V and RL > 1M unless otherwise specified. Typ Parameter Conditions LMC6061AI LMC6061AI Limit Limit Limit (Note 6) (Note 6) TCVOS 100 LMC6061I LMC6061I Units Input Offset Voltage 350 350 800 µV 1200 VOS Input Offset Voltage LMC6061AM LMC6061AM (Note 9) (Note 6) Symbol 900 1300 Max 1.0 µV/°C Average Drift IB Input Bias Current 0.010 pA 100 IOS Input Offset Current RIN Input Resistance CMRR Common Mode 4 4 0.005 pA 100 2 2 Max Tera > 10 0V VCM 12.0V Max 85 75 70 85 75 70 + 75 66 dB 72 63 Min 75 66 dB 72 63 Min 84 74 dB Min Rejection Ratio V = 15V Positive Power Supply 5V V+ 15V Rejection Ratio VO = 2.5V -PSRR Negative Power Supply 0V V- -10V 100 84 70 81 71 VCM Input Common-Mode V+ = 5V and 15V -0.4 -0.1 -0.1 -0.1 V Voltage Range for CMRR 60 dB 0 0 0 Max V+ - 2.3 V+ - 2.3 V+ - 2.3 V +PSRR Rejection Ratio V+ - 1.9 + V - 2.6 AV Large Signal RL = 100 k Voltage Gain Sourcing 4000 Sinking V+ - 2.5 Min 400 400 300 V/mV 300 200 Min V/mV 180 180 90 70 RL = 25 k 3000 V - 2.5 200 (Note 7) + 100 60 Min 400 200 V/mV Sourcing 3000 400 150 150 80 Min Sinking 2000 100 100 70 V/mV 35 50 35 Min (Note 7) www.national.com 2 (Continued) Unless otherwise specified, all limits guaranteed for TJ = 25°C. Boldface limits apply at the temperature extremes. V+ = 5V, V- = 0V, VCM = 1.5V, VO = 2.5V and RL > 1M unless otherwise specified. Typ Parameter V+ = 5V LMC6061AI LMC6061AI Limit Limit Limit (Note 6) (Note 6) 4.995 LMC6061I LMC6061I Units 4.990 4.990 4.950 V 4.970 4.980 4.925 Min 0.010 0.010 0.050 V 0.030 0.020 0.075 Max 4.975 4.975 4.950 V 4.955 4.965 4.850 Min 0.010 0.020 0.020 0.050 V 0.045 0.035 0.150 Max 14.990 14.975 14.975 14.950 V 14.955 14.965 14.925 Min 0.025 0.025 0.050 V 0.050 0.035 0.075 Max 14.900 14.900 14.850 V 14.800 14.850 14.800 Min 0.050 0.050 0.100 V 0.200 VO Output Swing Conditions LMC6061AM LMC6061AM (Note 9) (Note 6) Symbol 0.150 0.200 Max 13 mA Min RL = 100 k to 2.5V 0.005 V+ = 5V 4.990 RL = 25 k to 2.5V V+ = 15V RL = 100 k to 7.5V 0.010 V+ = 15V 14.965 RL = 25 k to 7.5V 0.025 IO Output Current Sourcing, VO = 0V 22 16 16 8 10 8 Sinking, VO = 5V 21 16 16 16 mA 7 8 8 Min + V = 5V IO Output Current Sourcing, VO = 0V 25 15 15 15 mA 9 10 10 Min Sinking, VO = 13V 35 24 24 24 mA 7 8 8 Min 24 24 32 µA 35 32 40 Max 30 30 40 µA 40 38 48 Max + V = 15V (Note 10) IS Supply Current V+ = +5V, VO = 1.5V 20 V+ = +15V, VO = 7.5V 24 AC Electrical Characteristics Unless otherwise specified, all limits guaranteed for TJ = 25°C, Boldface limits apply at the temperature extremes. V+ = 5V, V- = 0V, VCM = 1.5V, VO = 2.5V and RL > 1M unless otherwise specified. Typ Slew Rate Conditions (Note 8) LMC6061AM LMC6061AM LMC6061AI LMC6061AI Limit Limit Limit (Note 6) (Note 6) 20 20 15 8 SR Parameter (Note 5) (Note 6) Symbol 10 7 35 GBW Gain-Bandwidth Product m Phase Margin en Input-Referred Voltage Noise F = 1 kHz Input-Referred Current Noise F = 1 kHz Total Harmonic Distortion V/ms Min 0.0002 T.H.D. Units 83 in LMC6061I LMC6061I 100 kHz 50 Deg F = 1 kHz, AV = -5 RL = 100 k, VO = 2 VPP 0.01 % ± 5V Supply 3 www.national.com LMC6061 LMC6061 DC Electrical Characteristics LMC6061 LMC6061 AC Electrical Characteristics (Continued) Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is intended to be functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Note 2: Applies to both single-supply and split-supply operation. Continous short circuit operation at elevated ambient temperature can result in exceeding the maximum allowed junction temperature of 150°C. Output currents in excess of ± 30 mA over long term may adversely affect reliability. Note 3: The maximum power dissipation is a function of TJ(Max), JA, and TA. The maximum allowable power dissipation at any ambient temperature is PD = (TJ(Max) - TA)/JA. Note 4: Human body model, 1.5 k in series with 100 pF. Note 5: Typical values represent the most likely parametric norm. Note 6: All limits are guaranteed by testing or statistical analysis. Note 7: V+ = 15V, VCM = 7.5V and RL connected to 7.5V. For Sourcing tests, 7.5V VO 11.5V. For Sinking tests, 2.5V VO 7.5V. Note 8: V+ = 15V. Connected as Voltage Follower with 10V step input. Number specified is the slower of the positive and negative slew rates. Note 9: For operating at elevated temperatures the device must be derated based on the thermal resistance JA with PD = (TJTA)/JA. Note 10: Do not connect output to V+, when V+ is greater than 13V or reliability witll be adversely affected. Note 11: All numbers apply for packages soldered directly into a PC board. Note 12: For guaranteed Military Temperature Range parameters see RETSMC6061X RETSMC6061X. Typical Performance Characteristics Distribution of LMC6061 LMC6061 Input Offset Voltage (TA = +25°C) VS = ± 7.5V, TA = 25°C, Unless otherwise specified Distribution of LMC6061 LMC6061 Input Offset Voltage (TA = -55°C) DS011422-15 DS011422-15 Input Bias Current vs Temperature DS011422-16 DS011422-16 Supply Current vs Supply Voltage DS011422-18 DS011422-18 www.national.com Distribution of LMC6061 LMC6061 Input Offset Voltage (TA = +125°C) Input Voltage vs Output Voltage DS011422-19 DS011422-19 4 DS011422-17 DS011422-17 DS011422-20 DS011422-20 LMC6061 LMC6061 Typical Performance Characteristics VS = ± 7.5V, TA = 25°C, Unless otherwise specified (Continued) Common Mode Rejection Ratio vs Frequency Power Supply Rejection Ratio vs Frequency Input Voltage Noise vs Frequency DS011422-22 DS011422-22 DS011422-23 DS011422-23 DS011422-21 DS011422-21 Output Characteristics Sourcing Current Output Characteristics Sinking Current Gain and Phase Response vs Temperature (-55°C to +125°C) DS011422-24 DS011422-24 DS011422-25 DS011422-25 Typical Performance Characteristics Gain and Phase Response vs Capacitive Load with RL = 20 k DS011422-26 DS011422-26 VS = ± 7.5V, TA = 25°C, Unless otherwise specified Gain and Phase Response vs Capacitive Load with RL = 500 k Open Loop Frequency Response DS011422-29 DS011422-29 DS011422-27 DS011422-27 DS011422-28 DS011422-28 5 www.national.com LMC6061 LMC6061 Typical Performance Characteristics VS = ± 7.5V, TA = 25°C, Unless otherwise specified (Continued) Inverting Small Signal Pulse Response Inverting Large Signal Pulse Response DS011422-30 DS011422-30 Non-Inverting Large Signal Pulse Response DS011422-31 DS011422-31 Stability vs Capacitive Load, RL = 20 k DS011422-33 DS011422-33 DS011422-32 DS011422-32 Stability vs Capacitive Load RL = 1 M DS011422-35 DS011422-35 DS011422-34 DS011422-34 duce leakage, but lowers stray input capacitance as well. (See Printed-Circuit-Board Layout for High Impedance Work). The effect of input capacitance can be compensated for by adding a capacitor. Place a capacitor, Cf, around the feedback resistor (as in Figure 1) such that: Applications Hints AMPLIFIER TOPOLOGY The LMC6061 LMC6061 incorporates a novel op-amp design topology that enables it to maintain rail-to-rail output swing even when driving a large load. Instead of relying on a push-pull unity gain output buffer stage, the output stage is taken directly from the internal integrator, which provides both low output impedance and large gain. Special feed-forward compensation design techniques are incorporated to maintain stability over a wider range of operating conditions than traditional micropower op-amps. These features make the LMC6061 LMC6061 both easier to design with, and provide higher speed than products typically found in this ultra-low power class. or R1 CIN R2 Cf Since it is often difficult to know the exact value of CIN, Cf can be experimentally adjusted so that the desired pulse response is achieved. Refer to the LMC660 LMC660 and the LMC662 LMC662 for a more detailed discussion on compensating for input capacitance. COMPENSATING FOR INPUT CAPACITANCE It is quite common to use large values of feedback resistance for amplifiers with ultra-low input current, like the LMC6061 LMC6061. Although the LMC6061 LMC6061 is highly stable over a wide range of operating conditions, certain precautions must be met to achieve the desired pulse response when a large feedback resistor is used. Large feedback resistors and even small values of input capacitance, due to transducers, photodiodes, and circuit board parasitics, reduce phase margins. When high input impedances are demanded, guarding of the LMC6061 LMC6061 is suggested. Guarding input lines will not only re- www.national.com Non-Inverting Small Signal Pulse Response 6 fier with respect to the desired output swing. Open loop gain of the amplifier can also be affected by the pull up resistor (see electrical characteristics). (Continued) DS011422-14 DS011422-14 FIGURE 3. Compensating for Large Capacitive Loads with a Pull Up Resistor DS011422-5 DS011422-5 FIGURE 1. Canceling the Effect of Input Capacitance PRINTED-CIRCUIT-BOARD LAYOUT FOR HIGH-IMPEDANCE WORK It is generally recognized that any circuit which must operate with less than 1000 pA of leakage current requires special layout of the PC board. When one wishes to take advantage of the ultra-low bias current of the LMC6061 LMC6061, typically less than 10 fA, it is essential to have an excellent layout. Fortunately, the techniques of obtaining low leakages are quite simple. First, the user must not ignore the surface leakage of the PC board, even though it may sometimes appear acceptably low, because under conditions of high humidity or dust or contamination, the surface leakage will be appreciable. To minimize the effect of any surface leakage, lay out a ring of foil completely surrounding the LMC6061 LMC6061's inputs and the terminals of capacitors, diodes, conductors, resistors, relay terminals etc. connected to the op-amp's inputs, as in Figure 4. To have a significant effect, guard rings should be placed on both the top and bottom of the PC board. This PC foil must then be connected to a voltage which is at the same voltage as the amplifier inputs, since no leakage current can flow between two points at the same potential. For example, a PC board trace-to-pad resistance of 1012, which is normally considered a very large resistance, could leak 5 pA if the trace were a 5V bus adjacent to the pad of the input. This would cause a 100 times degradation from the LMC6061 LMC6061's actual performance. However, if a guard ring is held within 5 mV of the inputs, then even a resistance of 1011 would cause only 0.05 pA of leakage current. See Figure 5 for typical connections of guard rings for standard op-amp configurations. CAPACITIVE LOAD TOLERANCE All rail-to-rail output swing operational amplifiers have voltage gain in the output stage. A compensation capacitor is normally included in this integrator stage. The frequency location of the dominate pole is affected by the resistive load on the amplifier. Capacitive load driving capability can be optimized by using an appropriate resistive load in parallel with the capacitive load (see typical curves). Direct capacitive loading will reduce the phase margin of many op-amps. A pole in the feedback loop is created by the combination of the op-amp's output impedance and the capacitive load. This pole induces phase lag at the unity-gain crossover frequency of the amplifier resulting in either an oscillatory or underdamped pulse response. With a few external components, op amps can easily indirectly drive capacitive loads, as shown in Figure 2. DS011422-4 DS011422-4 FIGURE 2. LMC6061 LMC6061 Noninverting Gain of 10 Amplifier, Compensated to Handle Capacitive Loads In the circuit of Figure 2, R1 and C1 serve to counteract the loss of phase margin by feeding the high frequency component of the output signal back to the amplifier's inverting input, thereby preserving phase margin in the overall feedback loop. Capacitive load driving capability is enhanced by using a pull up resistor to V+ Figure 3. Typically a pull up resistor conducting 10 µA or more will significantly improve capacitive load responses. The value of the pull up resistor must be determined based on the current sinking capability of the ampli- DS011422-6 DS011422-6 FIGURE 4. Example of Guard Ring in P.C. Board Layout 7 www.national.com LMC6061 LMC6061 Applications Hints LMC6061 LMC6061 Applications Hints (Continued) DS011422-10 DS011422-10 (Input pins are lifted out of PC board and soldered directly to components. All other pins connected to PC board). DS011422-7 DS011422-7 FIGURE 6. Air Wiring Inverting Amplifier Latchup CMOS devices tend to be susceptible to latchup due to their internal parasitic SCR effects. The (I/O) input and output pins look similar to the gate of the SCR. There is a minimum current required to trigger the SCR gate lead. The LMC6061 LMC6061 and LMC6081 LMC6081 are designed to withstand 100 mA surge current on the I/O pins. Some resistive method should be used to isolate any capacitance from supplying excess current to the I/O pins. In addition, like an SCR, there is a minimum holding current for any latchup mode. Limiting current to the supply pins will also inhibit latchup susceptibility. DS011422-8 DS011422-8 Non-Inverting Amplifier Typical Single-Supply Applications (V+ = 5.0 VDC) DS011422-9 DS011422-9 The extremely high input impedance, and low power consumption, of the LMC6061 LMC6061 make it ideal for applications that require battery-powered instrumentation amplifiers. Examples of these types of applications are hand-held pH probes, analytic medical instruments, magnetic field detectors, gas detectors, and silicon based pressure transducers. Follower FIGURE 5. Typical Connections of Guard Rings The designer should be aware that when it is inappropriate to lay out a PC board for the sake of just a few circuits, there is another technique which is even better than a guard ring on a PC board: Don't insert the amplifier's input pin into the board at all, but bend it up in the air and use only air as an insulator. Air is an excellent insulator. In this case you may have to forego some of the advantages of PC board construction, but the advantages are sometimes well worth the effort of using point-to-point up-in-the-air wiring. See Figure 6. www.national.com Figure 7 shows an instrumentation amplifier that features high differential and common mode input resistance ( > 1014), 0.01% gain accuracy at AV = 100, excellent CMRR with 1 k imbalance in bridge source resistance. Input current is less than 100 fA and offset drift is less than 2.5 µV/°C. R2 provides a simple means of adjusting gain over a wide range without degrading CMRR. R7 is an initial trim used to maximize CMRR without using super precision matched resistors. For good CMRR over temperature, low drift resistors should be used. 8 LMC6061 LMC6061 Typical Single-Supply Applications (V+ = 5.0 VDC) (Continued) DS011422-11 DS011422-11 If R1 = R5, R3 = R6, and R4 = R7; then AV 100 for circuit shown (R2 = 9.822k). FIGURE 7. Instrumentation Amplifier DS011422-12 DS011422-12 FIGURE 8. Low-Leakage Sample and Hold DS011422-13 DS011422-13 FIGURE 9. 1 Hz Square Wave Oscillator 9 www.national.com LMC6061 LMC6061 Ordering Information Package Temperature Range Military Industrial -55°C to +125°C Transport Media N08E Rail -40°C to +85°C 8-Pin LMC6061AIN LMC6061AIN Molded DIP LMC6061IN LMC6061IN 8-Pin LMC6061AIM LMC6061AIM, LMC606AIMX LMC606AIMX Small Outline LMC6061IM LMC6061IM, LMC6061IMX LMC6061IMX 8-Pin LMC6061AMJ/883 LMC6061AMJ/883 M08A 10 Rail Tape and Reel J08A Ceramic DIP www.national.com NSC Drawing Rail LMC6061 LMC6061 Physical Dimensions inches (millimeters) unless otherwise noted 8-Pin Ceramic Dual-In-Line Package Order Number LMC6061AMJ/883 LMC6061AMJ/883 NS Package Number J08A 8-Pin Small Outline Package Order Number LMC6061AIM LMC6061AIM, LMC6061AIMX LMC6061AIMX, LMC6061IM LMC6061IM or LMC6061IMX LMC6061IMX NS Package Number M08A 11 www.national.com LMC6061 LMC6061 Precision CMOS Single Micropower Operational Amplifier Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 8-Pin Molded Dual-In-Line Package Order Number LMC6061AIN LMC6061AIN or LMC6061IN LMC6061IN NS Package Number N08E LIFE SUPPORT POLICY NATIONAL'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. 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