LM3S817 DS-LM3S81 LM3S317 LM3S617 LM3S618 LM3S818 64-KB RS-232C 16C550 - Datasheet Archive

 

LM3S817 Microcontroller D A TA S H E E T DS-LM3S81 7-02 Co pyrigh t © 200 7 Lumin ary Micro, In c. Legal Disclaimers and

 

P REL I MIN AR Y LM3S817 LM3S817 Microcontroller D A TA S H E E T DS-LM3S81 DS-LM3S81 7-02 Co pyrigh t © 200 7 Lumin ary Micro, In c. Legal Disclaimers and Trademark Information INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH LUMINARY MICRO PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN LUMINARY MICRO'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, LUMINARY MICRO ASSUMES NO LIABILITY WHATSOEVER, AND LUMINARY MICRO DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF LUMINARY MICRO'S PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. LUMINARY MICRO'S PRODUCTS ARE NOT INTENDED FOR USE IN MEDICAL, LIFE SAVING, OR LIFE-SUSTAINING APPLICATIONS. Luminary Micro may make changes to specifications and product descriptions at any time, without notice. Contact your local Luminary Micro sales office or your distributor to obtain the latest specifications before placing your product order. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Luminary Micro reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. Copyright © 2007 Luminary Micro, Inc. All rights reserved. Stellaris is a registered trademark and the Luminary Micro logo is a trademark of Luminary Micro, Inc. or its subsidiaries in the United States and other countries. ARM and Thumb are registered trademarks, and Cortex is a trademark of ARM Limited. Other names and brands may be claimed as the property of others. Luminary Micro, Inc. 108 Wild Basin, Suite 350 Austin, TX 78746 Main: +1-512-279-8800 Fax: +1-512-279-8879 http://www.luminarymicro.com 2 May 4, 2007 Preliminary LM3S817 LM3S817 Data Sheet Table of Contents Legal Disclaimers and Trademark Information. 2 Revision History . 17 About This Document. 18 Audience. 18 About This Manual. 18 Related Documents . 18 Documentation Conventions. 18 1. Architectural Overview . 21 1.1 1.2 1.3 1.4 1.4.1 1.4.2 1.4.3 1.4.4 1.4.5 1.4.6 1.4.7 1.4.8 1.5 Product Features . 21 Target Applications . 25 High-Level Block Diagram . 26 Functional Overview . 27 ARM CortexTM-M3 . 27 Motor Control Peripherals . 27 Analog Peripherals . 28 Serial Communications Peripherals. 28 System Peripherals. 29 Memory Peripherals. 30 Additional Features . 30 Hardware Details . 31 System Block Diagram . 32 2. ARM Cortex-M3 Processor Core. 33 2.1 2.2 2.2.1 2.2.2 2.2.3 2.2.4 2.2.5 2.2.6 Block Diagram . 34 Functional Description . 34 Serial Wire and JTAG Debug . 34 Embedded Trace Macrocell (ETM) . 35 Trace Port Interface Unit (TPIU) . 35 ROM Table . 35 Memory Protection Unit (MPU) . 35 Nested Vectored Interrupt Controller (NVIC) . 35 3. Memory Map . 41 4. Interrupts . 43 5. JTAG Interface . 46 5.1 5.2 5.2.1 5.2.2 5.2.3 5.2.4 5.3 5.4 5.4.1 5.4.2 Block Diagram . 47 Functional Description . 47 JTAG Interface Pins. 48 JTAG TAP Controller . 49 Shift Registers . 50 Operational Considerations . 50 Initialization and Configuration. 51 Register Descriptions. 52 Instruction Register (IR) . 52 Data Registers . 54 May 4, 2007 3 Preliminary Table of Contents 6. System Control. 56 6.1 6.1.1 6.1.2 6.1.3 6.1.4 6.1.5 6.2 6.3 6.4 Functional Description . 56 Device Identification. 56 Reset Control . 56 Power Control . 59 Clock Control . 59 System Control . 61 Initialization and Configuration. 62 Register Map . 62 Register Descriptions. 63 7. Internal Memory . 98 7.1 7.2 7.2.1 7.2.2 7.3 7.3.1 7.3.2 7.4 7.5 Block Diagram . 98 Functional Description . 98 SRAM Memory . 98 Flash Memory . 99 Initialization and Configuration. 101 Changing Flash Protection Bits . 101 Flash Programming . 102 Register Map . 102 Register Descriptions. 103 8. General-Purpose Input/Outputs (GPIOs) . 115 8.1 8.2 8.2.1 8.2.2 8.2.3 8.2.4 8.2.5 8.2.6 8.3 8.4 8.5 Block Diagram . 116 Functional Description . 116 Data Register Operation . 117 Data Direction . 118 Interrupt Operation. 118 Mode Control . 119 Pad Configuration . 119 Identification. 119 Initialization and Configuration. 119 Register Map . 121 Register Descriptions. 122 9. General-Purpose Timers . 153 9.1 9.2 9.2.1 9.2.2 9.2.3 9.3 9.3.1 9.3.2 9.3.3 9.3.4 9.3.5 9.3.6 9.4 9.5 Block Diagram . 154 Functional Description . 154 GPTM Reset Conditions . 154 32-Bit Timer Operating Modes. 154 16-Bit Timer Operating Modes. 156 Initialization and Configuration. 160 32-Bit One-Shot/Periodic Timer Mode . 160 32-Bit Real-Time Clock (RTC) Mode . 161 16-Bit One-Shot/Periodic Timer Mode . 161 16-Bit Input Edge Count Mode . 161 16-Bit Input Edge Timing Mode . 162 16-Bit PWM Mode. 162 Register Map . 163 Register Descriptions. 164 4 May 4, 2007 Preliminary LM3S817 LM3S817 Data Sheet 10. Watchdog Timer . 185 10.1 10.2 10.3 10.4 10.5 Block Diagram . 185 Functional Description . 186 Initialization and Configuration. 186 Register Map . 186 Register Descriptions. 187 11. Analog-to-Digital Converter (ADC) . 208 11.1 11.2 11.2.1 11.2.2 11.2.3 11.2.4 11.2.5 11.2.6 11.3 11.3.1 11.3.2 11.4 11.5 Block Diagram . 209 Functional Description . 209 Sample Sequencers . 209 Module Control . 210 Hardware Sample Averaging Circuit. 211 Analog-to-Digital Converter . 211 Test Modes . 211 Internal Temperature Sensor . 211 Initialization and Configuration. 211 Module Initialization . 212 Sample Sequencer Configuration . 212 Register Map . 212 Register Descriptions. 213 12. Universal Asynchronous Receivers/Transmitters (UARTs). 238 12.1 12.2 12.2.1 12.2.2 12.2.3 12.2.4 12.2.5 12.2.6 12.3 12.4 12.5 Block Diagram . 239 Functional Description . 239 Transmit/Receive Logic . 239 Baud-Rate Generation . 240 Data Transmission . 241 FIFO Operation . 241 Interrupts. 241 Loopback Operation . 242 Initialization and Configuration. 242 Register Map . 243 Register Descriptions. 244 13. Synchronous Serial Interface (SSI) . 274 13.1 13.2 13.2.1 13.2.2 13.2.3 13.2.4 13.3 13.4 13.5 Block Diagram . 274 Functional Description . 275 Bit Rate Generation . 275 FIFO Operation . 275 Interrupts. 275 Frame Formats . 276 Initialization and Configuration. 283 Register Map . 284 Register Descriptions. 285 14. Analog Comparator. 309 14.1 14.2 14.2.1 14.3 Block Diagram . 309 Functional Description . 309 Internal Reference Programming. 310 Initialization and Configuration. 311 May 4, 2007 5 Preliminary Table of Contents 14.4 14.5 Register Map . 312 Register Descriptions. 312 15. Pulse Width Modulator (PWM) . 320 15.1 15.2 15.2.1 15.2.2 15.2.3 15.2.4 15.2.5 15.2.6 15.2.7 15.2.8 15.3 15.4 15.5 Block Diagram . 320 Functional Description . 320 PWM Timer . 320 PWM Comparators . 320 PWM Signal Generator . 321 Dead-Band Generator . 322 Interrupt Selector . 322 Synchronization Methods . 322 Fault Conditions . 323 Output Control Block. 323 Initialization and Configuration. 323 Register Map . 324 Register Descriptions. 325 16. Pin Diagram . 349 17. Signal Tables . 350 18. Operating Characteristics . 360 19. Electrical Characteristics . 361 19.1 19.1.1 19.1.2 19.1.3 19.1.4 19.1.5 19.2 19.2.1 19.2.2 19.2.3 19.2.4 19.2.5 19.2.6 19.2.7 19.2.8 DC Characteristics . 361 Maximum Ratings . 361 Recommended DC Operating Conditions . 361 On-Chip Low Drop-Out (LDO) Regulator Characteristics . 362 Power Specifications . 363 Flash Memory Characteristics . 364 AC Characteristics . 364 Load Conditions . 364 Clocks . 364 Analog-to-Digital Converter . 365 Analog Comparator. 366 Synchronous Serial Interface (SSI) . 366 JTAG and Boundary Scan . 368 General-Purpose I/O. 370 Reset . 370 20. Package Information. 373 Appendix A. Serial Flash Loader . 374 21.1 21.1.1 21.1.2 21.2 21.2.1 21.2.2 21.2.3 21.3 21.3.1 21.3.2 21.3.3 21.3.4 Interfaces . 374 UART . 374 SSI . 374 Packet Handling. 374 Packet Format . 375 Sending Packets . 375 Receiving Packets . 375 Commands . 375 COMMAND_PING (0x20) . 376 COMMAND_GET_STATUS (0x23) . 376 COMMAND_DOWNLOAD (0x21). 376 COMMAND_SEND_DATA (0x24) . 376 6 May 4, 2007 Preliminary LM3S817 LM3S817 Data Sheet 21.3.5 COMMAND_RUN (0x22) . 377 21.3.6 COMMAND_RESET (0x25). 377 Ordering and Contact Information . 379 Ordering Information. 379 Development Kit . 379 Company Information . 379 Support Information . 380 May 4, 2007 7 Preliminary List of Figures List of Figures Figure 1-1. Figure 1-2. Figure 2-1. Figure 2-2. Figure 5-1. Figure 5-2. Figure 5-3. Figure 5-4. Figure 5-5. Figure 6-1. Figure 6-2. Figure 7-1. Figure 8-1. Figure 8-2. Figure 8-3. Figure 8-4. Figure 9-1. Figure 9-2. Figure 9-3. Figure 9-4. Figure 10-1. Figure 11-1. Figure 11-2. Figure 12-1. Figure 12-2. Figure 13-1. Figure 13-2. Figure 13-3. Figure 13-4. Figure 13-5. Figure 13-6. Figure 13-7. Figure 13-8. Figure 13-9. Figure 13-10. Figure 13-11. Figure 13-12. Figure 14-1. Figure 14-2. Figure 14-3. Figure 15-1. Figure 15-2. Figure 15-3. Figure 15-4. Figure 15-5. Figure 16-1. Stellaris® High-Level Block Diagram . 26 LM3S817 LM3S817 Controller System-Level Block Diagram . 32 CPU Block Diagram . 34 TPIU Block Diagram . 35 JTAG Module Block Diagram . 47 Test Access Port State Machine . 50 IDCODE Register Format. 54 BYPASS Register Format . 54 Boundary Scan Register Format . 55 External Circuitry to Extend Reset. 57 Main Clock Tree . 60 Flash Block Diagram . 98 GPIO Module Block Diagram . 116 GPIO Port Block Diagram. 117 GPIODATA Write Example. 118 GPIODATA Read Example . 118 GPTM Module Block Diagram . 154 16-Bit Input Edge Count Mode Example . 158 16-Bit Input Edge Time Mode Example. 159 16-Bit PWM Mode Example . 160 WDT Module Block Diagram . 185 ADC Module Block Diagram. 209 Internal Temperature Sensor Characteristic. 211 UART Module Block Diagram. 239 UART Character Frame. 240 SSI Module Block Diagram. 274 TI Synchronous Serial Frame Format (Single Transfer). 276 TI Synchronous Serial Frame Format (Continuous Transfer) . 277 Freescale SPI Format (Single Transfer) with SPO=0 and SPH=0 . 278 Freescale SPI Format (Continuous Transfer) with SPO=0 and SPH=0 . 278 Freescale SPI Frame Format with SPO=0 and SPH=1. 279 Freescale SPI Frame Format (Single Transfer) with SPO=1 and SPH=0. 279 Freescale SPI Frame Format (Continuous Transfer) with SPO=1 and SPH=0. 280 Freescale SPI Frame Format with SPO=1 and SPH=1. 280 MICROWIRE Frame Format (Single Frame). 281 MICROWIRE Frame Format (Continuous Transfer) . 282 MICROWIRE Frame Format, SSIFss Input Setup and Hold Requirements. 283 Analog Comparator Module Block Diagram . 309 Structure of Comparator Unit. 310 Comparator Internal Reference Structure . 311 PWM Module Block Diagram. 320 PWM Count-Down Mode. 321 PWM Count-Up/Down Mode . 321 PWM Generation Example In Count-Up/Down Mode . 322 PWM Dead-Band Generator . 322 Pin Connection Diagram . 349 8 May 4, 2007 Preliminary LM3S817 LM3S817 Data Sheet Figure 19-1. Figure 19-2. Figure 19-3. Figure 19-4. Figure 19-5. Figure 19-6. Figure 19-7. Figure 19-8. Figure 19-9. Figure 19-10. Figure 19-11. Figure 19-12. Figure 19-13. Figure 20-1. Load Conditions. 364 SSI Timing for TI Frame Format (FRF=01), Single Transfer Timing Measurement . 367 SSI Timing for MICROWIRE Frame Format (FRF=10), Single Transfer. 367 SSI Timing for SPI Frame Format (FRF=00), with SPH=1. 367 JTAG Test Clock Input Timing. 369 JTAG Test Access Port (TAP) Timing . 369 JTAG TRST Timing . 369 External Reset Timing (RST). 371 Power-On Reset Timing . 371 Brown-Out Reset Timing . 371 Software Reset Timing . 371 Watchdog Reset Timing . 372 LDO Reset Timing . 372 48-Pin LQFP Package. 373 May 4, 2007 9 Preliminary List of Tables List of Tables Table 0-1. Table 3-1. Table 4-1. Table 4-2. Table 5-1. Table 5-2. Table 6-1. Table 6-2. Table 6-3. Table 6-4. Table 7-1. Table 7-2. Table 8-1. Table 8-2. Table 8-3. Table 9-1. Table 9-2. Table 10-1. Table 11-1. Table 11-2. Table 12-1. Table 13-1. Table 14-1. Table 14-2. Table 14-3. Table 15-1. Table 15-2. Table 17-1. Table 17-2. Table 17-3. Table 17-4. Table 18-1. Table 18-2. Table 19-1. Table 19-2. Table 19-3. Table 19-4. Table 19-5. Table 19-6. Table 19-7. Table 19-8. Table 19-9. Table 19-10. Table 19-11. Table 19-12. Table 19-13. Table 19-14. Documentation Conventions . 18 Memory Map. 41 Exception Types . 43 Interrupts . 44 JTAG Port Pins Reset State . 48 JTAG Instruction Register Commands . 52 System Control Register Map. 62 VADJ to VOUT . 75 PLL Mode Control. 87 Default Crystal Field Values and PLL Programming . 88 Flash Protection Policy Combinations . 100 Flash Register Map . 103 GPIO Pad Configuration Examples . 120 GPIO Interrupt Configuration Example . 120 GPIO Register Map . 121 16-Bit Timer with Prescaler Configurations . 157 GPTM Register Map. 163 WDT Register Map . 186 Samples and FIFO Depth of Sequencers. 209 ADC Register Map. 212 UART Register Map . 243 SSI Register Map . 284 Comparator 0 Operating Modes . 310 Internal Reference Voltage and ACREFCTL Field Values . 311 Analog Comparator Register Map . 312 PWM Register Map . 324 PWM Generator Action Encodings. 344 Signals by Pin Number . 350 Signals by Signal Name . 353 Signals by Function, Except for GPIO . 355 GPIO Pins and Alternate Functions. 358 Temperature Characteristics . 360 Thermal Characteristics. 360 Maximum Ratings. 361 Recommended DC Operating Conditions . 361 LDO Regulator Characteristics. 362 Power Specifications . 363 Flash Memory Characteristics . 364 Phase Locked Loop (PLL) Characteristics . 364 Clock Characteristics. 365 ADC Characteristics . 365 Analog Comparator Characteristics. 366 Analog Comparator Voltage Reference Characteristics. 366 SSI Characteristics . 366 JTAG Characteristics. 368 GPIO Characteristics. 370 Reset Characteristics . 370 10 May 4, 2007 Preliminary LM3S817 LM3S817 Data Sheet List of Registers ARM Cortex-M3 Processor Core . 33 Register 1: Register 2: Register 3: SysTick Control and Status Register. 38 SysTick Reload Value Register . 39 SysTick Current Value Register . 40 System Control . 56 Register 1: Register 2: Register 3: Register 4: Register 5: Register 6: Register 7: Register 8: Register 9: Register 10: Register 11: Register 12: Register 13: Register 14: Register 15: Register 16: Register 17: Register 18: Register 19: Register 20: Register 21: Register 22: Register 23: Register 24: Register 25: Register 26: Register 27: Register 28: Register 29: Register 30: Device Identification 0 (DID0), offset 0x000 . 64 Device Identification 1 (DID1), offset 0x004 . 65 Device Capabilities 0 (DC0), offset 0x008. 67 Device Capabilities 1 (DC1), offset 0x010. 68 Device Capabilities 2 (DC2), offset 0x014. 70 Device Capabilities 3 (DC3), offset 0x018. 71 Device Capabilities 4 (DC4), offset 0x01C . 73 Power-On and Brown-Out Reset Control (PBORCTL), offset 0x030 . 74 LDO Power Control (LDOPCTL), offset 0x034. 75 Software Reset Control 0 (SRCR0), offset 0x040 . 76 Software Reset Control 1 (SRCR1), offset 0x044 . 77 Software Reset Control 2 (SRCR2), offset 0x048 . 78 Raw Interrupt Status (RIS), offset 0x050. 79 Interrupt Mask Control (IMC), offset 0x054 . 80 Masked Interrupt Status and Clear (MISC), offset 0x058. 82 Reset Cause (RESC), offset 0x05C . 83 Run-Mode Clock Configuration (RCC), offset 0x060. 84 XTAL to PLL Translation (PLLCFG), offset 0x064 . 89 Run-Mode Clock Gating Control 0 (RCGC0), offset 0x100 . 90 Sleep-Mode Clock Gating Control 0 (SCGC0), offset 0x110. 90 Deep-Sleep-Mode Clock Gating Control 0 (DCGC0), offset 0x120. 90 Run-Mode Clock Gating Control 1 (RCGC1), offset 0x104 . 92 Sleep-Mode Clock Gating Control 1 (SCGC1), offset 0x114. 92 Deep-Sleep-Mode Clock Gating Control 1 (DCGC1), offset 0x124. 92 Run-Mode Clock Gating Control 2 (RCGC2), offset 0x108 . 94 Sleep-Mode Clock Gating Control 2 (SCGC2), offset 0x118. 94 Deep-Sleep-Mode Clock Gating Control 2 (DCGC2), offset 0x128. 94 Deep-Sleep Clock Configuration (DSLPCLKCFG), offset 0x144 . 95 Clock Verification Clear (CLKVCLR), offset 0x150. 96 Allow Unregulated LDO to Reset the Part (LDOARST), offset 0x160 . 97 Internal Memory . 98 Register 1: Register 2: Register 3: Register 4: Register 5: Register 6: Register 7: Register 8: Register 9: Flash Memory Protection Read Enable (FMPRE), offset 0x130 . 104 Flash Memory Protection Program Enable (FMPPE), offset 0x134 . 105 USec Reload (USECRL), offset 0x140. 106 Flash Memory Address (FMA), offset 0x000 . 107 Flash Memory Data (FMD), offset 0x004 . 109 Flash Memory Control (FMC), offset 0x008 . 110 Flash Controller Raw Interrupt Status (FCRIS), offset 0x00C . 112 Flash Controller Interrupt Mask (FCIM), offset 0x010 . 113 Flash Controller Masked Interrupt Status and Clear (FCMISC), offset 0x014. 114 May 4, 2007 11 Preliminary List of Registers General-Purpose Input/Outputs (GPIOs) . 115 Register 1: Register 2: Register 3: Register 4: Register 5: Register 6: Register 7: Register 8: Register 9: Register 10: Register 11: Register 12: Register 13: Register 14: Register 15: Register 16: Register 17: Register 18: Register 19: Register 20: Register 21: Register 22: Register 23: Register 24: Register 25: Register 26: Register 27: Register 28: Register 29: Register 30: GPIO Data (GPIODATA), offset 0x000 . 123 GPIO Direction (GPIODIR), offset 0x400 . 124 GPIO Interrupt Sense (GPIOIS), offset 0x404. 125 GPIO Interrupt Both Edges (GPIOIBE), offset 0x408. 126 GPIO Interrupt Event (GPIOIEV), offset 0x40C. 127 GPIO Interrupt Mask (GPIOIM), offset 0x410. 128 GPIO Raw Interrupt Status (GPIORIS), offset 0x414. 129 GPIO Masked Interrupt Status (GPIOMIS), offset 0x418 . 130 GPIO Interrupt Clear (GPIOICR), offset 0x41C. 131 GPIO Alternate Function Select (GPIOAFSEL), offset 0x420 . 132 GPIO 2-mA Drive Select (GPIODR2R), offset 0x500. 133 GPIO 4-mA Drive Select (GPIODR4R), offset 0x504. 134 GPIO 8-mA Drive Select (GPIODR8R), offset 0x508. 135 GPIO Open Drain Select (GPIOODR), offset 0x50C. 136 GPIO Pull-Up Select (GPIOPUR), offset 0x510 . 137 GPIO Pull-Down Select (GPIOPDR), offset 0x514. 138 GPIO Slew Rate Control Select (GPIOSLR), offset 0x518. 139 GPIO Digital Input Enable (GPIODEN), offset 0x51C . 140 GPIO Peripheral Identification 4 (GPIOPeriphID4), offset 0xFD0 . 141 GPIO Peripheral Identification 5 (GPIOPeriphID5), offset 0xFD4 . 142 GPIO Peripheral Identification 6 (GPIOPeriphID6), offset 0xFD8 . 143 GPIO Peripheral Identification 7 (GPIOPeriphID7), offset 0xFDC. 144 GPIO Peripheral Identification 0 (GPIOPeriphID0), offset 0xFE0 . 145 GPIO Peripheral Identification 1(GPIOPeriphID1), offset 0xFE4 . 146 GPIO Peripheral Identification 2 (GPIOPeriphID2), offset 0xFE8 . 147 GPIO Peripheral Identification 3 (GPIOPeriphID3), offset 0xFEC. 148 GPIO PrimeCell Identification 0 (GPIOPCellID0), offset 0xFF0 . 149 GPIO PrimeCell Identification 1 (GPIOPCellID1), offset 0xFF4 . 150 GPIO PrimeCell Identification 2 (GPIOPCellID2), offset 0xFF8 . 151 GPIO PrimeCell Identification 3 (GPIOPCellID3), offset 0xFFC. 152 General-Purpose Timers . 153 Register 1: Register 2: Register 3: Register 4: Register 5: Register 6: Register 7: Register 8: Register 9: Register 10: Register 11: Register 12: Register 13: Register 14: GPTM Configuration (GPTMCFG), offset 0x000. 165 GPTM TimerA Mode (GPTMTAMR), offset 0x004 . 166 GPTM TimerB Mode (GPTMTBMR), offset 0x008 . 167 GPTM Control (GPTMCTL), offset 0x00C. 168 GPTM Interrupt Mask (GPTMIMR), offset 0x018 . 170 GPTM Raw Interrupt Status (GPTMRIS), offset 0x01C . 172 GPTM Masked Interrupt Status (GPTMMIS), offset 0x020 . 173 GPTM Interrupt Clear (GPTMICR), offset 0x024. 174 GPTM TimerA Interval Load (GPTMTAILR), offset 0x028 . 175 GPTM TimerB Interval Load (GPTMTBILR), offset 0x02C. 176 GPTM TimerA Match (GPTMTAMATCHR), offset 0x030 . 177 GPTM TimerB Match (GPTMTBMATCHR), offset 0x034 . 178 GPTM TimerA Prescale (GPTMTAPR), offset 0x038. 179 GPTM TimerB Prescale (GPTMTBPR), offset 0x03C . 180 12 May 4, 2007 Preliminary LM3S817 LM3S817 Data Sheet Register 15: Register 16: Register 17: Register 18: GPTM TimerA Prescale Match (GPTMTAPMR), offset 0x040. 181 GPTM TimerB Prescale Match (GPTMTBPMR), offset 0x044. 182 GPTM TimerA (GPTMTAR), offset 0x048 . 183 GPTM TimerB (GPTMTBR), offset 0x04C . 184 Watchdog Timer. 185 Register 1: Register 2: Register 3: Register 4: Register 5: Register 6: Register 7: Register 8: Register 9: Register 10: Register 11: Register 12: Register 13: Register 14: Register 15: Register 16: Register 17: Register 18: Register 19: Register 20: Watchdog Load (WDTLOAD), offset 0x000 . 188 Watchdog Value (WDTVALUE), offset 0x004 . 189 Watchdog Control (WDTCTL), offset 0x008. 190 Watchdog Interrupt Clear (WDTICR), offset 0x00C . 191 Watchdog Raw Interrupt Status (WDTRIS), offset 0x010 . 192 Watchdog Masked Interrupt Status (WDTMIS), offset 0x014. 193 Watchdog Lock (WDTLOCK), offset 0xC00 . 194 Watchdog Test (WDTTEST), offset 0x418 . 195 Watchdog Peripheral Identification 4 (WDTPeriphID4), offset 0xFD0. 196 Watchdog Peripheral Identification 5 (WDTPeriphID5), offset 0xFD4. 197 Watchdog Peripheral Identification 6 (WDTPeriphID6), offset 0xFD8. 198 Watchdog Peripheral Identification 7 (WDTPeriphID7), offset 0xFDC . 199 Watchdog Peripheral Identification 0 (WDTPeriphID0), offset 0xFE0 . 200 Watchdog Peripheral Identification 1 (WDTPeriphID1), offset 0xFE4 . 201 Watchdog Peripheral Identification 2 (WDTPeriphID2), offset 0xFE8 . 202 Watchdog Peripheral Identification 3 (WDTPeriphID3), offset 0xFEC . 203 Watchdog PrimeCell Identification 0 (WDTPCellID0), offset 0xFF0. 204 Watchdog PrimeCell Identification 1 (WDTPCellID1), offset 0xFF4. 205 Watchdog PrimeCell Identification 2 (WDTPCellID2), offset 0xFF8. 206 Watchdog PrimeCell Identification 3 (WDTPCellID3 ), offset 0xFFC . 207 Analog-to-Digital Converter (ADC). 208 Register 1: Register 2: Register 3: Register 4: Register 5: Register 6: Register 7: Register 8: Register 9: Register 10: Register 11: Register 12: Register 13: Register 14: Register 15: Register 16: Register 17: Register 18: Register 19: Register 20: ADC Active Sample Sequencer (ADCACTSS), offset 0x000 . 214 ADC Raw Interrupt Status (ADCRIS), offset 0x004. 215 ADC Interrupt Mask (ADCIM), offset 0x008 . 216 ADC Interrupt Status and Clear (ADCISC), offset 0x00C. 217 ADC Overflow Status (ADCOSTAT), offset 0x010 . 218 ADC Event Multiplexer Select (ADCEMUX), offset 0x014 . 219 ADC Underflow Status (ADCUSTAT), offset 0x018 . 220 ADC Sample Sequencer Priority (ADCSSPRI), offset 0x020. 221 ADC Processor Sample Sequence Initiate (ADCPSSI), offset 0x028 . 222 ADC Sample Averaging Control (ADCSAC), offset 0x030 . 223 ADC Sample Sequence Input Multiplexer Select 0 (ADCSSMUX0), offset 0x040. 224 ADC Sample Sequence Control 0 (ADCSSCTL0), offset 0x044. 226 ADC Sample Sequence Result FIFO 0 (ADCSSFIFO0), offset 0x048. 228 ADC Sample Sequence FIFO 0 Status (ADCSSFSTAT0), offset 0x04C. 229 ADC Sample Sequence Input Multiplexer Select 1 (ADCSSMUX1), offset 0x060. 230 ADC Sample Sequence Control 1 (ADCSSCTL1), offset 0x064. 231 ADC Sample Sequence Result FIFO 1 (ADCSSFIFO1), offset 0x068. 231 ADC Sample Sequence FIFO 1 Status (ADCSSFSTAT1), offset 0x06C. 231 ADC Sample Sequence Input Multiplexer Select 2 (ADCSSMUX2), offset 0x080. 232 ADC Sample Sequence Control 2 (ADCSSCTL2), offset 0x084. 233 May 4, 2007 13 Preliminary List of Registers Register 21: Register 22: Register 23: Register 24: Register 25: Register 26: Register 27: ADC Sample Sequence Result FIFO 2 (ADCSSFIFO2), offset 0x088. 233 ADC Sample Sequence FIFO 2 Status (ADCSSFSTAT2), offset 0x08C. 233 ADC Sample Sequence Input Multiplexer Select 3 (ADCSSMUX3), offset 0x0A0 . 234 ADC Sample Sequence Control 3 (ADCSSCTL3), offset 0x0A4 . 235 ADC Sample Sequence Result FIFO 3 (ADCSSFIFO3), offset 0x0A8 . 235 ADC Sample Sequence FIFO 3 Status (ADCSSFSTAT3), offset 0x0AC . 235 ADC Test Mode Loopback (ADCTMLB), offset 0x100 . 236 Universal Asynchronous Receivers/Transmitters (UARTs) . 238 Register 1: Register 2: Register 3: Register 4: Register 5: Register 6: Register 7: Register 8: Register 9: Register 10: Register 11: Register 12: Register 13: Register 14: Register 15: Register 16: Register 17: Register 18: Register 19: Register 20: Register 21: Register 22: Register 23: Register 24: UART Data (UARTDR), offset 0x000 . 245 UART Receive Status/Error Clear (UARTRSR/UARTECR), offset 0x004 . 247 UART Flag (UARTFR), offset 0x018 . 249 UART Integer Baud-Rate Divisor (UARTIBRD), offset 0x024 . 251 UART Fractional Baud-Rate Divisor (UARTFBRD), offset 0x028 . 252 UART Line Control (UARTLCRH), offset 0x02C . 253 UART Control (UARTCTL), offset 0x030. 255 UART Interrupt FIFO Level Select (UARTIFLS), offset 0x034 . 256 UART Interrupt Mask (UARTIM), offset 0x038 . 257 UART Raw Interrupt Status (UARTRIS), offset 0x03C. 259 UART Masked Interrupt Status (UARTMIS), offset 0x040 . 260 UART Interrupt Clear (UARTICR), offset 0x044. 261 UART Peripheral Identification 4 (UARTPeriphID4), offset 0xFD0. 262 UART Peripheral Identification 5 (UARTPeriphID5), offset 0xFD4. 263 UART Peripheral Identification 6 (UARTPeriphID6), offset 0xFD8. 264 UART Peripheral Identification 7 (UARTPeriphID7), offset 0xFDC . 265 UART Peripheral Identification 0 (UARTPeriphID0), offset 0xFE0. 266 UART Peripheral Identification 1 (UARTPeriphID1), offset 0xFE4. 267 UART Peripheral Identification 2 (UARTPeriphID2), offset 0xFE8. 268 UART Peripheral Identification 3 (UARTPeriphID3), offset 0xFEC . 269 UART PrimeCell Identification 0 (UARTPCellID0), offset 0xFF0. 270 UART PrimeCell Identification 1 (UARTPCellID1), offset 0xFF4. 271 UART PrimeCell Identification 2 (UARTPCellID2), offset 0xFF8. 272 UART PrimeCell Identification 3 (UARTPCellID3), offset 0xFFC . 273 Synchronous Serial Interface (SSI) . 274 Register 1: Register 2: Register 3: Register 4: Register 5: Register 6: Register 7: Register 8: Register 9: Register 10: Register 11: Register 12: Register 13: SSI Control 0 (SSICR0), offset 0x000 . 286 SSI Control 1 (SSICR1), offset 0x004 . 288 SSI Data (SSIDR), offset 0x008 . 290 SSI Status (SSISR), offset 0x00C . 291 SSI Clock Prescale (SSICPSR), offset 0x010 . 292 SSI Interrupt Mask (SSIIM), offset 0x014 . 293 SSI Raw Interrupt Status (SSIRIS), offset 0x018 . 294 SSI Masked Interrupt Status (SSIMIS), offset 0x01C. 295 SSI Interrupt Clear (SSIICR), offset 0x020. 296 SSI Peripheral Identification 4 (SSIPeriphID4), offset 0xFD0. 297 SSI Peripheral Identification 5 (SSIPeriphID5), offset 0xFD4. 298 SSI Peripheral Identification 6 (SSIPeriphID6), offset 0xFD8. 299 SSI Peripheral Identification 7 (SSIPeriphID7), offset 0xFDC . 300 14 May 4, 2007 Preliminary LM3S817 LM3S817 Data Sheet Register 14: Register 15: Register 16: Register 17: Register 18: Register 19: Register 20: Register 21: SSI Peripheral Identification 0 (SSIPeriphID0), offset 0xFE0. 301 SSI Peripheral Identification 1 (SSIPeriphID1), offset 0xFE4. 302 SSI Peripheral Identification 2 (SSIPeriphID2), offset 0xFE8. 303 SSI Peripheral Identification 3 (SSIPeriphID3), offset 0xFEC . 304 SSI PrimeCell Identification 0 (SSIPCellID0), offset 0xFF0. 305 SSI PrimeCell Identification 1 (SSIPCellID1), offset 0xFF4. 306 SSI PrimeCell Identification 2 (SSIPCellID2), offset 0xFF8. 307 SSI PrimeCell Identification 3 (SSIPCellID3), offset 0xFFC . 308 Analog Comparator . 309 Register 1: Register 2: Register 3: Register 4: Register 5: Register 6: Analog Comparator Masked Interrupt Status (ACMIS), offset 0x00. 313 Analog Comparator Raw Interrupt Status (ACRIS), offset 0x04. 314 Analog Comparator Interrupt Enable (ACINTEN), offset 0x08 . 315 Analog Comparator Reference Voltage Control (ACREFCTL), offset 0x10 . 316 Analog Comparator Status 0 (ACSTAT0), offset 0x20 . 317 Analog Comparator Control 0 (ACCTL0), offset 0x24 . 318 Pulse Width Modulator (PWM). 320 Register 1: Register 2: Register 3: Register 4: Register 5: Register 6: Register 7: Register 8: Register 9: Register 10: Register 11: Register 12: Register 13: Register 14: Register 15: Register 16: Register 17: Register 18: Register 19: Register 20: Register 21: Register 22: PWM Master Control (PWMCTL), offset 0x000. 326 PWM Time Base Sync (PWMSYNC), offset 0x004. 327 PWM Output Enable (PWMENABLE), offset 0x008. 328 PWM Output Inversion (PWMINVERT), offset 0x00C. 329 PWM Output Fault (PWMFAULT), offset 0x010. 330 PWM Interrupt Enable (PWMINTEN), offset 0x014. 331 PWM Raw Interrupt Status (PWMRIS), offset 0x018 . 332 PWM Interrupt Status and Clear (PWMISC), offset 0x01C . 333 PWM Status (PWMSTATUS), offset 0x020. 334 PWM0 Control (PWM0CTL), offset 0x040. 335 PWM0 Interrupt Enable (PWM0INTEN), offset 0x044. 336 PWM0 Raw Interrupt Status (PWM0RIS), offset 0x048 . 337 PWM0 Interrupt Status and Clear (PWM0ISC), offset 0x04C . 338 PWM0 Load (PWM0LOAD), offset 0x050 . 339 PWM0 Counter (PWM0COUNT), offset 0x054 . 340 PWM0 Compare A (PWM0CMPA), offset 0x058 . 341 PWM0 Compare B (PWM0CMPB), offset 0x05C. 342 PWM0 Generator A Control (PWM0GENA), offset 0x060. 343 PWM0 Generator B Control (PWM0GENB), offset 0x064. 345 PWM0 Dead-Band Control (PWM0DBCTL), offset 0x068 . 346 PWM0 Dead-Band Rising-Edge Delay (PWM0DBRISE), offset 0x06C . 347 PWM0 Dead-Band Falling-Edge-Delay (PWM0DBFALL), offset 0x070. 348 Pin Diagram . 349 Signal Tables. 350 Operating Characteristics . 360 Electrical Characteristics . 361 Package Information . 373 May 4, 2007 15 Preliminary LM3S817 LM3S817 Data Sheet Revision History This table provides a summary of the document revisions. Date Revision Description February 2007 00 Initial release of LM3S317 LM3S317, LM3S617 LM3S617, LM3S618 LM3S618, LM3S817 LM3S817 and LM3S818 LM3S818 data sheet to customers. April 2007 01 Second release of LM3S317 LM3S317, LM3S618 LM3S618, and LM3S817 LM3S817 data sheets. Includes the following changes: · Added information to the Thermal chapter. · Added information to the Power Specifications section in the Electrical chapter. April 2007 02 Third release of LM3S317 LM3S317, LM3S617 LM3S617, LM3S618 LM3S618, LM3S817 LM3S817, and LM3S818 LM3S818 data sheets. Includes the following changes: · In the Internal Memory chapter, added information on code protection. · In the ARM Cortex-M3 Processor Core, Architecture Overview, and General-Purpose Timers chapters, added information for the System Timer (SysTick). · In the Timers chapter, added note to the 16-Bit Input Edge Time Mode section. May 4, 2007 17 Preliminary About This Document About This Document This data sheet provides reference information for the LM3S817 LM3S817 microcontroller, describing the functional blocks of the system-on-chip (SoC) device designed around the ARM® CortexTM-M3 core. Audience This manual is intended for system software developers, hardware designers, and application developers. About This Manual This document is organized into sections that correspond to each major feature. Related Documents The following documents are referenced by the data sheet, and available on the documentation CD or from the Luminary Micro web site at www.luminarymicro.com: ARM® CortexTM-M3 Technical Reference Manual CoreSightTM Design Kit Technical Reference Manual ARM® v7-M Architecture Application Level Reference Manual The following related documents are also referenced: IEEE Standard 1149.1-Test Access Port and Boundary-Scan Architecture This documentation list was current as of publication date. Please check the Luminary Micro web site for additional documentation, including application notes and white papers. Documentation Conventions This document uses the conventions shown in Table 0-1. Table 0-1. Documentation Conventions Notation Meaning General Register Notation REGISTER APB registers are indicated in uppercase bold. For example, PBORCTL is the Power-On and Brown-Out Reset Control register. If a register name contains a lowercase n, it represents more than one register. For example, SRCRn represents any (or all) of the three Software Reset Control registers: SRCR0, SRCR1, and SRCR2. bit A single bit in a register. bit field Two or more consecutive and related bits. offset 0xnnn A hexadecimal increment to a register's address, relative to that module's base address as specified in Table 3-1, "Memory Map," on page 41. 18 May 4, 2007 Preliminary LM3S817 LM3S817 Data Sheet Table 0-1. Documentation Conventions Notation Meaning Register N Registers are numbered consecutively throughout the document to aid in referencing them. The register number has no meaning to software. reserved Register bits marked reserved are reserved for future use. Reserved bits return an indeterminate value, and should never be changed. Only write a reserved bit with its current value. yy:xx The range of register bits inclusive from xx to yy. For example, 31:15 means bits 15 through 31 in that register. Register Bit/Field Types This value in the register bit diagram indicates whether software running on the controller can change the value of the bit field. RO Software can read this field. Always write the chip reset value. R/W Software can read or write this field. R/W1C Software can read or write this field. A write of a 0 to a W1C bit does not affect the bit value in the register. A write of a 1 clears the value of the bit in the register; the remaining bits remain unchanged. This register type is primarily used for clearing interrupt status bits where the read operation provides the interrupt status and the write of the read value clears only the interrupts being reported at the time the register was read. W1C Software can write this field. A write of a 0 to a W1C bit does not affect the bit value in the register. A write of a 1 clears the value of the bit in the register; the remaining bits remain unchanged. A read of the register returns no meaningful data. This register is typically used to clear the corresponding bit in an interrupt register. WO Only a write by software is valid; a read of the register returns no meaningful data. Register Bit/Field Reset Value This value in the register bit diagram shows the bit/field value after any reset, unless noted. 0 Bit cleared to 0 on chip reset. 1 Bit set to 1 on chip reset. ­ Nondeterministic. Pin/Signal Notation [] Pin alternate function; a pin defaults to the signal without the brackets. pin Refers to the physical connection on the package. signal Refers to the electrical signal encoding of a pin. May 4, 2007 19 Preliminary About This Document Table 0-1. Documentation Conventions Notation Meaning assert a signal Change the value of the signal from the logically False state to the logically True state. For active High signals, the asserted signal value is 1 (High); for active Low signals, the asserted signal value is 0 (Low). The active polarity (High or Low) is defined by the signal name (see SIGNAL and SIGNAL below). deassert a signal Change the value of the signal from the logically True state to the logically False state. SIGNAL Signal names are in uppercase and in the Courier font. An overbar on a signal name indicates that it is active Low. To assert SIGNAL is to drive it Low; to deassert SIGNAL is to drive it High. SIGNAL Signal names are in uppercase and in the Courier font. An active High signal has no overbar. To assert SIGNAL is to drive it High; to deassert SIGNAL is to drive it Low. Numbers X An uppercase X indicates any of several values is allowed, where X can be any legal pattern. For example, a binary value of 0X00 can be either 0100 or 0000, a hex value of 0xX is 0x0 or 0x1, and so on. 0x Hexadecimal numbers have a prefix of 0x. For example, 0x00FF is the hexadecimal number FF. Binary numbers are indicated with a b suffix, for example, 1011b. Decimal numbers are written without a prefix or suffix. 20 May 4, 2007 Preliminary LM3S817 LM3S817 Data Sheet 1 Architectural Overview The Luminary Micro Stellaris® family of microcontrollers-the first ARM® CortexTM-M3 based controllers-brings high-performance 32-bit computing to cost-sensitive embedded microcontroller applications. These pioneering parts deliver customers 32-bit performance at a cost equivalent to legacy 8- and 16-bit devices, all in a package with a small footprint. The LM3S817 LM3S817 controller in the Stellaris family offers the advantages of ARM's widely available development tools, System-on-Chip (SoC) infrastructure IP applications, and a large user community. Additionally, the controller uses ARM's Thumb®-compatible Thumb-2 instruction set to reduce memory requirements and, thereby, cost. Luminary Micro offers a complete solution to get to market quickly, with a customer development board, white papers and application notes, and a strong support, sales, and distributor network. 1.1 Product Features The LM3S817 LM3S817 microcontroller includes the following product features: 32-Bit RISC Performance ­ 32-bit ARM® CortexTM-M3 v7M architecture optimized for small-footprint embedded applications ­ System timer (SysTick) provides a simple, 24-bit clear-on-write, decrementing, wrap-on-zero counter with a flexible control mechanism ­ Thumb®-compatible Thumb-2-only instruction set processor core for high code density ­ 50-MHz operation ­ Hardware-division and single-cycle-multiplication ­ Integrated Nested Vectored Interrupt Controller (NVIC) providing deterministic interrupt handling ­ 26 interrupts with eight priority levels ­ Memory protection unit (MPU) provides a privileged mode for protected operating system functionality ­ Unaligned data access, enabling data to be efficiently packed into memory ­ Atomic bit manipulation (bit-banding) delivers maximum memory utilization and streamlined peripheral control Internal Memory ­ 64-KB 64-KB single-cycle flash · User-managed flash block protection on a 2-KB block basis · User-managed flash data programming · User-defined and managed flash-protection block ­ 8-KB single-cycle SRAM General-Purpose Timers ­ Three timers, each of which can be configured: as a single 32-bit timer, as two 16-bit timers, or to initiate an ADC event ­ 32-bit Timer modes: · Programmable one-shot timer May 4, 2007 21 Preliminary Architectural Overview · Programmable periodic timer · Real-Time Clock when using an external 32.768-KHz clock as the input · User-enabled stalling in periodic and one-shot mode when the controller asserts the CPU Halt flag during debug · ADC event trigger ­ 16-bit Timer modes: · General-purpose timer function with an 8-bit prescaler · Programmable one-shot timer · Programmable periodic timer · User-enabled stalling when the controller asserts CPU Halt flag during debug · ADC event trigger ­ 16-bit Input Capture modes: · Input edge count capture · Input edge time capture ­ 16-bit PWM mode: · Simple PWM mode with software-programmable output inversion of the PWM signal ARM FiRM-compliant Watchdog Timer ­ 32-bit down counter with a programmable load register ­ Separate watchdog clock with an enable ­ Programmable interrupt generation logic with interrupt masking ­ Lock register protection from runaway software ­ Reset generation logic with an enable/disable ­ User-enabled stalling when the controller asserts the CPU Halt flag during debug Synchronous Serial Interface (SSI) ­ Master or slave operation ­ Programmable clock bit rate and prescale ­ Separate transmit and receive FIFOs, 16 bits wide, 8 locations deep ­ Programmable interface operation for Freescale SPI, MICROWIRE, or Texas Instruments synchronous serial interfaces ­ Programmable data frame size from 4 to 16 bits ­ Internal loopback test mode for diagnostic/debug testing UART ­ Two fully programmable 16C550-type UARTs ­ Separate 16x8 transmit (TX) and 16x12 receive (RX) FIFOs to reduce CPU interrupt service loading ­ Programmable baud-rate generator with fractional divider ­ Programmable FIFO length, including 1-byte deep operation providing conventional double-buffered interface 22 May 4, 2007 Preliminary LM3S817 LM3S817 Data Sheet ­ FIFO trigger levels of 1/8, 1/4, 1/2, 3/4, and 7/8 ­ Standard asynchronous communication bits for start, stop, and parity ­ False-start-bit detection ­ Line-break generation and detection ADC ­ Single- and differential-input configurations ­ Six 10-bit channels (inputs) when used as single-ended inputs ­ Sample rate of one million samples/second ­ Flexible, configurable analog-to-digital conversion ­ Four programmable sample conversion sequences from one to eight entries long, with corresponding conversion result FIFOs ­ Each sequence triggered by software or internal event (timers, analog comparators, PWM or GPIO) Analog Comparator ­ One independent integrated analog comparator ­ Configurable for output to: drive an output pin, or generate an interrupt, or initiate an ADC sample sequence ­ Compare external pin input to external pin input or to internal programmable voltage reference PWM ­ Three PWM generator blocks, each with one 16-bit counter, two comparators, a PWM generator, and a dead-band generator ­ One 16-bit counter · Runs in Down or Up/Down mode · Output frequency controlled by a 16-bit load value · Load value updates can be synchronized · Produces output signals at zero and load value ­ Two comparators · Comparator value updates can be synchronized · Produces output signals on match ­ PWM generator · Output PWM signal is constructed based on actions taken as a result of the counter and comparator output signals · Produces two independent PWM signals ­ Dead-band generator · Produces two PWM signals with programmable dead-band delays suitable for driving a half-H bridge · Can be bypassed, leaving input PWM signals unmodified ­ Flexible output control block with PWM output enable of each PWM signal May 4, 2007 23 Preliminary Architectural Overview · PWM output enable of each PWM signal · Optional output inversion of each PWM signal (polarity control) · Optional fault handling for each PWM signal · Synchronization of timers in the PWM generator blocks · Synchronization of timer/comparator updates across the PWM generator blocks · Interrupt status summary of the PWM generator blocks ­ Can initiate an ADC sample sequence GPIOs ­ 1 to 30 GPIOs, depending on configuration ­ 5-V-tolerant input/outputs ­ Programmable interrupt generation as either edge-triggered or level-sensitive ­ Bit masking in both read and write operations through address lines ­ Can initiate an ADC sample sequence ­ Programmable control for GPIO pad configuration: · Weak pull-up or pull-down resistors · 2-mA, 4-mA, and 8-mA pad drive · Slew rate control for the 8-mA drive · Open drain enables · Digital input enables Power ­ On-chip Low Drop-Out (LDO) voltage regulator, with programmable output user-adjustable from 2.25 V to 2.75 V ­ Low-power options on controller: Sleep and Deep-sleep modes ­ Low-power options for peripherals: software controls shutdown of individual peripherals ­ User-enabled LDO unregulated voltage detection and automatic reset ­ 3.3-V supply brownout detection and reporting via interrupt or reset ­ On-chip temperature sensor Flexible Reset Sources ­ Power-on reset (POR) ­ Reset pin assertion ­ Brown-out (BOR) detector alerts to system power drops ­ Software reset ­ Watchdog timer reset ­ Internal low drop-out (LDO) regulator output goes unregulated Additional Features ­ Six reset sources ­ Programmable clock source control 24 May 4, 2007 Preliminary LM3S817 LM3S817 Data Sheet ­ Clock gating to individual peripherals for power savings ­ IEEE 1149.1-1990 compliant Test Access Port (TAP) controller ­ Debug access via JTAG and Serial Wire interfaces ­ Full JTAG boundary scan Industrial-range 48-pin RoHS-compliant LQFP package 1.2 Target Applications Factory automation and control Industrial control power devices Building and home automation Stepper motors Brushless DC motors AC induction motors May 4, 2007 25 Preliminary Architectural Overview 1.3 High-Level Block Diagram Figure 1-1. Stellaris® High-Level Block Diagram ARM Cortex-M3 (including Nested DCode bus Flash Vectored Interrupt Controller (NVIC) ICode bus System Control & Clocks LMI JTAG Test Access Port (TAP) Controller APB Bridge Memory Peripherals SRAM General-Purpose Timers General-Purpose Input/Outputs (GPIOs) System Peripherals Universal Asynchronous Receiver/ Transmitters (UARTs) Peripheral Bus Watchdog Timer Analog-toDigital Converter (ADC) Synchronous Serial Interface (SSI) Analog Comparators Serial Communications Peripherals Analog Peripherals Temperature Sensor Pulse Width Modulator (PWM) Motor Control Peripherals LM3S817 LM3S817 26 May 4, 2007 Preliminary LM3S817 LM3S817 Data Sheet 1.4 Functional Overview The following sections provide an overview of the features of the LM3S817 LM3S817 microcontroller. The chapter number in parenthesis indicates where that feature is discussed in detail. Ordering and support information can be found in "Ordering and Contact Information" on page 379. 1.4.1 ARM CortexTM-M3 1.4.1.1 Processor Core (Section 2 on page 33) All members of the Stellaris product family, including the LM3S817 LM3S817 microcontroller, are designed around an ARM CortexTM-M3 processor core. The ARM Cortex-M3 processor provides the core for a high-performance, low-cost platform that meets the needs of minimal memory implementation, reduced pin count, and low power consumption, while delivering outstanding computational performance and exceptional system response to interrupts. Section 2, "ARM Cortex-M3 Processor Core," on page 33 provides an overview of the ARM core; the core is detailed in the ARM® CortexTM-M3 Technical Reference Manual. 1.4.1.2 Nested Vectored Interrupt Controller (NVIC) The LM3S817 LM3S817 controller includes the ARM Nested Vectored Interrupt Controller (NVIC) on the ARM Cortex-M3 core. The NVIC and Cortex-M3 prioritize and handle all exceptions. All exceptions are handled in Handler Mode. The processor state is automatically stored to the stack on an exception, and automatically restored from the stack at the end of the Interrupt Service Routine (ISR). The vector is fetched in parallel to the state saving, which enables efficient interrupt entry. The processor supports tail-chaining, which enables back-to-back interrupts to be performed without the overhead of state saving and restoration. Software can set eight priority levels on 7 exceptions (system handlers) and 26 interrupts. Section 4, "Interrupts," on page 43 provides an overview of the NVIC controller and the interrupt map. Exceptions and interrupts are detailed in the ARM® CortexTM-M3 Technical Reference Manual. 1.4.2 Motor Control Peripherals To enhance motor control, the LM3S817 LM3S817 controller features Pulse Width Modulation (PWM) outputs. 1.4.2.1 PWM Pulse width modulation (PWM) is a powerful technique for digitally encoding analog signal levels. High-resolution counters are used to generate a square wave, and the duty cycle of the square wave is modulated to encode an analog signal. Typical applications include switching power supplies and motor control. On the LM3S817 LM3S817, PWM motion control functionality can be achieved through dedicated, flexible motion control hardware (the PWM pins) or through the motion control features of the general-purpose timers (using the CCP pins). PWM Pins (Section 15 on page 320) The LM3S817 LM3S817 PWM module consists of three PWM generator blocks and a control block. Each PWM generator block contains one timer (16-bit down or up/down counter), two comparators, a PWM signal generator, a dead-band generator, and an interrupt/ADC-trigger selector. The control block determines the polarity of the PWM signals, and which signals are passed through to the pins. May 4, 2007 27 Preliminary Architectural Overview Each PWM generator block produces two PWM signals that can either be independent signals or a single pair of complementary signals with dead-band delays inserted. The output of the PWM generation blocks are managed by the output control block before being passed to the device pins. CCP Pins ("16-Bit PWM Mode" on page 162) The General-Purpose Timer Module's CCP (Capture Compare PWM) pins are software programmable to support a simple PWM mode with a software-programmable output inversion of the PWM signal. 1.4.3 Analog Peripherals To handle analog signals, the LM3S817 LM3S817 controller offers an Analog-to-Digital Converter (ADC) and an analog comparator. 1.4.3.1 ADC (Section 11 on page 208) An analog-to-digital converter (ADC) is a peripheral that converts a continuous analog voltage to a discrete digital number. The Stellaris ADC module features 10-bit conversion resolution and supports six input channels, plus an internal temperature sensor. Four buffered sample sequences allow rapid sampling of up to six analog input sources without controller intervention. Each sample sequence provides flexible programming with fully configurable input source, trigger events, interrupt generation, and sequence priority. 1.4.3.2 Analog Comparator (Section 14 on page 309) An analog comparator is a peripheral that compares two analog voltages, and provides a logical output that signals the comparison result. The LM3S817 LM3S817 controller provides one independent integrated analog comparator that can be configured to drive an output or generate an interrupt or ADC event. A comparator can compare a test voltage against any one of these voltages: An individual external reference voltage A single external reference voltage A shared internal reference voltage The comparator can provide its output to a device pin, acting as a replacement for an analog comparator on the board, or it can be used to signal the application via interrupts or triggers to the ADC to cause it to start capturing a sample sequence. The interrupt generation and ADC triggering logic is separate. This means, for example, that an interrupt can be generated on a rising edge and the ADC triggered on a falling edge. 1.4.4 Serial Communications Peripherals The LM3S817 LM3S817 controller supports both asynchronous and synchronous serial communications with two fully programmable 16C550-type UARTs and SSI serial communications. 1.4.4.1 UART (Section 12 on page 238) A Universal Asynchronous Receiver/Transmitter (UART) is an integrated circuit used for RS-232C RS-232C serial communications, containing a transmitter (parallel-to-serial converter) and a receiver (serial-to-parallel converter), each clocked separately. The LM3S817 LM3S817 controller includes two fully programmable 16C550-type UARTs that support data transfer speeds up to 460.8 Kbps. (Although similar in functionality to a 16C550 16C550 UART, it is not register compatible.) 28 May 4, 2007 Preliminary LM3S817 LM3S817 Data Sheet Separate 16x8 transmit (TX) and 16x12 receive (RX) FIFOs reduce CPU interrupt service loading. The UART can generate individually masked interrupts from the RX, TX, modem status, and error conditions. The module provides a single combined interrupt when any of the interrupts are asserted and are unmasked. 1.4.4.2 SSI (Section 13 on page 274) Synchronous Serial Interface (SSI) is a four-wire bi-directional communications interface. The Stellaris SSI module provides the functionality for synchronous serial communications with peripheral devices, and can be configured to use the Freescale SPI, MICROWIRE, or TI synchronous serial interface frame formats. The size of the data frame is also configurable, and can be set between 4 and 16 bits, inclusive. The SSI module performs serial-to-parallel conversion on data received from a peripheral device, and parallel-to-serial conversion on data transmitted to a peripheral device. The TX and RX paths are buffered with internal FIFOs, allowing up to eight 16-bit values to be stored independently. The SSI module can be configured as either a master or slave device. As a slave device, the SSI module can also be configured to disable its output, which allows a master device to be coupled with multiple slave devices. The SSI module also includes a programmable bit rate clock divider and prescaler to generate the output serial clock derived from the SSI mo