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LM3S801 Microcontroller D ATA SHE E T DS -LM3S 801- 01 C opyr ight © 2006 Lumi nary Micro , Inc. Legal Disclaimers and

 

P RE L I M I NA R Y LM3S801 LM3S801 Microcontroller D ATA SHE E T DS -LM3S 801- 01 C opyr ight © 2006 Lumi nary Micro , Inc. Legal Disclaimers and Trademark Information INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH LUMINARY MICRO PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN LUMINARY MICRO'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, LUMINARY MICRO ASSUMES NO LIABILITY WHATSOEVER, AND LUMINARY MICRO DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF LUMINARY MICRO'S PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. LUMINARY MICRO'S PRODUCTS ARE NOT INTENDED FOR USE IN MEDICAL, LIFE SAVING, OR LIFE-SUSTAINING APPLICATIONS. Luminary Micro may make changes to specifications and product descriptions at any time, without notice. Contact your local Luminary Micro sales office or your distributor to obtain the latest specifications before placing your product order. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Luminary Micro reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. Copyright © 2006 Luminary Micro, Inc. All rights reserved. Stellaris and the Luminary Micro logo are trademarks of Luminary Micro, Inc. or its subsidiaries in the United States and other countries. ARM and Thumb are registered trademarks, and Cortex is a trademark of ARM Limited. Other names and brands may be claimed as the property of others. Luminary Micro, Inc. 2499 South Capital of Texas Hwy, Suite A-100 Austin, TX 78746 Main: +1-512-279-8800 Fax: +1-512-279-8879 http://www.luminarymicro.com 2 October 8, 2006 Preliminary LM3S801 LM3S801 Data Sheet Table of Contents Legal Disclaimers and Trademark Information. 2 Revision History . 18 About This Document. 19 Audience. 19 About This Manual. 19 Related Documents . 19 Documentation Conventions. 19 1. Architectural Overview . 22 1.1 1.2 1.3 1.4 1.4.1 1.4.2 1.4.3 1.4.4 1.4.5 1.4.6 1.4.7 1.4.8 1.5 Product Features . 22 Target Applications . 26 High-Level Block Diagram . 27 Functional Overview . 28 ARM CortexTM-M3 . 28 Motor Control Peripherals . 28 Analog Peripherals . 29 Serial Communications Peripherals. 29 System Peripherals. 30 Memory Peripherals. 31 Additional Features . 31 Hardware Details . 32 System Block Diagram . 33 2. ARM Cortex-M3 Processor Core. 34 2.1 2.2 2.2.1 2.2.2 2.2.3 2.2.4 2.2.5 2.2.6 Block Diagram . 35 Functional Description . 35 Serial Wire and JTAG Debug . 35 Embedded Trace Macrocell (ETM) . 36 Trace Port Interface Unit (TPIU) . 36 ROM Table . 36 Memory Protection Unit (MPU) . 36 Nested Vectored Interrupt Controller (NVIC) . 36 3. Memory Map . 37 4. Interrupts . 39 5. JTAG Interface . 42 5.1 5.2 5.2.1 5.2.2 5.2.3 5.2.4 5.3 5.4 5.4.1 5.4.2 Block Diagram . 43 Functional Description . 43 JTAG Interface Pins. 44 JTAG TAP Controller . 45 Shift Registers . 46 Operational Considerations . 46 Initialization and Configuration. 47 Register Descriptions. 48 Instruction Register (IR) . 48 Data Registers . 50 6. System Control. 52 6.1 6.1.1 Functional Description . 52 Device Identification. 52 October 8, 2006 3 Preliminary Table of Contents 6.1.2 6.1.3 6.1.4 6.1.5 6.2 6.3 6.4 Reset Control . 52 Power Control . 55 Clock Control . 55 System Control . 57 Initialization and Configuration. 58 Register Map . 58 Register Descriptions. 59 7. Internal Memory . 95 7.1 7.2 7.2.1 7.2.2 7.3 7.3.1 7.3.2 7.4 7.5 Block Diagram . 95 Functional Description . 95 SRAM Memory . 95 Flash Memory . 96 Initialization and Configuration. 97 Changing Flash Protection Bits . 97 Flash Programming . 98 Register Map . 98 Register Descriptions. 99 8. General-Purpose Input/Outputs (GPIOs) . 109 8.1 8.2 8.2.1 8.2.2 8.2.3 8.2.4 8.2.5 8.2.6 8.3 8.4 8.5 Block Diagram . 110 Functional Description . 110 Data Register Operation . 111 Data Direction . 112 Interrupt Operation. 112 Mode Control . 113 Pad Configuration . 113 Identification. 113 Initialization and Configuration. 113 Register Map . 115 Register Descriptions. 116 9. General-Purpose Timers . 147 9.1 9.2 9.2.1 9.2.2 9.2.3 9.3 9.3.1 9.3.2 9.3.3 9.3.4 9.3.5 9.3.6 9.4 9.5 Block Diagram . 148 Functional Description . 148 GPTM Reset Conditions . 148 32-Bit Timer Operating Modes. 148 16-Bit Timer Operating Modes. 150 Initialization and Configuration. 154 32-Bit One-Shot/Periodic Timer Mode . 154 32-Bit Real-Time Clock (RTC) Mode . 155 16-Bit One-Shot/Periodic Timer Mode . 155 16-Bit Input Edge Count Mode . 155 16-Bit Input Edge Timing Mode . 156 16-Bit PWM Mode. 156 Register Map . 157 Register Descriptions. 158 10. Watchdog Timer . 179 10.1 10.2 10.3 10.4 Block Diagram . 179 Functional Description . 180 Initialization and Configuration. 180 Register Map . 180 4 October 8, 2006 Preliminary LM3S801 LM3S801 Data Sheet 10.5 Register Descriptions. 181 11. Universal Asynchronous Receivers/Transmitters (UARTs). 202 11.1 11.2 11.2.1 11.2.2 11.2.3 11.2.4 11.2.5 11.2.6 11.3 11.4 11.5 Block Diagram . 203 Functional Description . 203 Transmit/Receive Logic . 203 Baud-Rate Generation . 204 Data Transmission . 205 FIFO Operation . 205 Interrupts. 205 Loopback Operation . 206 Initialization and Configuration. 206 Register Map . 207 Register Descriptions. 208 12. Synchronous Serial Interface (SSI) . 238 12.1 12.2 12.2.1 12.2.2 12.2.3 12.2.4 12.3 12.4 12.5 Block Diagram . 238 Functional Description . 239 Bit Rate Generation . 239 FIFO Operation . 239 Interrupts. 239 Frame Formats . 240 Initialization and Configuration. 247 Register Map . 248 Register Descriptions. 249 13. Inter-Integrated Circuit (I2C) Interface . 273 13.1 13.2 13.2.1 13.2.2 13.3 13.4 13.5 13.6 Block Diagram . 273 Functional Description . 273 I2C Bus Functional Overview . 274 Available Speed Modes . 281 Initialization and Configuration. 282 Register Map . 283 Register Descriptions (I2C Master). 283 Register Descriptions (I2C Slave). 297 14. Analog Comparators. 305 14.1 14.2 14.2.1 14.3 14.4 14.5 Block Diagram . 305 Functional Description . 306 Internal Reference Programming. 307 Initialization and Configuration. 308 Register Map . 309 Register Descriptions. 309 15. Pulse Width Modulator (PWM) . 317 15.1 15.2 15.2.1 15.2.2 15.2.3 15.2.4 15.2.5 15.2.6 15.2.7 Block Diagram . 317 Functional Description . 317 PWM Timer . 317 PWM Comparators . 318 PWM Signal Generator . 319 Dead-Band Generator . 320 Interrupt Selector . 320 Synchronization Methods . 320 Fault Conditions . 321 October 8, 2006 5 Preliminary Table of Contents 15.2.8 15.3 15.4 15.5 Output Control Block. 321 Initialization and Configuration. 321 Register Map . 322 Register Descriptions. 324 16. Quadrature Encoder Interface (QEI). 349 16.1 16.2 16.3 16.4 16.5 Block Diagram . 349 Functional Description . 349 Initialization and Configuration. 352 Register Map . 352 Register Descriptions. 352 17. Pin Diagram . 365 18. Signal Tables . 366 19. Operating Characteristics . 377 20. Electrical Characteristics . 378 20.1 20.1.1 20.1.2 20.1.3 20.1.4 20.1.5 20.2 20.2.1 20.2.2 20.2.3 20.2.4 20.2.5 20.2.6 20.2.7 20.2.8 DC Characteristics . 378 Maximum Ratings . 378 Recommended DC Operating Conditions . 378 On-Chip Low Drop-Out (LDO) Regulator Characteristics . 379 Power Specifications . 380 Flash Memory Characteristics . 380 AC Characteristics . 381 Load Conditions . 381 Clocks . 381 Analog Comparator. 382 I2C. 382 Synchronous Serial Interface (SSI) . 384 JTAG and Boundary Scan . 386 General-Purpose I/O. 388 Reset . 388 21. Package Information. 391 Appendix A. Serial Flash Loader . 392 A.1 A.1.1 A.1.2 A.2 A.2.1 A.2.2 A.2.3 A.3 A.3.1 A.3.2 A.3.3 A.3.4 A.3.5 A.3.6 Interfaces . 392 UART . 392 SSI . 392 Packet Handling. 392 Packet Format . 393 Sending Packets . 393 Receiving Packets . 393 Commands . 393 COMMAND_PING (0x20) . 394 COMMAND_GET_STATUS (0x23) . 394 COMMAND_DOWNLOAD (0x21). 394 COMMAND_SEND_DATA (0x24) . 394 COMMAND_RUN (0x22) . 395 COMMAND_RESET (0x25). 395 6 October 8, 2006 Preliminary LM3S801 LM3S801 Data Sheet Ordering and Contact Information . 396 Ordering Information . 396 Development Kit . 396 Company Information . 396 Support Information . 397 October 8, 2006 7 Preliminary List of Figures List of Figures Figure 1-1. Figure 1-2. Figure 2-1. Figure 2-2. Figure 5-1. Figure 5-2. Figure 5-3. Figure 5-4. Figure 5-5. Figure 6-1. Figure 6-2. Figure 7-1. Figure 8-1. Figure 8-2. Figure 8-3. Figure 8-4. Figure 9-1. Figure 9-2. Figure 9-3. Figure 9-4. Figure 10-1. Figure 11-1. Figure 11-2. Figure 12-1. Figure 12-2. Figure 12-3. Figure 12-4. Figure 12-5. Figure 12-6. Figure 12-7. Figure 12-8. Figure 12-9. Figure 12-10. Figure 12-11. Figure 12-12. Figure 13-1. Figure 13-2. Figure 13-3. Figure 13-4. Figure 13-5. Figure 13-6. Figure 13-7. Figure 13-8. Figure 13-9. Figure 13-10. Figure 13-11. Stellaris High-Level Block Diagram . 27 LM3S801 LM3S801 Controller System-Level Block Diagram . 33 CPU Block Diagram . 35 TPIU Block Diagram . 36 JTAG Module Block Diagram . 43 Test Access Port State Machine . 46 IDCODE Register Format. 50 BYPASS Register Format . 50 Boundary Scan Register Format . 51 External Circuitry to Extend Reset. 53 Main Clock Tree . 56 Flash Block Diagram . 95 GPIO Module Block Diagram . 110 GPIO Port Block Diagram. 111 GPIODATA Write Example. 112 GPIODATA Read Example . 112 GPTM Module Block Diagram . 148 16-Bit Input Edge Count Mode Example . 152 16-Bit Input Edge Time Mode Example. 153 16-Bit PWM Mode Example . 154 WDT Module Block Diagram . 179 UART Module Block Diagram. 203 UART Character Frame. 204 SSI Module Block Diagram. 238 TI Synchronous Serial Frame Format (Single Transfer). 240 TI Synchronous Serial Frame Format (Continuous Transfer) . 241 Freescale SPI Format (Single Transfer) with SPO=0 and SPH=0 . 242 Freescale SPI Format (Continuous Transfer) with SPO=0 and SPH=0 . 242 Freescale SPI Frame Format with SPO=0 and SPH=1. 243 Freescale SPI Frame Format (Single Transfer) with SPO=1 and SPH=0. 243 Freescale SPI Frame Format (Continuous Transfer) with SPO=1 and SPH=0. 244 Freescale SPI Frame Format with SPO=1 and SPH=1. 244 MICROWIRE Frame Format (Single Frame). 245 MICROWIRE Frame Format (Continuous Transfer) . 246 MICROWIRE Frame Format, SSIFss Input Setup and Hold Requirements. 247 I2C Block Diagram . 273 I2C Bus Configuration. 274 Data Validity During Bit Transfer on the I2C Bus. 274 START and STOP Conditions . 274 Complete Data Transfer with a 7-Bit Address . 275 R/S Bit in First Byte . 276 Master Single SEND. 276 Master Single RECEIVE. 277 Master Burst SEND . 278 Master Burst RECEIVE . 279 Master Burst RECEIVE after Burst SEND. 280 8 October 8, 2006 Preliminary LM3S801 LM3S801 Data Sheet Figure 13-12. Figure 13-13. Figure 14-1. Figure 14-2. Figure 14-3. Figure 15-1. Figure 15-2. Figure 15-3. Figure 15-4. Figure 15-5. Figure 16-1. Figure 16-2. Figure 17-1. Figure 20-1. Figure 20-2. Figure 20-3. Figure 20-4. Figure 20-5. Figure 20-6. Figure 20-7. Figure 20-8. Figure 20-9. Figure 20-10. Figure 20-11. Figure 20-12. Figure 20-13. Figure 20-14. Figure 21-1. Master Burst SEND after Burst RECEIVE. 280 Slave Command Sequence. 281 Analog Comparator Module Block Diagram . 305 Structure of Comparator Unit. 306 Comparator Internal Reference Structure . 307 PWM Module Block Diagram. 317 PWM Count-Down Mode. 318 PWM Count-Up/Down Mode . 319 PWM Generation Example In Count-Up/Down Mode . 319 PWM Dead-Band Generator . 320 QEI Block Diagram . 349 Quadrature Encoder and Velocity Predivider Operation . 350 Pin Connection Diagram. 365 Load Conditions. 381 I2C Timing. 383 SSI Timing for TI Frame Format (FRF=01), Single Transfer Timing Measurement . 384 SSI Timing for MICROWIRE Frame Format (FRF=10), Single Transfer. 385 SSI Timing for SPI Frame Format (FRF=00), with SPH=1. 385 JTAG Test Clock Input Timing. 387 JTAG Test Access Port (TAP) Timing . 387 JTAG TRST Timing . 387 External Reset Timing (RST). 389 Power-On Reset Timing . 389 Brown-Out Reset Timing . 389 Software Reset Timing . 389 Watchdog Reset Timing . 390 LDO Reset Timing . 390 48-Pin LQFP Package. 391 October 8, 2006 9 Preliminary List of Tables List of Tables Table 0-1. Table 3-1. Table 4-1. Table 4-2. Table 5-1. Table 5-2. Table 6-1. Table 6-2. Table 6-3. Table 6-4. Table 7-1. Table 7-2. Table 8-1. Table 8-2. Table 8-3. Table 9-1. Table 9-2. Table 10-1. Table 11-1. Table 12-1. Table 13-1. Table 13-2. Table 13-3. Table 14-1. Table 14-4. Table 14-2. Table 14-3. Table 14-5. Table 15-1. Table 15-2. Table 16-1. Table 18-1. Table 18-2. Table 18-3. Table 18-4. Table 19-1. Table 19-2. Table 20-1. Table 20-2. Table 20-3. Table 20-4. Table 20-5. Table 20-6. Table 20-7. Table 20-8. Table 20-9. Table 20-10. Table 20-11. Documentation Conventions . 19 Memory Map. 37 Exception Types . 39 Interrupts . 40 JTAG Port Pins Reset State . 44 JTAG Instruction Register Commands . 48 System Control Register Map. 58 VADJ to VOUT . 72 PLL Mode Control. 84 Default Crystal Field Values and PLL Programming . 84 Flash Protection Policy Combinations . 97 Flash Register Map . 98 GPIO Pad Configuration Examples . 113 GPIO Interrupt Configuration Example . 114 GPIO Register Map . 115 16-Bit Timer With Prescaler Configurations . 151 GPTM Register Map. 157 WDT Register Map . 180 UART Register Map . 207 SSI Register Map . 248 Examples of I2C Master Timer Period versus Speed Mode . 282 I2C Register Map . 283 Write Field Decoding for I2CMCS[3:0] Field . 287 Comparator 0 Operating Modes . 306 Internal Reference Voltage and ACREFCTL Field Values . 307 Comparator 1 Operating Modes . 307 Comparator 2 Operating Modes . 307 Analog Comparator Register Map . 309 PWM Register Map . 322 PWM Generator Action Encodings. 344 QEI Register Map . 352 Signals by Pin Number . 366 Signals by Signal Name . 369 Signals by Function, Except for GPIO . 372 GPIO Pins and Alternate Functions. 374 Temperature Characteristics . 377 Thermal Characteristics. 377 Maximum Ratings. 378 Recommended DC Operating Conditions . 378 LDO Regulator Characteristics. 379 Power Specifications . 380 Flash Memory Characteristics . 380 Phase Locked Loop (PLL) Characteristics . 381 Clock Characteristics. 381 Analog Comparator Characteristics. 382 Analog Comparator Voltage Reference Characteristics. 382 I2C Characteristics. 382 SSI Characteristics . 384 10 October 8, 2006 Preliminary LM3S801 LM3S801 Data Sheet Table 20-12. JTAG Characteristics. 386 Table 20-13. GPIO Characteristics. 388 Table 20-14. Reset Characteristics . 388 October 8, 2006 11 Preliminary List of Registers List of Registers System Control . 52 Register 1: Register 2: Register 3: Register 4: Register 5: Register 6: Register 7: Register 8: Register 9: Register 10: Register 11: Register 12: Register 13: Register 14: Register 15: Register 16: Register 17: Register 18: Register 19: Register 20: Register 21: Register 22: Register 23: Register 24: Register 25: Register 26: Register 27: Register 28: Register 29: Register 30: Device Identification 0 (DID0), offset 0x000 . 60 Device Identification 1 (DID1), offset 0x004 . 61 Device Capabilities 0 (DC0), offset 0x008. 63 Device Capabilities 1 (DC1), offset 0x010. 64 Device Capabilities 2 (DC2), offset 0x014. 66 Device Capabilities 3 (DC3), offset 0x018. 68 Device Capabilities 4 (DC4), offset 0x01C . 70 Power-On and Brown-Out Reset Control (PBORCTL), offset 0x030 . 71 LDO Power Control (LDOPCTL), offset 0x034. 72 Software Reset Control 0 (SRCR0), offset 0x040 . 73 Software Reset Control 1 (SRCR1), offset 0x044 . 74 Software Reset Control 2 (SRCR2), offset 0x048 . 75 Raw Interrupt Status (RIS), offset 0x050. 76 Interrupt Mask Control (IMC), offset 0x054 . 77 Masked Interrupt Status and Clear (MISC), offset 0x058. 79 Reset Cause (RESC), offset 0x05C . 80 Run-Mode Clock Configuration (RCC), offset 0x060. 81 XTAL to PLL Translation (PLLCFG), offset 0x064 . 86 Run-Mode Clock Gating Control 0 (RCGC0), offset 0x100 . 87 Sleep-Mode Clock Gating Control 0 (SCGC0), offset 0x110. 87 Deep-Sleep-Mode Clock Gating Control 0 (DCGC0), offset 0x120. 87 Run-Mode Clock Gating Control 1 (RCGC1), offset 0x104 . 89 Sleep-Mode Clock Gating Control 1 (SCGC1), offset 0x114. 89 Deep-Sleep-Mode Clock Gating Control 1 (DCGC1), offset 0x124. 89 Run-Mode Clock Gating Control 2 (RCGC2), offset 0x108 . 91 Sleep-Mode Clock Gating Control 2 (SCGC2), offset 0x118. 91 Deep-Sleep-Mode Clock Gating Control 2 (DCGC2), offset 0x128. 91 Deep-Sleep Clock Configuration (DSLPCLKCFG), offset 0x144 . 92 Clock Verification Clear (CLKVCLR), offset 0x150. 93 Allow Unregulated LDO to Reset the Part (LDOARST), offset 0x160 . 94 Internal Memory . 95 Register 1: Register 2: Register 3: Register 4: Register 5: Register 6: Register 7: Register 8: Register 9: Flash Memory Protection Read Enable (FMPRE), offset 0x130 . 100 Flash Memory Protection Program Enable (FMPPE), offset 0x134 . 100 USec Reload (USECRL), offset 0x140. 101 Flash Memory Address (FMA), offset 0x000 . 102 Flash Memory Data (FMD), offset 0x004 . 103 Flash Memory Control (FMC), offset 0x008 . 104 Flash Controller Raw Interrupt Status (FCRIS), offset 0x00C . 106 Flash Controller Interrupt Mask (FCIM), offset 0x010 . 107 Flash Controller Masked Interrupt Status and Clear (FCMISC), offset 0x014. 108 General-Purpose Input/Outputs (GPIOs) . 109 Register 1: Register 2: Register 3: Register 4: GPIO Data (GPIODATA), offset 0x000 . 117 GPIO Direction (GPIODIR), offset 0x400 . 118 GPIO Interrupt Sense (GPIOIS), offset 0x404. 119 GPIO Interrupt Both Edges (GPIOIBE), offset 0x408. 120 12 October 8, 2006 Preliminary LM3S801 LM3S801 Data Sheet Register 5: Register 6: Register 7: Register 8: Register 9: Register 10: Register 11: Register 12: Register 13: Register 14: Register 15: Register 16: Register 17: Register 18: Register 19: Register 20: Register 21: Register 22: Register 23: Register 24: Register 25: Register 26: Register 27: Register 28: Register 29: Register 30: GPIO Interrupt Event (GPIOIEV), offset 0x40C. 121 GPIO Interrupt Mask (GPIOIM), offset 0x410. 122 GPIO Raw Interrupt Status (GPIORIS), offset 0x414. 123 GPIO Masked Interrupt Status (GPIOMIS), offset 0x418 . 124 GPIO Interrupt Clear (GPIOICR), offset 0x41C. 125 GPIO Alternate Function Select (GPIOAFSEL), offset 0x420 . 126 GPIO 2-mA Drive Select (GPIODR2R), offset 0x500. 127 GPIO 4-mA Drive Select (GPIODR4R), offset 0x504. 128 GPIO 8-mA Drive Select (GPIODR8R), offset 0x508. 129 GPIO Open Drain Select (GPIOODR), offset 0x50C. 130 GPIO Pull-Up Select (GPIOPUR), offset 0x510 . 131 GPIO Pull-Down Select (GPIOPDR), offset 0x514. 132 GPIO Slew Rate Control Select (GPIOSLR), offset 0x518. 133 GPIO Digital Input Enable (GPIODEN), offset 0x51C . 134 GPIO Peripheral Identification 4 (GPIOPeriphID4), offset 0xFD0 . 135 GPIO Peripheral Identification 5 (GPIOPeriphID5), offset 0xFD4 . 136 GPIO Peripheral Identification 6 (GPIOPeriphID6), offset 0xFD8 . 137 GPIO Peripheral Identification 7 (GPIOPeriphID7), offset 0xFDC. 138 GPIO Peripheral Identification 0 (GPIOPeriphID0), offset 0xFE0 . 139 GPIO Peripheral Identification 1(GPIOPeriphID1), offset 0xFE4 . 140 GPIO Peripheral Identification 2 (GPIOPeriphID2), offset 0xFE8 . 141 GPIO Peripheral Identification 3 (GPIOPeriphID3), offset 0xFEC. 142 GPIO PrimeCell Identification 0 (GPIOPCellID0), offset 0xFF0 . 143 GPIO PrimeCell Identification 1 (GPIOPCellID1), offset 0xFF4 . 144 GPIO PrimeCell Identification 2 (GPIOPCellID2), offset 0xFF8 . 145 GPIO PrimeCell Identification 3 (GPIOPCellID3), offset 0xFFC. 146 General-Purpose Timers . 147 Register 1: Register 2: Register 3: Register 4: Register 5: Register 6: Register 7: Register 8: Register 9: Register 10: Register 11: Register 12: Register 13: Register 14: Register 15: Register 16: Register 17: Register 18: GPTM Configuration (GPTMCFG), offset 0x000. 159 GPTM TimerA Mode (GPTMTAMR), offset 0x004 . 160 GPTM TimerB Mode (GPTMTBMR), offset 0x008 . 161 GPTM Control (GPTMCTL), offset 0x00C. 162 GPTM Interrupt Mask (GPTMIMR), offset 0x018 . 164 GPTM Raw Interrupt Status (GPTMRIS), offset 0x01C . 166 GPTM Masked Interrupt Status (GPTMMIS), offset 0x020 . 167 GPTM Interrupt Clear (GPTMICR), offset 0x024. 168 GPTM TimerA Interval Load (GPTMTAILR), offset 0x028 . 169 GPTM TimerB Interval Load (GPTMTBILR), offset 0x02C. 170 GPTM TimerA Match (GPTMTAMATCHR), offset 0x030 . 171 GPTM TimerB Match (GPTMTBMATCHR), offset 0x034 . 172 GPTM TimerA Prescale (GPTMTAPR), offset 0x038. 173 GPTM TimerB Prescale (GPTMTBPR), offset 0x03C . 174 GPTM TimerA Prescale Match (GPTMTAPMR), offset 0x040. 175 GPTM TimerB Prescale Match (GPTMTBPMR), offset 0x044. 176 GPTM TimerA (GPTMTAR), offset 0x048 . 177 GPTM TimerB (GPTMTBR), offset 0x04C . 178 Watchdog Timer. 179 Register 1: Register 2: Watchdog Load (WDTLOAD), offset 0x000 . 182 Watchdog Value (WDTVALUE), offset 0x004 . 183 October 8, 2006 13 Preliminary List of Registers Register 3: Register 4: Register 5: Register 6: Register 7: Register 8: Register 9: Register 10: Register 11: Register 12: Register 13: Register 14: Register 15: Register 16: Register 17: Register 18: Register 19: Register 20: Watchdog Control (WDTCTL), offset 0x008. 184 Watchdog Interrupt Clear (WDTICR), offset 0x00C . 185 Watchdog Raw Interrupt Status (WDTRIS), offset 0x010 . 186 Watchdog Masked Interrupt Status (WDTMIS), offset 0x014. 187 Watchdog Lock (WDTLOCK), offset 0xC00 . 188 Watchdog Test (WDTTEST), offset 0x418 . 189 Watchdog Peripheral Identification 4 (WDTPeriphID4), offset 0xFD0. 190 Watchdog Peripheral Identification 5 (WDTPeriphID5), offset 0xFD4. 191 Watchdog Peripheral Identification 6 (WDTPeriphID6), offset 0xFD8. 192 Watchdog Peripheral Identification 7 (WDTPeriphID7), offset 0xFDC . 193 Watchdog Peripheral Identification 0 (WDTPeriphID0), offset 0xFE0 . 194 Watchdog Peripheral Identification 1 (WDTPeriphID1), offset 0xFE4 . 195 Watchdog Peripheral Identification 2 (WDTPeriphID2), offset 0xFE8 . 196 Watchdog Peripheral Identification 3 (WDTPeriphID3), offset 0xFEC . 197 Watchdog PrimeCell Identification 0 (WDTPCellID0), offset 0xFF0. 198 Watchdog PrimeCell Identification 1 (WDTPCellID1), offset 0xFF4. 199 Watchdog PrimeCell Identification 2 (WDTPCellID2), offset 0xFF8. 200 Watchdog PrimeCell Identification 3 (WDTPCellID3 ), offset 0xFFC . 201 Universal Asynchronous Receivers/Transmitters (UARTs) . 202 Register 1: Register 2: Register 3: Register 4: Register 5: Register 6: Register 7: Register 8: Register 9: Register 10: Register 11: Register 12: Register 13: Register 14: Register 15: Register 16: Register 17: Register 18: Register 19: Register 20: Register 21: Register 22: Register 23: Register 24: UART Data (UARTDR), offset 0x000 . 209 UART Receive Status/Error Clear (UARTRSR/UARTECR), offset 0x004 . 211 UART Flag (UARTFR), offset 0x018 . 213 UART Integer Baud-Rate Divisor (UARTIBRD), offset 0x024 . 215 UART Fractional Baud-Rate Divisor (UARTFBRD), offset 0x028 . 216 UART Line Control (UARTLCRH), offset 0x02C . 217 UART Control (UARTCTL), offset 0x030. 219 UART Interrupt FIFO Level Select (UARTIFLS), offset 0x034 . 220 UART Interrupt Mask (UARTIM), offset 0x038 . 221 UART Raw Interrupt Status (UARTRIS), offset 0x03C. 223 UART Masked Interrupt Status (UARTMIS), offset 0x040 . 224 UART Interrupt Clear (UARTICR), offset 0x044. 225 UART Peripheral Identification 4 (UARTPeriphID4), offset 0xFD0. 226 UART Peripheral Identification 5 (UARTPeriphID5), offset 0xFD4. 227 UART Peripheral Identification 6 (UARTPeriphID6), offset 0xFD8. 228 UART Peripheral Identification 7 (UARTPeriphID7), offset 0xFDC . 229 UART Peripheral Identification 0 (UARTPeriphID0), offset 0xFE0. 230 UART Peripheral Identification 1 (UARTPeriphID1), offset 0xFE4. 231 UART Peripheral Identification 2 (UARTPeriphID2), offset 0xFE8. 232 UART Peripheral Identification 3 (UARTPeriphID3), offset 0xFEC . 233 UART PrimeCell Identification 0 (UARTPCellID0), offset 0xFF0. 234 UART PrimeCell Identification 1 (UARTPCellID1), offset 0xFF4. 235 UART PrimeCell Identification 2 (UARTPCellID2), offset 0xFF8. 236 UART PrimeCell Identification 3 (UARTPCellID3), offset 0xFFC . 237 Synchronous Serial Interface (SSI) . 238 Register 1: Register 2: Register 3: Register 4: SSI Control 0 (SSICR0), offset 0x000 . 250 SSI Control 1 (SSICR1), offset 0x004 . 252 SSI Data (SSIDR), offset 0x008 . 254 SSI Status (SSISR), offset 0x00C . 255 14 October 8, 2006 Preliminary LM3S801 LM3S801 Data Sheet Register 5: Register 6: Register 7: Register 8: Register 9: Register 10: Register 11: Register 12: Register 13: Register 14: Register 15: Register 16: Register 17: Register 18: Register 19: Register 20: Register 21: SSI Clock Prescale (SSICPSR), offset 0x010 . 256 SSI Interrupt Mask (SSIIM), offset 0x014 . 257 SSI Raw Interrupt Status (SSIRIS), offset 0x018 . 258 SSI Masked Interrupt Status (SSIMIS), offset 0x01C. 259 SSI Interrupt Clear (SSIICR), offset 0x020. 260 SSI Peripheral Identification 4 (SSIPeriphID4), offset 0xFD0. 261 SSI Peripheral Identification 5 (SSIPeriphID5), offset 0xFD4. 262 SSI Peripheral Identification 6 (SSIPeriphID6), offset 0xFD8. 263 SSI Peripheral Identification 7 (SSIPeriphID7), offset 0xFDC . 264 SSI Peripheral Identification 0 (SSIPeriphID0), offset 0xFE0. 265 SSI Peripheral Identification 1 (SSIPeriphID1), offset 0xFE4. 266 SSI Peripheral Identification 2 (SSIPeriphID2), offset 0xFE8. 267 SSI Peripheral Identification 3 (SSIPeriphID3), offset 0xFEC . 268 SSI PrimeCell Identification 0 (SSIPCellID0), offset 0xFF0. 269 SSI PrimeCell Identification 1 (SSIPCellID1), offset 0xFF4. 270 SSI PrimeCell Identification 2 (SSIPCellID2), offset 0xFF8. 271 SSI PrimeCell Identification 3 (SSIPCellID3), offset 0xFFC . 272 Inter-Integrated Circuit (I2C) Interface . 273 Register 1: Register 2: Register 3: Register 4: Register 5: Register 6: Register 7: Register 8: Register 9: Register 10: Register 11: Register 12: Register 13: Register 14: Register 15: Register 16: I2C Master Slave Address (I2CMSA), offset 0x000 . 284 I2C Master Control/Status (I2CMCS), offset 0x004. 285 I2C Master Data (I2CMDR), offset 0x008. 290 I2C Master Timer Period (I2CMTPR), offset 0x00C . 291 I2C Master Interrupt Mask (I2CMIMR), offset 0x010 . 292 I2C Master Raw Interrupt Status (I2CMRIS), offset 0x014 . 293 I2C Master Masked Interrupt Status (I2CMMIS), offset 0x018 . 294 I2C Master Interrupt Clear (I2CMICR), offset 0x01C . 295 I2C Master Configuration (I2CMCR), offset 0x020 . 296 I2C Slave Own Address (I2CSOAR), offset 0x000 . 297 I2C Slave Control/Status (I2CSCSR), offset 0x004 . 298 I2C Slave Data (I2CSDR), offset 0x008. 300 I2C Slave Interrupt Mask (I2CSIMR), offset 0x00C . 301 I2C Slave Raw Interrupt Status (I2CSRIS), offset 0x010. 302 I2C Slave Masked Interrupt Status (I2CSMIS), offset 0x014. 303 I2C Slave Interrupt Clear (I2CSICR), offset 0x018 . 304 Analog Comparators . 305 Register 1: Register 2: Register 3: Register 4: Register 5: Register 6: Register 7: Register 8: Register 9: Register 10: Analog Comparator Masked Interrupt Status (ACMIS), offset 0x00. 310 Analog Comparator Raw Interrupt Status (ACRIS), offset 0x04. 311 Analog Comparator Interrupt Enable (ACINTEN), offset 0x08 . 312 Analog Comparator Reference Voltage Control (ACREFCTL), offset 0x10 . 313 Analog Comparator Status 0 (ACSTAT0), offset 0x20 . 314 Analog Comparator Status 1 (ACSTAT1), offset 0x40 . 314 Analog Comparator Status 2 (ACSTAT2), offset 0x60 . 314 Analog Comparator Control 0 (ACCTL0), offset 0x24 . 315 Analog Comparator Control 1 (ACCTL1), offset 0x44 . 315 Analog Comparator Control 2 (ACCTL2), offset 0x64 . 315 Pulse Width Modulator (PWM). 317 Register 1: Register 2: PWM Master Control (PWMCTL), offset 0x000. 325 PWM Time Base Sync (PWMSYNC), offset 0x004. 326 October 8, 2006 15 Preliminary List of Registers Register 3: Register 4: Register 5: Register 6: Register 7: Register 8: Register 9: Register 10: Register 11: Register 12: Register 13: Register 14: Register 15: Register 16: Register 17: Register 18: Register 19: Register 20: Register 21: Register 22: Register 23: Register 24: Register 25: Register 26: Register 27: Register 28: Register 29: Register 30: Register 31: Register 32: Register 33: Register 34: Register 35: Register 36: Register 37: Register 38: Register 39: Register 40: Register 41: Register 42: Register 43: Register 44: Register 45: Register 46: Register 47: Register 48: PWM Output Enable (PWMENABLE), offset 0x008. 327 PWM Output Inversion (PWMINVERT), offset 0x00C. 328 PWM Output Fault (PWMFAULT), offset 0x010. 329 PWM Interrupt Enable (PWMINTEN), offset 0x014. 330 PWM Raw Interrupt Status (PWMRIS), offset 0x018 . 331 PWM Interrupt Status and Clear (PWMISC), offset 0x01C . 332 PWM Status (PWMSTATUS), offset 0x020. 333 PWM0 Control (PWM0CTL), offset 0x040. 334 PWM1 Control (PWM1CTL), offset 0x080. 334 PWM2 Control (PWM2CTL), offset 0x0C0 . 334 PWM0 Interrupt Enable (PWM0INTEN), offset 0x044. 336 PWM1 Interrupt Enable (PWM1INTEN), offset 0x084. 336 PWM2 Interrupt Enable (PWM2INTEN), offset 0x0C4 . 336 PWM0 Raw Interrupt Status (PWM0RIS), offset 0x048 . 337 PWM1 Raw Interrupt Status (PWM1RIS), offset 0x088 . 337 PWM2 Raw Interrupt Status (PWM2RIS), offset 0x0C8. 337 PWM0 Interrupt Status and Clear (PWM0ISC), offset 0x04C . 338 PWM1 Interrupt Status and Clear (PWM1ISC), offset 0x08C . 338 PWM2 Interrupt Status and Clear (PWM2ISC), offset 0x0CC. 338 PWM0 Load (PWM0LOAD), offset 0x050 . 339 PWM1 Load (PWM1LOAD), offset 0x090 . 339 PWM2 Load (PWM2LOAD), offset 0x0D0. 339 PWM0 Counter (PWM0COUNT), offset 0x054 . 340 PWM1 Counter (PWM1COUNT), offset 0x094 . 340 PWM2 Counter (PWM2COUNT), offset 0x0D4. 340 PWM0 Compare A (PWM0CMPA), offset 0x058 . 341 PWM1 Compare A (PWM1CMPA), offset 0x098 . 341 PWM2 Compare A (PWM2CMPA), offset 0x0D8. 341 PWM0 Compare B (PWM0CMPB), offset 0x05C. 342 PWM1 Compare B (PWM1CMPB), offset 0x09C. 342 PWM2 Compare B (PWM2CMPB), offset 0x0DC . 342 PWM0 Generator A Control (PWM0GENA), offset 0x060. 343 PWM1 Generator A Control (PWM1GENA), offset 0x0A0 . 343 PWM2 Generator A Control (PWM2GENA), offset 0x0E0 . 343 PWM0 Generator B Control (PWM0GENB), offset 0x064. 345 PWM1 Generator B Control (PWM1GENB), offset 0x0A4 . 345 PWM2 Generator B Control (PWM2GENB), offset 0x0E4 . 345 PWM0 Dead-Band Control (PWM0DBCTL), offset 0x068 . 346 PWM1 Dead-Band Control (PWM1DBCTL), offset 0x0A8 . 346 PWM2 Dead-Band Control (PWM2DBCTL), offset 0x0E8 . 346 PWM0 Dead-Band Rising-Edge Delay (PWM0DBRISE), offset 0x06C . 347 PWM1 Dead-Band Rising-Edge Delay (PWM1DBRISE), offset 0x0AC. 347 PWM2 Dead-Band Rising-Edge Delay (PWM2DBRISE), offset 0x0EC. 347 PWM0 Dead-Band Falling-Edge-Delay (PWM0DBFALL), offset 0x070. 348 PWM1 Dead-Band Falling-Edge-Delay (PWM1DBFALL), offset 0x0B0 . 348 PWM2 Dead-Band Falling-Edge-Delay (PWM2DBFALL), offset 0x0F0 . 348 Quadrature Encoder Interface (QEI). 349 Register 1: Register 2: Register 3: QEI Control (QEICTL), offset 0x000. 353 QEI Status (QEISTAT), offset 0x004. 355 QEI Position (QEIPOS), offset 0x008. 356 16 October 8, 2006 Preliminary LM3S801 LM3S801 Data Sheet Register 4: Register 5: Register 6: Register 7: Register 8: Register 9: Register 10: Register 11: QEI Maximum Position (QEIMAXPOS), offset 0x00C. 357 QEI Timer Load (QEILOAD), offset 0x010 . 358 QEI Timer (QEITIME), offset 0x014 . 359 QEI Velocity Counter (QEICOUNT), offset 0x018 . 360 QEI Velocity (QEISPEED), offset 0x01C. 361 QEI Interrupt Enable (QEIINTEN), offset 0x020. 362 QEI Raw Interrupt Status (QEIRIS), offset 0x024 . 363 QEI Interrupt Status and Clear (QEIISC), offset 0x028 . 364 October 8, 2006 17 Preliminary Revision History Revision History This table provides a summary of the document revisions. Date Revision Description July 2006 00 Initial public release of LM3S328 LM3S328, LM3S601 LM3S601, LM3S610 LM3S610, LM3S611 LM3S611, LM3S612 LM3S612, LM3S613 LM3S613, LM3S615 LM3S615, LM3S628 LM3S628, LM3S801 LM3S801, LM3S811 LM3S811, LM3S812 LM3S812, LM3S815 LM3S815, and LM3S828 LM3S828 data sheets. October 2006 01 Second release of LM3S328 LM3S328, LM3S601 LM3S601, LM3S610 LM3S610, LM3S611 LM3S611, LM3S613 LM3S613, LM3S615 LM3S615, LM3S628 LM3S628, LM3S801 LM3S801, LM3S812 LM3S812, LM3S815 LM3S815, and LM3S828 LM3S828 data sheets. Includes the following changes: · Updated the clocking examples in the I2C chapter. · Added Serial Flash Loader usage information. · Added "5-V-tolerant" description for GPIOs to feature list, GPIO chapter, and Electrical chapter. · Added maximum values for 20 MHz and 25 MHz parts to Table 9-1, "16-Bit Timer With Prescaler Configurations" in the Timers chapter. · Made the following changes in the System Control chapter: - Updated field descriptions in the Run-Mode Clock Configuration (RCC) register . - Updated the internal oscillator clock speed. - Added the Deep-Sleep Clock Configuration (DSLPCFG) register. - Added bus fault information to the clock gating registers. 18 October 8, 2006 Preliminary LM3S801 LM3S801 Data Sheet About This Document This data sheet provides reference information for the LM3S801 LM3S801 microcontroller, describing the functional blocks of the system-on-chip (SoC) device designed around the ARM® CortexTM-M3 core. Audience This manual is intended for system software developers, hardware designers, and application developers. About This Manual This document is organized into sections that correspond to each major feature. Related Documents The following documents are referenced by the data sheet, and available on the documentation CD or from the Luminary Micro web site at www.luminarymicro.com: ARM® CortexTM-M3 Technical Reference Manual CoreSightTM Design Kit Technical Reference Manual ARM® v7-M Architecture Application Level Reference Manual The following related documents are also referenced: IEEE Standard 1149.1-Test Access Port and Boundary-Scan Architecture This documentation list was current as of publication date. Please check the Luminary Micro web site for additional documentation, including application notes and white papers. Documentation Conventions This document uses the conventions shown in Table 0-1. Table 0-1. Documentation Conventions Notation Meaning General Register Notation REGISTER APB registers are indicated in uppercase bold. For example, PBORCTL is the Power-On and Brown-Out Reset Control register. If a register name contains a lowercase n, it represents more than one register. For example, SRCRn represents any (or all) of the three Software Reset Control registers: SRCR0, SRCR1, and SRCR2. bit A single bit in a register. bit field Two or more consecutive and related bits. offset 0xnnn A hexadecimal increment to a register's address, relative to that module's base address as specified in Table 3-1, "Memory Map," on page 37. October 8, 2006 19 Preliminary About This Document Table 0-1. Documentation Conventions Notation Meaning Register N Registers are numbered consecutively throughout the document to aid in referencing them. The register number has no meaning to software. reserved Register bits marked reserved are reserved for future use. Reserved bits return an indeterminate value, and should never be changed. Only write a reserved bit with its current value. yy:xx The range of register bits inclusive from xx to yy. For example, 31:15 means bits 15 through 31 in that register. Register Bit/Field Types This value in the register bit diagram indicates whether software running on the controller can change the value of the bit field. RO Software can read this field. Always write the chip reset value. R/W Software can read or write this field. R/W1C Software can read or write this field. A write of a 0 to a W1C bit does not affect the bit value in the register. A write of a 1 clears the value of the bit in the register; the remaining bits remain unchanged. This register type is primarily used for clearing interrupt status bits where the read operation provides the interrupt status and the write of the read value clears only the interrupts being reported at the time the register was read. W1C Software can write this field. A write of a 0 to a W1C bit does not affect the bit value in the register. A write of a 1 clears the value of the bit in the register; the remaining bits remain unchanged. A read of the register returns no meaningful data. This register is typically used to clear the corresponding bit in an interrupt register. WO Only a write by software is valid; a read of the register returns no meaningful data. Register Bit/Field Reset Value This value in the register bit diagram shows the bit/field value after any reset, unless noted. 0 Bit cleared to 0 on chip reset. 1 Bit set to 1 on chip reset. ­ Nondeterministic. Pin/Signal Notation [] Pin alternate function; a pin defaults to the signal without the brackets. pin Refers to the physical connection on the package. signal Refers to the electrical signal encoding of a pin. 20 October 8, 2006 Preliminary LM3S801 LM3S801 Data Sheet Table 0-1. Documentation Conventions Notation Meaning assert a signal Change the value of the signal from the logically False state to the logically True state. For active High signals, the asserted signal value is 1 (High); for active Low signals, the asserted signal value is 0 (Low). The active polarity (High or Low) is defined by the signal name (see SIGNAL and SIGNAL below). deassert a signal Change the value of the signal from the logically True state to the logically False state. SIGNAL Signal names are in uppercase and in the Courier font. An overbar on a signal name indicates that it is active Low. To assert SIGNAL is to drive it Low; to deassert SIGNAL is to drive it High. SIGNAL Signal names are in uppercase and in the Courier font. An active High signal has no overbar. To assert SIGNAL is to drive it High; to deassert SIGNAL is to drive it Low. Numbers X An uppercase X indicates any of several values is allowed, where X can be any legal pattern. For example, a binary value of 0X00 can be either 0100 or 0000, a hex value of 0xX is 0x0 or 0x1, and so on. 0x Hexadecimal numbers have a prefix of 0x. For example, 0x00FF is the hexadecimal number FF. Binary numbers are indicated with a b suffix, for example, 1011b. Decimal numbers are written without a prefix or suffix. October 8, 2006 21 Preliminary Architectural Overview 1 Architectural Overview The Luminary Micro StellarisTM family of microcontrollers-the first ARM® CortexTM-M3 based controllers-brings high-performance 32-bit computing to cost-sensitive embedded microcontroller applications. These pioneering parts deliver customers 32-bit performance at a cost equivalent to legacy 8- and 16-bit devices, all in a package with a small footprint. The LM3S801 LM3S801 controller in the Stellaris family offers the advantages of ARM's widely available development tools, System-on-Chip (SoC) infrastructure IP applications, and a large user community. Additionally, the controller uses ARM's Thumb®-compatible Thumb-2 instruction set to reduce memory requirements and, thereby, cost. Luminary Micro offers a complete solution to get to market quickly, with a customer development board, white papers and application notes, and a strong support, sales, and distributor network. 1.1 Product Features The LM3S801 LM3S801 microcontroller includes the following product features: 32-Bit RISC Performance ­ 32-bit ARM® CortexTM-M3 v7M architecture optimized for small-footprint embedded applications ­ Thumb®-compatible Thumb-2-only instruction set processor core for high code density ­ 50-MHz operation ­ Hardware-division and single-cycle-multiplication ­ Integrated Nested Vectored Interrupt Controller (NVIC) providing deterministic interrupt handling ­ 26 interrupts with eight priority levels ­ Memory protection unit (MPU) provides a privileged mode for protected operating system functionality ­ Unaligned data access, enabling data to be efficiently packed into memory ­ Atomic bit manipulation (bit-banding) delivers maximum memory utilization and streamlined peripheral control Internal Memory ­ 64 KB single-cycle flash · User-managed flash block protection on a 2-KB block basis · User-managed flash data programming · User-defined and managed flash-protection block ­ 8 KB single-cycle SRAM General-Purpose Timers ­ Three timers, each of which can be configured as a single 32-bit timer or as two 16-bit timers ­ 32-bit Timer modes: · Programmable one-shot timer · Programmable periodic timer · Real-Time Clock when using an external 32.768-KHz clock as the input 22 October 8, 2006 Preliminary LM3S801 LM3S801 Data Sheet · User-enabled stalling in periodic and one-shot mode when the controller asserts the CPU Halt flag during debug ­ 16-bit Timer modes: · General-purpose timer function with an 8-bit prescaler · Programmable one-shot timer · Programmable periodic timer · User-enabled stalling when the controller asserts CPU Halt flag during debug ­ 16-bit Input Capture modes: · Input edge count capture · Input edge time capture ­ 16-bit PWM mode: · Simple PWM mode with software-programmable output inversion of the PWM signal ARM FiRM-compliant Watchdog Timer ­ 32-bit down counter with a programmable load register ­ Separate watchdog clock with an enable ­ Programmable interrupt generation logic with interrupt masking ­ Lock register protection from runaway software ­ Reset generation logic with an enable/disable ­ User-enabled stalling when the controller asserts the CPU Halt flag during debug Synchronous Serial Interface (SSI) ­ Master or slave operation ­ Programmable clock bit rate and prescale ­ Separate transmit and receive FIFOs, 16 bits wide, 8 locations deep ­ Programmable interface operation for Freescale SPI, MICROWIRE, or Texas Instruments synchronous serial interfaces ­ Programmable data frame size from 4 to 16 bits ­ Internal loopback test mode for diagnostic/debug testing UART ­ Two fully programmable 16C550-type UARTs ­ Separate 16x8 transmit (TX) and 16x12 receive (RX) FIFOs to reduce CPU interrupt service loading ­ Programmable baud-rate generator with fractional divider ­ Programmable FIFO length, including 1-byte deep operation providing conventional double-buffered interface ­ FIFO trigger levels of 1/8, 1/4, 1/2, 3/4, and 7/8 ­ Standard asynchronous communication bits for start, stop, and parity ­ False-start-bit detection ­ Line-break generation and detection October 8, 2006 23 Preliminary Architectural Overview Analog Comparators ­ Three independent integrated analog comparators ­ Configurable for output to drive an output pin or generate an interrupt ­ Compare external pin input to external pin input or to internal programmable voltage reference I2C ­ Master and slave receive and transmit operation with transmission speed up to 100 Kbps in Standard mode and 400 Kbps in Fast mode ­ Interrupt generation ­ Master with arbitration and clock synchronization, multimaster support, and 7-bit addressing mode PWM ­ Three PWM generator blocks, each with one 16-bit counter, two comparators, a PWM generator, and a dead-band generator ­ One 16-bit counter · Runs in Down or Up/Down mode · Output frequency controlled by a 16-bit load value · Load value updates can be synchronized · Produces output signals at zero and load value ­ Two comparators · Comparator value updates can be synchronized · Produces output signals on match ­ PWM generator · Output PWM signal is constructed based on actions taken as a result of the counter and comparator output signals · Produces two independent PWM signals ­ Dead-band generator · Produces two PWM signals with programmable dead-band delays suitable for driving a half-H bridge · Can be bypassed, leaving input PWM signals unmodified ­ Flexible output control block with PWM output enable of each PWM signal · PWM output enable of each PWM signal · Optional output inversion of each PWM signal (polarity control) · Optional fault handling for each PWM signal · Synchronization of timers in the PWM generator blocks · Synchronization of timer/comparator updates across the PWM generator blocks · Interrupt status summary of the PWM generator blocks QEI ­ Hardware position integrator tracks the encoder position 24 October 8, 2006 Preliminary LM3S801 LM3S801 Data Sheet ­ Velocity capture using built-in timer ­ Interrupt generation on index pulse, velocity-timer expiration, direction change, and quadrature error detection GPIOs ­ Up to 36 GPIOs, depending on configuration ­ 5-V-tolerant input/outputs ­ Programmable interrupt generation as either edge-triggered or level-sensitive ­ Bit masking in both read and write operations through address lines ­ Programmable control for GPIO pad configuration: · Weak pull-up or pull-down resistors · 2-mA, 4-mA, and 8-mA pad drive · Slew rate control for the 8-mA drive · Open drain enables · Digital input enables Power ­ On-chip Low Drop-Out (LDO) voltage regulator, with programmable output user-adjustable from 2.25 V to 2.75 V ­ Low-power options on controller: Sleep and Deep-sleep modes ­ Low-power options for peripherals: software controls shutdown of individual peripherals ­ User-enabled LDO unregulated voltage detection and automatic reset ­ 3.3-V supply brownout detection and reporting via interrupt or reset Flexible Reset Sources ­ Power-on reset (POR) ­ Reset pin assertion ­ Brown-out (BOR) detector alerts to system power drops ­ Software reset ­ Watchdog timer reset ­ Internal low drop-out (LDO) regulator output goes unregulated Additional Features ­ Six reset sources ­ Programmable clock source control ­ Clock gating to individual peripherals for power savings ­ IEEE 1149.1-1990 compliant Test Access Port (TAP) controller ­ Debug access via JTAG and Serial Wire interfaces ­ Full JTAG boundary scan Industrial-range 48-pin RoHS-compliant LQFP package October 8, 2006 25 Preliminary Architectural Overview 1.2 Target Applications Factory automation and control Industrial control power devices Building and home automation Brushless DC and AC induction motors 26 October 8, 2006 Preliminary LM3S801 LM3S801 Data Sheet 1.3 High-Level Block Diagram Figure 1-1. Stellaris High-Level Block Diagram ARM Cortex-M3 (including Nested DCode bus Flash Vectored Interrupt Controller (NVIC) ICode bus System Control & Clocks LMI JTAG Test Access Port (TAP) Controller APB Bridge Memory Peripherals SRAM General-Purpose Timers General-Purpose Input/Outputs (GPIOs) System Peripherals Universal Asynchronous Receivers/ Transmitters (UARTs) Peripheral Bus Watchdog Timer Inter Integrated Circuit (I2C) Synchronous Serial Serial Communications Interface Peripherals (SSI) Analog Comparators Quadrature Encoder Interface (QEI) Pulse Width Modulator (PWM) Analog Peripherals Motor Control Peripherals LM3S801 LM3S801 October 8, 2006 27 Preliminary Architectural Overview 1.4 Functional Overview The following sections provide an overview of the features of the LM3S801 LM3S801 microcontroller. The chapter number in parenthesis indicates where that feature is discussed in detail. Ordering and support information can be found in "Ordering and Contact Information" on page 396. 1.4.1 ARM CortexTM-M3 1.4.1.1 Processor Core (Section 2 on page 34) All members of the Stellaris product family, including the LM3S801 LM3S801 microcontroller, are designed around an ARM CortexTM-M3 processor core. The ARM Cortex-M3 processor provides the core for a high-performance, low-cost platform that meets the needs of minimal memory implementation, reduced pin count, and low power consumption, while delivering outstanding computational performance and exceptional system response to interrupts. Section 2, "ARM Cortex-M3 Processor Core," on page 34 provides an overview of the ARM core; the core is detailed in the ARM® CortexTM-M3 Technical Reference Manual. 1.4.1.2 Nested Vectored Interrupt Controller (NVIC) The LM3S801 LM3S801 controller includes the ARM Nested Vectored Interrupt Controller (NVIC) on the ARM Cortex-M3 core. The NVIC and Cortex-M3 prioritize and handle all exceptions. All exceptions are handled in Handler Mode. The processor state is automatically stored to the stack on an exception, and automatically restored from the stack at the end of the Interrupt Service Routine (ISR). The vector is fetched in parallel to the state saving, which enables efficient interrupt entry. The processor supports tail-chaining, which enables back-to-back interrupts to be performed without the overhead of state saving and restoration. Software ca