LH28F008BJU-WTLZ4 LHF08JZ4 FM032005B 32-LEAD 20K-100K A10-A0 A31-A24 A23-A20 - Datasheet Archive

 

® Integrated Circuits Group LH28F008BJU-WTLZ4 Flash Memory 8M (1M × 8) (Model No.: LHF08JZ4) Spec No.: FM032005B Issue

 

PRELIMINARY PRODUCT SPECIFICATIONS ® Integrated Circuits Group LH28F008BJU-WTLZ4 LH28F008BJU-WTLZ4 Flash Memory 8M (1M × 8) (Model No.: LHF08JZ4 LHF08JZ4) Spec No.: FM032005B FM032005B Issue Date: April 3, 2003 sharp LHF08JZ4 LHF08JZ4 · Handle this document carefully for it contains material protected by international copyright law. Any reproduction, full or in part, of this material is prohibited without the express written permission of the company. · When using the products covered herein, please observe the conditions written herein and the precautions outlined in the following paragraphs. In no event shall the company be liable for any damages resulting from failure to strictly adhere to these conditions and precautions. (1) The products covered herein are designed and manufactured for the following application areas. When using the products covered herein for the equipment listed in Paragraph (2), even for the following application areas, be sure to observe the precautions given in Paragraph (2). Never use the products for the equipment listed in Paragraph (3). · Office electronics · Instrumentation and measuring equipment · Machine tools · Audiovisual equipment · Home appliance · Communication equipment other than for trunk lines (2) Those contemplating using the products covered herein for the following equipment which demands high reliability, should first contact a sales representative of the company and then accept responsibility for incorporating into the design fail-safe operation, redundancy, and other appropriate measures for ensuring reliability and safety of the equipment and the overall system. · Control and safety devices for airplanes, trains, automobiles, and other transportation equipment · Mainframe computers · Traffic control systems · Gas leak detectors and automatic cutoff devices · Rescue and security equipment · Other safety devices and safety equipment, etc. (3) Do not use the products covered herein for the following equipment which demands extremely high performance in terms of functionality, reliability, or accuracy. · Aerospace equipment · Communications equipment for trunk lines · Control equipment for the nuclear power industry · Medical equipment related to life support, etc. (4) Please direct all queries and comments regarding the interpretation of the above three Paragraphs to a sales representative of the company. · Please direct all queries regarding the products covered herein to a sales representative of the company. Rev. 0.04 sharp LHF08JZ4 LHF08JZ4 1 CONTENTS PAGE PAGE 1 Product Description . 4 2.12 Memory Map . 14 2 Device Operation. 6 2.13 A/A Mode. 15 2.1 Mode Selection . 6 2.14 Command Definitions . 16 2.2 LPC Mode . 6 2.15 Status Register Definition . 17 2.2.1 CE#, LFRAME#. 6 3 Electrical Specifications . 18 2.2.2 Abort Mechanism . 6 3.1 Absolute Maximum Ratings . 18 2.3 Status Polling DQ7 (LPC Mode, A/A Mode) . 6 3.2 Operating Conditions . 18 2.4 Toggle Bit DQ6 (LPC Mode, A/A Mode) . 6 3.2.1 Capacitance . 18 2.5 LPC Memory Cycle Field Definitions . 7 3.2.2 AC Input/Output Test Conditions . 19 2.6 Multi Byte Read (LPC Mode) . 9 3.2.3 DC Characteristics . 20 2.7 Multiple Device Selection (LPC Mode) . 10 3.2.4 AC Characteristics (LPC Mode) . 22 2.8 General Purpose Inputs (GPI) Register (LPC Mode). 11 3.2.5 Reset and Abort Operations (LPC Mode) 29 2.9 Product Identifier Codes (LPC Mode, A/A Mode). 12 3.2.6 AC Characteristics (A/A Mode) . 31 3.2.7 Reset Operations (A/A Mode) . 35 2.10 Lock Registers (LPC Mode, A/A Mode) . 12 2.11 Write Protection . 13 2.11.1 TBL# and WP# Hardware Write Protection (LPC Mode) . 13 2.11.2 Whole Block Lock Software Write Protection (LPC Mode, A/A Mode) . 13 Rev. 0.04 sharp LHF08JZ4 LHF08JZ4 2 LH28F008BJU-WTLZ4 LH28F008BJU-WTLZ4 8Mbit (1Mbit×8) LPC Flash MEMORY Conforms to Intel LPC Interface Specification 1.0 Optimized Array Blocking Architecture · Fifteen 64-KByte Uniform Blocks · Eight 8-KByte Boot Sectors · Boot Sector Data Protection for each 8-KByte sector · Full Chip Erase for A/A Mode Only VCC=3.0V-3.6V Operation Extended Cycling Capability · Minimum 100,000 Block Erase Cycles Low Power Consumption (LPC Interface) · Standby Current : 15µA (Max.) · Read Current : 15mA (Max.) · Erase or Program Current : 25mA (Max.) Erase or Program Operation · Byte Program Time : 25µs (Typ.) · Sector Erase Time : 0.6s (Typ.) · Block Erase Time : 1.2s (Typ.) · Full Chip Erase Time : 40s (Typ.) · Sector Rewrite Time : 0.8s (Typ.) · Block Rewrite Time : 2.8s (Typ.) Operating Temperature 0°C to +85°C CMOS Process (P-type silicon substrate) Two Operational Modes · Low Pin Count (LPC) Interface mode for In-System operation · Address/Address Multiplexed Interface (A/A) Mode for production erasing and programming LPC Interface Mode · 5 signal communication interface supporting byte Read and Write · 33MHz clock frequency operation · WP# and TBL# pins provide hardware data protection for entire chip and/or boot sector · Status Polling and Toggle Bit for End-of-Write detection · 5 GPI pins for system design flexibility · ID pins for multi-chip selection Multi Byte Read Mode (LPC) · Max. 128-Byte Sequential Read Operation for data transfer A/A Interface Mode · 11 pin multiplexed address and 8-pin data I/O interface · Supports fast In-System or PROM programming for manufacturing CMOS and PCI I/O Compatibility 32-Lead PLCC ETOXTM* Flash Technology Not designed or rated as radiation hardened Rev. 0.04 sharp (GPI4) R/C# (LCLK) 1 32 31 30 A10 2 VCC (VCC) RST# (RST#) 3 (NC) (GPI3) A9 4 3 NC (GPI2) A8 LHF08JZ4 LHF08JZ4 A7 A6 A5 A4 5 29 6 28 A3 9 A2 A1 10 11 23 (ID0) A0 (LAD0) DQ0 12 22 7 27 32-LEAD 32-LEAD PLCC 11.4mm x 14mm TOP VIEW 8 26 25 24 13 21 MODE (MODE) (CE#) NC (NC) NC NC (NC) VCC (VCC) OE# (INIT#) WE# (LFRAME#) RY/BY# (RY/BY#) DQ7 (RES) (RES) DQ6 (RES) DQ5 (RES) DQ4 (LAD3) DQ3 (GND) GND (LAD2) DQ2 14 15 16 17 18 19 20 (LAD1) DQ1 (GPI1) (GPI0) (WP#) (TBL#) (ID3) (ID2) (ID1) Figure 1. 32-Lead PLCC Pinout Symbols inside ( ) are those for LPC mode. Rev. 0.04 sharp LHF08JZ4 LHF08JZ4 4 1 Product Description The product is offered in 32-Lead PLCC package. Refer to Figure 1 for pinouts and Table 1 for pin descriptions. Table 1. Pin Descriptions Symbol Type Interface A/A LPC Name and Function RST# INPUT RESET: When low (VIL), RST# resets internal automation and inhibits erase and program operations, which provides data protection. RST#-high (VIH) enables normal operation. After power-up or reset mode, the device is automatically set to read array mode. MODE INPUT MODE: This pin determines which interface is operational. This pin must be held high (VIH) for A/A mode and low (VIL) for LPC mode. This pin is internally pulled-down with a resistor between 20K-100K 20K-100K. INIT# INPUT INITIALIZE: This is the second reset pin for in-system use. This pin is internally combined with the RST# pin; If this pin or RST# pin is driven low, identical operation is exhibited. CE# INPUT CHIP ENABLE: This signal must be asserted to select the device. When CE# is low, the device is enabled. When CE# is high, the device is placed in low power standby mode. LFRAME# INPUT FRAME: To indicate start of a data transfer operation. This pin is also used to abort an LPC cycle in progress. LAD3-LAD0 INPUT/ OUTPUT ADDRESS AND DATA: To provide LPC control signals, as well as addresses and command Inputs data/Outputs data. LCLK INPUT CLOCK: To provide a clock input to the control unit. ID3-ID0 INPUT IDENTIFICATION INPUTS: These four pins are part of the mechanism that allows multiple parts to be attached to the same bus. The strapping of these pins is used to identify the component. These pins are internally pulled-down with a resistor between 20K-100K 20K-100K. GPI4-GPI0 INPUT GENERAL PURPOSE INPUTS: These individual inputs can be used for additional board flexibility. The state of these pins can be read through GPI registers. TBL# INPUT TOP BOOT LOCK: When low, prevents erasing and programming to the boot sectors at top (highest address) of memory. When TBL# is high, it disables hardware data protection for the boot sectors. This pin cannot be left unconnected. WP# INPUT WRITE PROTECT: When low, prevents erasing and programming to all blocks other than boot sector. When WP# is high, it disables hardware data protection for these blocks. This pin cannot be left unconnected. RESERVED: These pins must be left unconnected. RES OE# INPUT OUTPUT ENABLE: Gates the device's outputs during a read cycle. Rev. 0.04 sharp LHF08JZ4 LHF08JZ4 5 Table 1. Pin Descriptions (Continued) Interface Symbol Type WE# INPUT WRITE ENABLE: Controls writes to the memory array. Data is latched on the rising edge of WE#. R/C# INPUT ROW/COLUMN SELECT: For A/A interface mode, this pin determines whether the address pins are porting to the row address, or to the column address. A10-A0 A10-A0 INPUT ADDRESS INPUTS: Inputs for low-order addresses during read and write operations. Addresses are internally latched by R/C# during an erase or program cycle. These addresses share the same pins as the high-order address inputs. DQ7-DQ0 INPUT/ OUTPUT DATA INPUTS/OUTPUTS: Inputs data and commands during write cycles, outputs data during memory array, status register and identifier code reads. Data pins float to high-impedance (High Z) when the chip or outputs are deselected. Data is internally latched during an erase or program cycle. RY/BY# OPEN DRAIN OUTPUT VCC SUPPLY GND SUPPLY NC A/A LPC Name and Function READY/BUSY#: This output pin is a reflection bit 7 in the status register. This pin is used to determine the erase or program completion. This pin must be pulled-up with an external resistor on board. DEVICE POWER SUPPLY (3.0V-3.6V): With VCCVLKO, all write attempts to the flash memory are inhibited. Device operations at invalid VCC voltage (refer to DC Characteristics) produce spurious results and should not be attempted. GROUND: Do not float any ground pins. NO CONNECT: Lead is not internally connected; it may be driven or floated. Rev. 0.04 sharp LHF08JZ4 LHF08JZ4 2 Device Operation 2.1 Mode Selection The product can operate in two distinct interface modes: · The LPC interface mode for In-System erasing and programming · Address/Address Multiplexed (A/A) interface mode for factory erasing and programming The state of the device's MODE pin determines which interface is in use. If the MODE pin is set to logic high, the device is in A/A mode; while if the MODE pin is set low, the device is in the LPC mode. The MODE selection pin must be configured prior to device operation. 2.2 LPC Mode The LPC mode uses a 5-signal communication interface, 4-bit address/data bus, LAD3-LAD0, and a control line, LFRAME#, to control operations of the product. Cycle type operations such as Memory Read and Memory Write are defined in Intel Low Pin Count Interface Specification, Rev.1.0. Erase and Program commands sequences are incorporated into the standard LPC memory cycles. LPC signals are transmitted via the 4-bit Address/Data bus (LAD3-LAD0), and follow a particular sequence, depending on whether they are Read or Write operations. The standard LPC memory cycle is defined in Table 2 and Table 3. 6 value on LAD3-LAD0 will initiate device operation. The device enters standby mode when LFRAME# and CE# are high and no internal operations is in progress. 2.2.2 Abort Mechanism If LFRAME# is driven low for 4 clock cycles during a LPC cycle, the cycle will be terminated and the device will wait for the "ABORT" command. To return the device to the ready mode, the host must drive the LAD3LAD0 with "1111b" ("ABORT" command) while LFRAME# is driven low, and LAD3-LAD0 must remain unchanged until LFRAME# goes to VIH (refer to Figure 18). If abort occurs during the internal write cycle, the data may be incorrectly programmed or erased. It is required to wait for the write operation to complete prior to initiation of the abort command. It is recommended to check the write status with status polling (DQ7) or toggle bit (DQ6). One other option is to wait for the fixed write time to expire. 2.3 Status Polling DQ7 (LPC Mode, A/A Mode) When the product device is in the automatic internal operation (program, erase, etc.), WSM (Write State Machine) status bit DQ7 (SR.7) will produce a "0". Once the internal operation is completed, DQ7 will produce a "1". The SR.7 bit can be polled to find the end of the operation. The other status bits (SR.5-0) should not be checked until the WSM completes the operation and the status bit SR.7 is "1". Refer to Table 13 for the status register definition. 2.2.1 CE#, LFRAME# 2.4 Toggle Bit DQ6 (LPC Mode, A/A Mode) The CE# pin, enables and disables the product, controlling read and write access of the device. To enable the product, the CE# pin must be driven low one cycle prior to LFRAME# being driven low. For write (erase or program) cycles, the CE# pin must remain low during the internal operation. When CE# is high, the product is placed in standby mode. During the automatic internal operation (program, erase, etc.), any consecutive attempts to read DQ6 (SR.6) will produce alternating "0"s and "1"s, i.e., toggling between "0" and "1". When the internal operation is completed, the toggling will stop. The LFRAME# signifies the start of a frame or the termination of a broken frame. Asserting LFRAME# for one or more clock cycle and driving a valid "START" Rev. 0.04 sharp LHF08JZ4 LHF08JZ4 7 2.5 LPC Memory Cycle Field Definitions Table 2. LPC Read Cycle Field Definitions Field Clocks LAD3-LAD0 Direction START 1 INPUT Start of Cycle: "0000b" appears on LPC bus to indicate the start of cycle. CYCTYPE 1 INPUT Cycle Type: Indicates the type of cycle. LAD3-LAD2 must be "01b" for memory cycle. LAD1 indicates the direction of the transfer: "0b" for read. LAD0 is reserved for future implementation. Description ADDR 8 INPUT Address Phase for Memory Cycle: LPC supports the 32-bit address protocol. It is transferred most significant nibble first. All the values of A31-A24 A31-A24 must be set to "1". For A23-A20 A23-A20 values, refer to Table 6. TAR 2 INPUT then High Z Turn-Around: It indicates a turn-around cycle to drive LAD3-LAD0 to "1111b" during the first clock and to drive LAD3-LAD0 to High Z during the second clock by the host. Sync 1-3 OUTPUT Sync: Synchronize to host or peripheral by adding wait states. "0000b" means Ready, "0101b" means Short Wait. The product supports three types of wait states: "no-wait", "1-wait", or "2-waits". Data 2 OUTPUT Data Phase: The data byte is transferred least significant nibble first. (DQ3-DQ0 on LAD3-LAD0 first, DQ7-DQ4 on LAD3-LAD0 last.) 2 OUTPUT then High Z Turn-Around: It indicates a turn-around cycle to drive LAD3-LAD0 to "1111b" during the first clock and to drive LAD3-LAD0 to High Z during the second clock by the Flash Memory. TAR Rev. 0.04 sharp LHF08JZ4 LHF08JZ4 8 Table 3. LPC Write Cycle Field Definitions Field Clocks LAD3-LAD0 Direction START 1 INPUT Start of Cycle: "0000b" appears on LPC bus to indicate the start of cycle. CYCTYPE 1 INPUT Cycle Type: Indicates the type of cycle. LAD3-LAD2 must be "01b" for memory cycle. LAD1 indicates the direction of the transfer: "1b" for write. LAD0 is reserved for future implementation. ADDR 8 INPUT Address Phase for Memory Cycle: LPC supports the 32-bit address protocol. It is transferred most significant nibble first. All the values of A31-A24 A31-A24 must be set to "1". For A23-A20 A23-A20 values, refer to Table 6. Data 2 INPUT Data Phase: The data byte is transferred least significant nibble first. (DQ3-DQ0 on LAD3-LAD0 first, DQ7-DQ4 on LAD3-LAD0 last.) TAR 2 INPUT then High Z Turn-Around: It indicates a turn-around cycle to drive LAD3-LAD0 to "1111b" during the first clock and to drive LAD3-LAD0 to High Z during the second clock by the last components driving LAD3-LAD0. Sync 1 OUTPUT Sync: The product only supports "0000b" Ready sync. 2 OUTPUT then High Z Turn-Around: It indicates a turn-around cycle to drive LAD3-LAD0 to "1111b" during the first clock and to drive LAD3-LAD0 to High Z during the second clock by the Flash Memory. TAR Description Rev. 0.04 sharp LHF08JZ4 LHF08JZ4 2.6 Multi Byte Read (LPC Mode) The product provides Multi Byte Read operation in LPC mode. Multi Byte Read mode enables two or more byte 9 of sequential read at one operation cycle. This increases data transfer rate compared with normal memory read operation. The transfer multi-byte size can be selected from four types. Table 4. LPC Multi Byte Read Cycle Field Definitions Field Clocks LAD3-LAD0 Direction START 1 INPUT Start of Cycle: "0000b" appears on LPC bus to indicate the start of cycle. CYCTYPE 1 INPUT Cycle Type: "1100b" = Multi Byte Read Description 2 byte 01 8 byte 32 byte 11 1 Transfer Byte Size 10 MSIZE LAD1-LAD0 00 Transfer Multi-Byte Size: 128 byte INPUT Address: Start address of Multi Byte Read: A31-A0 A31-A0. ADDR 8 INPUT TAR 2 Sync 1 N+1 OUTPUT Sync: "0101b" = Short Wait "0000b" = Ready Data 1 2 OUTPUT Data Phase: First byte; DQ3-DQ0 on LAD3-LAD0 (1st. cycle) DQ7-DQ4 on LAD3-LAD0 (2nd. cycle) Sync M (N+1) × M OUTPUT Sync: "0101b" = Short Wait "0000b" = Ready Data M 2×M OUTPUT Data Phase: Multi byte; DQ3-DQ0 on LAD3-LAD0 (1st. cycle) DQ7-DQ4 on LAD3-LAD0 (2nd. cycle) TAR 2 INPUT then Turn-Around: "1111b" and High Z High Z (N: the number of Short Wait) (N: the number of Short Wait) (M: the number of Multi Byte) OUTPUT then Turn-Around: "1111b" and High Z High Z Table 5. LPC Multi Byte Read Bandwidth [ f(CLK)=33MHz ] 128-Byte Multi Byte Read Clocks START 1 START 1 CYCTYPE 1 CYCTYPE 1 MSIZE+ADDR 9 ADDR 8 TAR 2 TAR 2 Sync (no-wait) 1 Data 2 Unit 128-Byte Normal Read Clocks Sync (no-wait) × 128 1 Data × 128 Unit 2 2 TAR 2 TAR Total Clocks 399 Total Clocks 17 × 128 Transfer Time 12 µs Transfer Time 65 µs Bandwidth 10.69 MByte/s Bandwidth 1.96 MByte/s Rev. 0.04 sharp LHF08JZ4 LHF08JZ4 2.7 Multiple Device Selection (LPC Mode) Multiple LPC Flash devices may be strapped to increase memory densities in a system. LPC protocol of the product supports up to 8 LPC Flash devices. 10 should use a sequential up-count strapping (i.e., "000x", "001x", "010x", "011x", etc.). ID0 is not used and may be either "0" or "1". The four ID pins, ID3-ID0, allow up to 8 devices to be attached to the same bus by using different ID strapping in a system. If the product is used as a boot device, ID3ID0 must be strapped as "000x", all subsequent devices 8Mbit 16Mbit Device 1 . 16Mbit 8Mbit Boot Device 0 8Mbit 16Mbit Device 6 8Mbit 16Mbit Device 7 Figure 2. Multiple LPC Device Mapping Table 6. ID Strapping Values (LPC Mode) Device No. ID3-ID0 0 (Boot device) 001x A22 2 010x 3 1 011x 4 10 Read: 1 = Memory Read 0 = Register Read 100x 5 101x 6 110x 7 111x A21-A20 A21-A20 11 000x 1 A23 01 00 11 0 Write: 0 or 1 = Memory Write 10 01 00 Rev. 0.04 sharp LHF08JZ4 LHF08JZ4 2.8 General Purpose Inputs (GPI) Register (LPC Mode) The GPI_REG (General Purpose Inputs Register) reads the status of the GPI4-GPI0 pins on the product. Since this is a pass-through register, there is no default value, only the state of the pins at power-up. The pins must have stable data from before the start of the cycle that reads the GPI_REG until after the cycle is complete. These pins must not be left to float and they should be driven VIL or VIH. 11 Refer to Table 7 for the GPI_REG bits and function, and Table 8 for memory address location for its respective device strapping. If this address is input, GPI_REG can be read also on read identifier codes mode, read status register mode or read array mode. Table 7. General Purpose Input Register Bit Function 7:5 Reserved for future implementation. 4 GPI4 : Reads status of general-purpose input pin (Pin 30) 3 GPI3 : Reads status of general-purpose input pin (Pin 3) 2 GPI2 : Reads status of general-purpose input pin (Pin 4) 1 GPI1 : Reads status of general-purpose input pin (Pin 5) 0 GPI0 : Reads status of general-purpose input pin (Pin 6) Table 8. Memory Map for General Purpose Input Register Addresses Device No. GPI_REG 0 (Boot device) FFBC0100H FFBC0100H 1 FFAC0100H FFAC0100H 2 FF9C0100H FF9C0100H 3 FF8C0100H FF8C0100H 4 FF3C0100H FF3C0100H 5 FF2C0100H FF2C0100H 6 FF1C0100H FF1C0100H 7 FF0C0100H FF0C0100H Rev. 0.04 sharp LHF08JZ4 LHF08JZ4 2.9 Product Identifier Codes (LPC Mode, A/A Mode) 12 2.10 Lock Registers (LPC Mode, A/A Mode) The product identifier codes identify the device as the product and manufacturer as SHARP. · In LPC mode: The Read Identifier Codes command is unnecessary and only an address shown in Table 9 is required. However, A22 must be "0" in this operation. The operation by the command is also possible if the Read Identifier Codes command is written. Any command is acceptable not only when A22="1" but also when A22="0". The product offers double write protection. The boot lock provides hardware write protection for each 8-Kbyte boot sector. Furthermore, the whole block lock provides software write protection for all sectors and blocks. The write protection status is controlled by each lock bit. Refer to "2.11 Write Protection" for details. The protection status can be checked through the lock registers. · In A/A mode: The Read Identifier Codes command is necessary. Refer to Table 12 for the command definitions. Table 9. LPC Flash Registers Configuration Map (1), (5) Device Address [A21-A20 A21-A20] 11 or 10 1 (3) Default Value FFFFFH - 00000H 00000H DQ1 = 1 RO 4 FE002H FE002H Block Lock Register (Sector 7) A22 (2) Protected Address Range [A19-A0 A19-A0] XX002H XX002H Whole Block Lock Register A23 (3) FFFFFH - FE000H FE000H DQ0 = 0 RO 4 FC002H FC002H Block Lock Register (Sector 6) FDFFFH - FC000H FC000H DQ0 = 0 RO 4 FA002H FA002H Block Lock Register (Sector 5) FBFFFH - FA000H FA000H DQ0 = 0 RO 4 F8002H F8002H Block Lock Register (Sector 4) F9FFFH - F8000H F8000H DQ0 = 0 RO 4 [A19-A0 A19-A0] Register Name Type Notes F6002H F6002H Block Lock Register (Sector 3) F7FFFH - F6000H F6000H DQ0 = 0 RO 4 F4002H F4002H Block Lock Register (Sector 2) F5FFFH - F4000H F4000H DQ0 = 0 RO 4 01 F2002H F2002H Block Lock Register (Sector 1) F3FFFH - F2000H F2000H DQ0 = 0 RO 4 F0002H F0002H Block Lock Register (Sector 0) F1FFFH - F0000H F0000H DQ0 = 0 RO 4 LPC General Purpose Input Register N/A N/A RO N/A C8H RO 00000H 00000H Manufacturer Code Register 0 0 (Register Access) or 00001H 00001H Device Code Register or N/A B0H RO or 00 C0100H C0100H NOTES: 1. A31-A20 A31-A20 are not used in A/A mode. 2. A22 must be "0" when the registers are read in LPC mode. 3. A23, A21-A20 A21-A20 correspond to the address for ID strapping (refer to Table 6). 4. DQ7-DQ2 are reserved for future implementation. 5. The registers shown above must not be read while the WSM is busy. Rev. 0.04 sharp LHF08JZ4 LHF08JZ4 2.11 Write Protection 13 Both TBL# and WP# pins must be set to their required protection states prior to starting an erase or program operation. A logic level change occurring at the TBL# or WP# pin during an erase or program operation could cause unpredictable results. 2.11.1 TBL# and WP# Hardware Write Protection (LPC Mode) The top boot lock (TBL#) and write protect (WP#) pins are provided for hardware write protection of the memory area in the product. TBL# pin is used to write protection of 8 boot sectors (8Kbytes) at the highest memory address range for the product. WP# pin is used for the remaining blocks in the flash memory. An active low signal at the TBL# pin prevents erase and program operations of the boot sectors. TBL# protection is effective only to the sector to which the boot lock bit is set. When TBL# pin is held high, the write protection of the boot sectors is disabled. The WP# pin serves the same function for the remaining blocks of the memory array. The TBL# and WP# pins write protection functions operate independently of one another. 2.11.2 Whole Block Lock Software Write Protection (LPC Mode, A/A Mode) The whole block lock is provided for software write protection of the memory area in the product. Whole block lock protects all sectors and blocks in the device by lock bit. The lock bit is set to locked state in an initial state after power-up or reset operation. The lock bit must be cleared to unlocked state before starting erase or program operation. The lock bit is cleared by clear whole block lock bit operation. After erase or program operation is finished, the memory array can be protected by set whole block lock bit operation. Table 10. Write Protection Alternatives TBL# Boot Lock Bit (1) WP# X X X All sectors and blocks are Locked. VIL 1 X Boot sector is Locked. VIL 0 X Boot sector is Unlocked. VIH X X All boot sectors are Unlocked VIH X VIL The remaining blocks other than boot sectors are Locked VIH Sector Erase or Block Erase or Full Chip Erase or Byte Program Whole Block Lock Bit (1) 1 Operation X VIH All sectors and blocks are Unlocked 0 Effect NOTES: 1. Lock Bit : "1" = Locked State, "0" = Unlocked State Rev. 0.04 sharp LHF08JZ4 LHF08JZ4 14 2.12 Memory Map Top Boot FFFFFH FE000H FE000H 8Kbyte Boot Sector 8Kbyte Boot Sector 6 8Kbyte Boot Sector 5 8Kbyte Boot Sector 4 8Kbyte Boot Sector 3 8Kbyte Boot Sector 2 8Kbyte Boot Sector 1 F2000H F2000H 8Kbyte Boot Sector TBL# for Boot Sector 0 - 7 7 0 F0000H F0000H EFFFFH E0000H E0000H 64Kbyte Block 64Kbyte Block 13 64Kbyte Block 12 64Kbyte Block 11 64Kbyte Block 10 64Kbyte Block 9 64Kbyte Block WP# for Block 0 - 14 14 8 64Kbyte Block 7 64Kbyte Block 6 64Kbyte Block 5 64Kbyte Block 4 64Kbyte Block 3 64Kbyte Block 2 64Kbyte Block 1 64Kbyte Block 0 FC000H FC000H FA000H FA000H F8000H F8000H 64Kbyte Block 15 F6000H F6000H F4000H F4000H D0000H D0000H C0000H C0000H B0000H B0000H A0000H A0000H 90000H 90000H 80000H 80000H 70000H 70000H 60000H 60000H 50000H 50000H 40000H 40000H 30000H 30000H 20000H 20000H 10000H 10000H 00000H 00000H Figure 3. Memory Map Rev. 0.04 sharp LHF08JZ4 LHF08JZ4 2.13 A/A Mode 15 During the software command sequence, the row address is latched on the falling edge of R/C# and the column address is latched on the rising edge of R/C#. Commands are used to initiate the memory operation functions of the device. The data portion of the software command sequence is latched on the rising edge of WE#. Table 11. Operation Modes Selection (1) Notes RST# OE# WE# Address DQ (2) 6 VIH VIL VIH AIN DOUT Output Disable VIH VIH VIH X High Z Standby VIH VIH VIH X High Z Mode Read Array Reset 3 VIL X X X High Z Read Identifier Codes 6 VIH VIL VIH Refer to Table 9 Refer to Table 9 4, 5, 6 VIH VIH VIL AIN DIN Write NOTES: 1. X can be VIL or VIH for control pins and addresses. 2. DQ refers to DQ7-DQ0. 3. RST# at GND±0.2V ensures the lowest power consumption. 4. Command writes involving sector/block erase, full chip erase, byte program, set whole block lock bit, clear whole block lock bit, set boot lock bit and clear boot lock bits are reliably executed when VCC=3.0V-3.6V. 5. Refer to Table 12 for valid DIN during a write operation. 6. Never hold OE# low and WE# low at the same timing. TBL# WP# INIT# DQ 7 -DQ 0 OE# WE# LPC Interface Command User Interface Address Buffers and Latches X-Decoder LAD 3 -LAD 0 LCLK LFRAME# ID 3 -ID 0 GPI 4 -GPI 0 R/C# A 10 -A 0 16M bit 8Mbit Flash Cell Array Y-Decoder Control Logic I/O Buffers and Data Latches MODE RST# CE# Figure 4. Block Diagram Rev. 0.04 sharp LHF08JZ4 LHF08JZ4 16 2.14 Command Definitions Table 12. Command Definitions (12) Interface Command Bus First Bus Cycle Cycles Notes Data Oper(1) Addr(2) A/A LPC Req'd Second Bus Cycle Oper(1) Addr(2) Data(3) Read Array O O 1 4 Write X FFH Read Identifier Codes O O 2 5 Write X 90H Read IA ID Read Status Register O O 2 Write X 70H Read X SRD Clear Status Register O O 1 4 Write X 50H Sector/Block Erase O O 2 6,7 Write BA 20H Write BA D0H Full Chip Erase O 2 6,7,8 Write X 30H Write X D0H Byte Program O O 2 6,7,9 Write X 40H or 10H Write WA WD Set Whole Block Lock Bit O O 2 Write X 60H Write X BBH Clear Whole Block Lock Bit O O 2 7 Write X 60H Write X DBH Set Boot Lock Bit O O 2 10 Write X 60H Write SA 01H Clear Boot Lock Bits O O 2 11 Write X 60H Write SA D0H NOTES: 1. Bus operations are defined in Table 11. 2. Any command is acceptable not only when A22="1" but also when A22="0" in LPC mode. X=Any valid address within the device. IA=Identifier codes address (Refer to Table 9). BA=Address within the sector/block for sector/block erase. WA=Address of memory location for program. SA=Address within the boot sector for set boot lock bit. 3. ID=Data to be read from identifier codes. (Refer to Table 9). SRD=Data to be read from status register. Refer to Table 13 for a description of the status register bits. WD=Data to be programmed at location WA. 4. The device returns to the read array mode even after Clear Status Register command or reset operation by RST#/INIT#. 5. Following the Read Identifier Codes command, read operations access manufacturer code, device code and block lock configuration code (Refer to Table 9). The identifier codes must not be read while the WSM is busy. 6. Sector/block erase, full chip erase and byte program operations cannot be executed to boot sector when TBL# goes to VIL. Sector/block erase, full chip erase and byte program operations cannot be executed to blocks other than boot sector when WP# goes to VIL. 7. Whole block lock bit must be cleared when executing sector/block erase, full chip erase and byte program operations. Sector/block erase, full chip erase and byte program operations cannot be executed if whole block lock bit is set. 8. Supported in A/A Mode only. Any boot sector which is locked by boot lock bit is protected from alteration. Boot lock bit should be cleared before performing an erase operation. 9. Either 40H or 10H are recognized as the program first bus cycle command. 10. Lock bit can be set to each sector within the boot block (block 15). Since this lock bit is non-volatility, it holds the lock state even after power-off or reset. 11. All boot lock bits of each sector are cleared at a time. SA=Address within the boot sector (1F0000H-1FFFFFH 1F0000H-1FFFFFH). 12. Commands other than those shown above are reserved by SHARP for future device implementations and should not be used. Rev. 0.04 sharp LHF08JZ4 LHF08JZ4 17 2.15 Status Register Definition Table 13. Status Register Definition WSMS TB ECLS PSLS PVEVS R DPS R 7 6 5 4 3 2 1 0 NOTES: SR.7 = WRITE STATE MACHINE STATUS (WSMS) 1 = Ready 0 = Busy SR.6 = TOGGLE BIT (TB) Toggling between "0" and "1" during the erase or program operation. SR.5 = SECTOR/BLOCK ERASE, FULL CHIP ERASE AND CLEAR BOOT LOCK BITS STATUS (ECLS) 1 = Error in Sector/Block Erase, Full Chip Erase or Clear Boot Lock Bits 0 = Successful Sector/Block Erase, Full Chip Erase or Clear Boot Lock Bits SR.4 = BYTE PROGRAM AND SET BOOT LOCK BIT STATUS (PSLS) 1 = Error in Byte Program or Set Boot Lock Bit 0 = Successful Byte Program or Set Boot Lock Bit SR.3 = PROGRAM VOLTAGE OR ERASE VOLTAGE STATUS (PVEVS) 1 = Invalid Program or Erase Voltage Detect, Operation Abort 0 = Program or Erase Voltage OK Check SR.7 or SR.6 or RY/BY# to determine sector/block erase, full chip erase, byte program, set whole block lock bit, clear whole block lock bit, set boot lock bit or clear boot lock bits completion. SR.5, SR.4, SR.3 and SR.1 are invalid while SR.7="0". If both SR.5 and SR.4 are "1"s after a sector/block erase, full chip erase, set whole block lock bit, clear whole block lock bit, set boot lock bit and clear boot lock bits attempt, an improper command sequence was entered. SR.3 indicates the program or erase voltage conditions. The program or erase voltage is the internal voltage which is used for the program or erase operation in the flash memory. SR.3 does not provide a continuous indication of the program or erase voltage level. The WSM interrogates and indicates the program or erase voltage level only after Sector/Block Erase, Full Chip Erase, Byte Program, Set Boot Lock Bit and Clear Boot Lock Bits command sequences. SR.2 = RESERVED FOR FUTURE ENHANCEMENTS (R) SR.1 does not provide a continuous indication of block lock SR.1 = DEVICE PROTECT STATUS (DPS) bit. The WSM interrogates TBL#, WP# or block lock bit only 1 = Erase or Program Attempted on a Locked Block by after Sector/Block Erase, Full Chip Erase or Byte Program TBL#, WP# or Block Lock Bit, Operation Abort command sequences. It informs the system, depending on the attempted operation, if the block is locked. 0 = Unlocked SR.0 = RESERVED FOR FUTURE ENHANCEMENTS (R) SR.2 and SR.0 are reserved for future use and should be masked out when polling the status register. Rev. 0.04 sharp LHF08JZ4 LHF08JZ4 18 *WARNING: Stressing the device beyond the "Absolute Maximum Ratings" may cause permanent damage. These are stress ratings only. Operation beyond the "Operating Conditions" is not recommended and extended exposure beyond the "Operating Conditions" may affect device reliability. 3 Electrical Specifications 3.1 Absolute Maximum Ratings* Operating Temperature During Read, Erase and Program . 0°C to +85°C (1) NOTES: 1. Operating temperature is for commercial temperature product defined by this specification. 2. All specified voltages are with respect to GND. Minimum DC voltage is -0.5V on input/output pins and -0.2V on VCC pin. During transitions, this level may undershoot to -2.0V for periods