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HFA1155IH96 Intersil Corporation 1 CHANNEL, VIDEO AMPLIFIER, PDSO5, PLASTIC, MO-178AA, SC-74A, SOT-23, 5 PIN visit Intersil
HFA1155IB Intersil Corporation OP-AMP, 10000uV OFFSET-MAX, PDSO8, PLASTIC, MS-012AA, SOIC-8 visit Intersil
HD1-15530-8 Intersil Corporation DATACOM, MANCHESTER ENCODER/DECODER, CDIP24, CERDIP-24 visit Intersil
HFA1155IB96 Intersil Corporation OP-AMP, 10000uV OFFSET-MAX, PDSO8, PLASTIC, MS-012AA, SOIC-8 visit Intersil
THS6032CGQE Texas Instruments DUAL LINE DRIVER, PLGA80, PLASTIC, LGA-80 visit Texas Instruments
THS6022IGQE Texas Instruments DUAL LINE DRIVER, PBGA80, PLASTIC, LGA-80 visit Texas Instruments

LGA 1155 PIN diagram

Catalog Datasheet MFG & Type PDF Document Tags

LGA 1155 Socket PIN diagram

Abstract: LGA 1155 PIN diagram III Features LGA 1155 Intel® CoreTM i7/i5/i3/Xeon® processors Dual Channel (ECC) DDR3 1333 MHz up , Intel LGA 1155 Sandy Bridge Processors Channel B (ECC) DDR3 1066/1333 DVI TI SN75DP139R GZR , WG2 version Socket Two 240-pin DDR3 memory sockets Onboard Intel HD Graphics Graphics VRAM 1 GB maximum shared memory with 2 GB and above system memory installed Video Output 15 pin VGA D-sub connector x1/onboard DVI pin header x 1 (Default on QG2 and WG2, optional on QVG) Interface 10/100/1000 Mbps
Advantech
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PCE-5126 NCT6776F PCE-5126QG2-00A1E 1960047831N001 LGA 1155 Socket PIN diagram LGA 1155 PIN diagram 1155 lga socket core i7 2600 INTEL CORE I3 2120 Nuvoton nct6776f Q67/B65/C206 1333MH LGA1155

WHM2040AE

Abstract: MIL-STD-202 and MIL-STD-883. Key Features: Impedance: MTBF2: LGA (land grid array) package , Temperature: Return Losses: Small size: Built-in Functions: 50 Ohm >600,000 hrs (68 Years) 6-pin k>1 , Total Power Dissipation mW 400 PIn,Max RF Input Power dBm 10 Tch Channel , Operating Temperature To 13 Maximum Average RF Input Power PIN, MAX dB dB 1.4 dB , frequency band and the amplifier is unconditional stable. Figure 5 is the block diagram of internal
WanTcom
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WHM2040AE WHM2040AE1

LGA 1155 PIN diagram

Abstract: LGA 1155 pin out device is housed in a low profile 4x4 mm, 16-pin, flip-chip LGA or a 3x3 mm 16 pin QFN package , 0.50 4.00 BSC 4.00 BSC 1.00 BSC 0.50 BSC NBSG86A PACKAGE DIMENSIONS 16 PIN LGA, 4x4x0.96 , SEL 3 10 Q VTSEL C 4 9 VCC VTD0 5 Figure 1. BGA-16 and LGA-16 Pinout , . Pin Description Pin BGA QFN Name I/O C2 1 OLS (Note 3) Input C1 2 SEL , VTSEL - Common Internal 50 W Termination Pin for SEL/SEL. See Table 7. (Note 1) A1 5 VTD1
ON Semiconductor
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FCLGA-16 LGA 1155 pin out 1155 lga socket pins LGA 775 Socket PIN diagram lga 1155 socket lga 1155 pinout lga 1155 socket FCBGA-16 NBSG86A/D

lga 1155

Abstract: 1155 lga socket products. A strappable control pin is provided to select between the two functions. The device is housed in a low profile 4x4 mm 16-pin Flip-Chip LGA (FCLGA) or a 3x3 mm 16 pin QFN package. The NBSG53A is , NBSG53A PACKAGE DIMENSIONS 16 PIN LGA, 4x4x0.96 CASE 526AB-01 ISSUE B NOTES: 1. DIMENSIONING AND , edge triggered device. http://onsemi.com MARKING DIAGRAM* SG 53A LYW FCBGA-16 BA SUFFIX , Figure 1. BGA-16 and LGA-16 Pinout (Top View) 6 7 8 VTD D D VTD Figure 2. QFN
ON Semiconductor
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LGA 1150 Socket PIN diagram NBSG53AMA1TBG LGA16 3x3 footprint LGA-16 3x3 FCLG 04/LGA 1150 Socket PIN diagram NBSG53A/D

LGA 1150 Socket PIN diagram

Abstract: LGA 1155 Socket PIN diagram . A strappable control pin is provided to select between the two functions. The device is housed in a low profile 4x4 mm 16-pin Flip-Chip LGA (FCLGA) or a 3x3 mm 16 pin QFN package. The NBSG53A is a , . BGA-16 and LGA-16 Pinout (Top View) Table 1. Pin Description Pin BGA C2 C1 QFN 1 2 Name VTCLK CLK I/O , NBSG53A PACKAGE DIMENSIONS 16 PIN LGA 4x4, 1.0P CASE 526AB-01 ISSUE C D 4X A B 0.10 C NOTES , http://onsemi.com MARKING DIAGRAM* FCBGA-16 BA SUFFIX CASE 489 SG 53A LYW FCLGA-16 MA SUFFIX
ON Semiconductor
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16 pins qfn 3x3 footprint

LGA 1155 PIN diagram

Abstract: LGA 1150 Socket PIN diagram device is housed in a low profile 4x4 mm, 16-pin, flip-chip LGA or a 3x3 mm 16 pin QFN package , BSC 4.00 BSC 1.00 BSC 0.50 BSC NBSG86A PACKAGE DIMENSIONS 16 PIN LGA 4x4, 1.0P CASE 526AB-01 , 4 9 VCC VTD0 5 Figure 1. BGA-16 and LGA-16 Pinout (Top View) 6 VTD1 D1 7 8 D1 VTD1 Figure 2. QFN-16 Pinout (Top View) Table 1. Pin Description Pin BGA QFN , Termination Pin for SEL/SEL. See Table 7. (Note 1) A1 5 VTD1 - Internal 50 W termination pin
ON Semiconductor
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lga 4x4 footprint lga-16 4x4 IC 2030 PIN CONNECTIONS transistor tip 1050 germanium transistor ac 128 qfn 3x3 tray dimension

socket lga 1156 pinout

Abstract: intel i5 MOTHERBOARD pcb CIRCUIT diagram processor at the IHS surface. Independent Loading Mechanism provides the force needed to seat the 1156-LGA , the topside markings on the processor. This diagram is to aid in the identification of the processor , LGA1156 Socket This chapter describes a surface mount, LGA (Land Grid Array) socket intended for the , indicated in Figure 3-6, a Pin 1 indicator on the cover provides a visual reference for proper orientation , Figure 3-6. Pick and Place Cover Pin 1 Pick & Place Cover ILM Installation 3.4 Package
Intel
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socket lga 1156 pinout intel i5 MOTHERBOARD pcb CIRCUIT diagram i3 desktop MOTHERBOARD CIRCUIT diagram 115XLM LGA 1156 PIN OUT diagram Intel socket 1156 PIN LAYOUT E20847 E21320 E58389

socket lga 1155 pinout

Abstract: lga1155 pinout force needed to seat the 1155-LGA land package onto the socket contacts. PCH Platform Controller , through this surface mount, 1155-land socket. PECI The Platform Environment Control Interface (PECI , processor. This diagram is to aid in the identification of the processor. Figure 2-3. 18 Processor , Socket 3 LGA1155 Socket This chapter describes a surface mount, LGA (Land Grid Array) socket intended for the processors. The socket provides I/O, power and ground contacts. The socket contains 1155
Intel
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lga1155 pinout lga1155 land profile pattern intel LGA 1155 PIN diagram pinout diagram for LGA1155 processor socket core lga1155 land REFLOW lga socket 1155 CHSP60PC UL1439

LGA 1156 PIN OUT diagram

Abstract: QSJ-44403 DIP8-P-300-2.54 5 Package material Lead frame material Pin treatment Package weight (g) Rev , -300-2.54 5 Package material Lead frame material Pin treatment Package weight (g) Rev. No./Last Revised , material Lead frame material Pin treatment Package weight (g) Rev. No./Last Revised Epoxy resin 42 alloy , material Pin treatment Package weight (g) Rev. No./Last Revised Epoxy resin 42 alloy Solder plating (5µm) 1.30 TYP. 2/Dec. 11, 1996 DIP20-P-300-2.54-W1 5 Package material Lead frame material Pin
OKI Electric Industry
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QSJ-44403 IC107-26035-20-G IC107-3204-G TB 2929 H alternative marking 453 8p land pattern for TSOP 2 86 DIP14-P-300-2 DIP16-P-300-2 DIP18-P-300-2 DIP22-P-400-2 DIP24-P-600-2 DIP28-P-600-2

3G/4G Power Amplifiers

Abstract: CATV Amplifiers 420 200 230 280 Package Style (dim. in mm) Part Number LGA 3.0 x 3.0 RFFM4203 LGA 4.0 x 4.0 RFFM4205 LGA 6.0 x 6.0 RFFM4204 LGA 3.0 x 3.0 RFFM4501 LGA 3.0 x 3.0 , (dim. in mm) Part Number LGA 3.0 x 3.0 RFFM4203 LGA 4.0 x 4.0 RFFM4205 LGA 6.0 x 6.0 RFFM4204 LGA 6.0 x 6.0 LGA 6.0 x 6.0 LGA 6.0 x 6.0 LGA 6.0 x 6.0 LGA 6.0 x 6.0 LGA 3.0 x 3.0 RFFM4200 RFFM4201 RFFM4202 RF5605 RFFM7600 RFFM4501 LGA 3.0 x 3.0 RFFM4501F WiFi and
RF Micro Devices
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3G/4G Power Amplifiers CATV Amplifiers CATV Hybrid Amplifier Modules Gain Blocks Linear Amplifiers Low Noise Amplifiers 11F-B

lga 1155 socket

Abstract: LGA 1155 pin out DIMENSIONS 16 PIN LGA 4x4, 1.0P CASE 526AB-01 ISSUE C D 4X A B 0.10 C NOTES: 1. DIMENSIONING , , LVCMOS, CML, or LVDS. The output amplitude is varied by applying a voltage to the VCTRL input pin , device only. The VBB is used as a reference voltage for single-ended NECL or PECL inputs and the VMM pin , VEE Figure 1. BGA-16 and LGA-16 Pinout (Top View) Figure 2. QFN-16 Pinout (Top View) Table 1. PIN DESCRIPTION Pin BGA C2 C1 QFN 1 2 Name VTD D I/O ECL, CML, LVCMOS, LVDS, LVTTL Input ECL, CML
ON Semiconductor
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NBSG16VS EP16VS 526AB NBSG16VS/D

LGA 1155 PIN diagram

Abstract: lga 4x4 footprint NBSG16VS PACKAGE DIMENSIONS 16 PIN LGA, 4x4x0.96 CASE 526AB-01 ISSUE B NOTES: 1. DIMENSIONING AND , amplitude is varied by applying a voltage to the VCTRL input pin. Outputs are variable swing ECL from 100 , reference voltage for single-ended NECL or PECL inputs and the VMM pin is used as a reference voltage for , . BGA-16 and LGA-16 Pinout (Top View) 6 7 8 NC VCTRL VEE Figure 2. QFN-16 Pinout (Top View) Table 1. PIN DESCRIPTION Pin BGA QFN Name I/O C2 1 VTD - C1 2
ON Semiconductor
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485G

srf 3417

Abstract: transistor srf 3417 Transceiver Block Diagram The DCRTM Transceiver family consists of: S KY74117 RF Transceiver-direct , /GPRS RF Subsystem with Integrated digital crystal oscillator DCRTM Transceiver Block Diagram , Supply Voltage (V) Package (mm) 2.9­4.8 22-pin MCM 6 x 8 x 1.2 2.9­4.8 20-pin MCM 6 x 6 x 1.2 2.9­4.8 20-pin MCM 6 x 6 x 1.2 2.9­4.8 16-pin MCM 6 x 8 x 1.2 The (Pb)-free , . HeliosTM DigRF Subsystem Block Diagram The HeliosTM DigRF Subsystem features: Direct
Skyworks Solutions
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srf 3417 transistor srf 3417 SKY77329 transistor tt 2170 em digrf SKY77519 CDMA2000 BRO254-07B
Abstract: embedded applications. The tiny form factor is configured on a Land Grid Array (LGA) assembly measuring , '  Tracking operation/Synchronized function Connection Diagram +Vin F1 External DC Power Source , Units Vdc W 20 A On/Off Control 14 Vdc Power Good Pin 6 Vdc Synchronized Pin 12 Vdc Sequence Pin Vin max Vdc Vin = Zero (no power) -55 125 ˚C Storage Temperature Range Absolute , Input currrent SYNC pin VSYNC = 3.0V 1 mA Minimun pulse width, SYNC 250 nS Minimum pulse set-up muRata
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OKL2-T/20-W12 5-14V OKL2-T20-W12
Abstract: embedded applications. The tiny form factor is configured on a Land Grid Array (LGA) assembly measuring , '  Tracking operation/Synchronized function Connection Diagram +Vin F1 External DC Power Source , Units Vdc W 20 A On/Off Control 14 Vdc Power Good Pin 6 Vdc Synchronized Pin 12 Vdc Sequence Pin Vin max Vdc Storage Temperature Range Vin = Zero (no power) -55 125 ˚C Absolute , Input currrent SYNC pin VSYNC = 3.0V 1 mA Minimun pulse width, SYNC 250 nS Minimum pulse set-up muRata Power Solutions
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Abstract: embedded applications. The tiny form factor is configured on a Land Grid Array (LGA) assembly measuring , Sequence/Tracking operation Connection Diagram +Vin F1 External DC Power Source On/Off , Units Vdc W 20 A On/Off Control 5.5 Vdc Sequence Pin Vin max Vdc Storage Temperature , Logic, ON state Pin open=ON -0.2 Vin-1.7 V Negative Logic, OFF state Vin-0.7 +Vin-max V Control Current open collector/drain 3 mA â'Pâ' suffix Positive Logic, ON state Pin open=ON +Vin-0.7V muRata
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OKL2-T/20-W5
Abstract: embedded applications. The tiny form factor is configured on a Land Grid Array (LGA) assembly measuring , '  Tracking operation/Synchronized function Connection Diagram +Vin F1 External DC Power Source , Units Vdc W 20 A On/Off Control 14 Vdc Power Good Pin 6 Vdc Synchronized Pin 12 Vdc Sequence Pin Vin max Vdc Storage Temperature Range Vin = Zero (no power) -55 125 ˚C Absolute , Input currrent SYNC pin VSYNC = 3.0V 1 mA Minimun pulse width, SYNC 250 nS Minimum pulse set-up muRata Power Solutions
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Abstract: embedded applications. The tiny form factor is configured on a Land Grid Array (LGA) assembly measuring , Sequence/Tracking operation Connection Diagram +Vin F1 External DC Power Source +Vout On , On/Off Control 5.5 Vdc Sequence Pin Vin max Vdc Storage Temperature Range Vin = Zero (no power , Remote On/Off Control (5) â'Nâ' suffix Negative Logic, ON state Pin open=ON -0.2 Vin-1.7 V , ' suffix Positive Logic, ON state Pin open=ON +Vin-0.7V Vin-max V Positive Logic, OFF state -0.3 muRata Power Solutions
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Abstract: held static 1.71 1.71 2.4 2.4 3.3 3.3 3.3 3.3 24.3 9 80.2 30 3.6 3.6 3.6 3.6 35 50 115.5 165 mA µA mW , www.ti.com PCM3793 PCM3794 SLES193C ­ AUGUST 2006 ­ REVISED FEBRUARY 2007 PIN ASSIGNMENTS PCM3793RHB , Clock Manager SPL SPOLP SPOLN +6 to ­70 dB FUNCTIONAL BLOCK DIAGRAM SPR SPORP SPORN +6 to ­70 , by using register 70 (OVER). Common Voltage The VCOM pin is normally biased to 0.5 VCC, and it , between this pin and ground to provide clean voltage and avoid pop noise. The PCM3793/94 may have a little Texas Instruments
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S/384
Abstract: held static 1.71 1.71 2.4 2.4 3.3 3.3 3.3 3.3 24.3 9 80.2 30 3.6 3.6 3.6 3.6 35 50 115.5 165 mA µA mW , www.ti.com PCM3793 PCM3794 SLES193C ­ AUGUST 2006 ­ REVISED FEBRUARY 2007 PIN ASSIGNMENTS PCM3793RHB , Clock Manager SPL SPOLP SPOLN +6 to ­70 dB FUNCTIONAL BLOCK DIAGRAM SPR SPORP SPORN +6 to ­70 , by using register 70 (OVER). Common Voltage The VCOM pin is normally biased to 0.5 VCC, and it , between this pin and ground to provide clean voltage and avoid pop noise. The PCM3793/94 may have a little Texas Instruments
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