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HS1-82C85RH-Q Intersil Corporation 15MHz, PROC SPECIFIC CLOCK GENERATOR, CDIP24 visit Intersil
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HS1-82C85RH-8 Intersil Corporation 15MHz, PROC SPECIFIC CLOCK GENERATOR, CDIP24, SIDE BRAZED, CERAMIC, DIP-24 visit Intersil

LDR SPECIFICATION

Catalog Datasheet MFG & Type PDF Document Tags

specification of ldr

Abstract: LDR SPECIFICATION pre-irradiation specification limits. 2. The 168-hour anneal was performed at 100oC under bias as shown in Figure , CURRENT (mA) 6 4 ISVP, LDR, BIASED ISVN, HDR, BIASED ISVP, CONTROL ISVN, CONTROL ISVP, SPEC LIMIT -2 ISVN, LDR, BIASED ISVN, LDR, GND 0 ISVP, LDR, GND ISVP, HDR, BIASED , high dose rate cell was 5 for each cell. The specification limits are +9.6mA (positive supply) and -9.6mA (negative supply). 500 400 OFFSET VOLTAGE (ÂuV) 300 200 100 0 -100 CH A, LDR
Intersil
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Abstract: specification limits are 2.042880V to 2.053120V (±0.25%). 0.6 LDR BIAS MEDIAN LDR BIAS MAX POWER , specification limits are 4.085760V to 4.106240V (±0.25%). 0.55 0.50 POWER SUPPLY CURRENT (mA) LDR , SPECIFICATION DLA Standard Microcircuit Drawing 5962-14208 Output voltage options 2.048V, 3.3V, 4.096V , LDR 8 150krad(Si) 2.048 0 100krad(Si) 5 8 50krad(Si) Biased 0 30krad(Si) LDR 8 Anneal 2.048 0 150krad(Si) 8 8 100krad(Si) Grounded 0 Intersil
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ISL71090SEHVF25

Abstract: post-irradiation specification limit is 1.28mA maximum. 20 LDR Bias Median LDR Bias Max LDR GND Min HDR Bias , provide individual discussion of the figures. 1.2545 LDR Bias Median LDR Bias Max LDR GND Min HDR Bias Median HDR Bias Max HDR GND Min Spec limit Output voltage, V 1.2535 LDR Bias Min LDR GND Median LDR GND Max HDR Bias Min HDR GND Median HDR GND Max Spec limit 1.2525 1.2515 , at high dose rate with all pins grounded. The SMD post-irradiation specification limits are
Intersil
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specification of ldr

Abstract: LDR SPECIFICATION 100 krad(Si) for the 15 units in each of the LDR and HDR test legs. The parametric specification , Trinh, and Joe Benedetto, PhD, Senior Member, IEEE Abstract- Low dose rate (LDR), ultralow dose rate , have been shown to fail LDR TID testing at doses from 18 to 25 krad(Si) [6][7]. INTRODUCTION , exposed at a low dose rate (LDR), Manuscript received July 29, 2009 Kirby Kruckmeyer is with National , [8]. Testing under LDR conditions was not routine, due to the time constraints. It can take several
National Semiconductor
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Abstract: maximum; the 2.0mA specification is an ATE limit. 180 HDR Ground HDR Biased LDR Ground LDR Biased , 400.0mV maximum; the 20mV specification is an ATE limit. 180 HDR Ground HDR Biased LDR Ground LDR , 400.0mV maximum; the 20mV specification is an ATE limit. 4.15 HDR Ground HDR Biased LDR Ground LDR , (1.0ms) maximum; the 100.0Âus specification is an ATE limit. 16 3000 HDR Ground HDR Biased LDR , (2.5ms) maximum; the 200.0Âus specification is an ATE limit. 3500 HDR Ground HDR Biased LDR Ground Intersil
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Abstract: post-irradiation SMD specification limits are -1.5°C to +0.5°C. 1.0 TEMPERATURE ERROR (°C) 0.5 LDR GND AVG LDR GND MAX LDR BIAS MIN SPEC LIMIT 0 LDR GND MIN LDR BIAS AVG LDR BIAS MAX SPEC , .0 November 1, 2013 Application Note 1895 Variables Data Plots 1.0 LDR GND AVG LDR GND MAX LDR BIAS MIN HDR GND AVG HDR GND MAX HDR BIAS MIN SPEC LIMIT TEMPERATURE ERROR (°C) 0.5 LDR GND MIN LDR BIAS AVG LDR BIAS MAX HDR GND MIN HDR BIAS AVG HDR BIAS MAX SPEC LIMIT 0 -0.5 Intersil
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Abstract: specification at 150krad(Si) LDR. Again it should be noted that most of this did not constitute functional , and 100% parametric yield to post-radiation specification at 50krad(Si) LDR downpoint. Wafer-by-wafer , Introduction Part Description This report summarizes the results of a low dose rate (LDR) total dose , specifically conducted to demonstrate LDR performance to support offering the 50krad(Si) LDR assurance tested , rad(Si)/s. Only the IS-139ASEH is wafer-by-wafer assurance tested at 50krad(Si) LDR (0.01 rad(Si)/s). Intersil
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IS-139ASRH MIL-STD-883H AN1821

sensitivity of ldr

Abstract: MIL-STD-883G though radiation at LDR is relatively minor compared to the historic parametric specification limit , it might be possible to simulate low dose rate (LDR) response by irradiating products at elevated , parametric drift to qualify products bipolar products for LDR environments [7]. This dose rate has been adopted for the LDR qualification in the latest revision of MIL-STD-883 (rev G) Test Method 1019 (rev. 7 , (Si) for LDR applications and could be considered to be "ELDRS-free". II. PRODUCTS TESTED The
National Semiconductor
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LM111 LM119 sensitivity of ldr MIL-STD-883G MILSTD-883G specification of ldr 3 pins LDR LM119xRLQMLV MIL-PRF-38535

3 pins LDR

Abstract: LDR SPECIFICATION ; ­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­ LDR PC, =start LDR PC, Undefined_Handler LDR PC, SWI_Handler LDR PC, Prefetch_Handler LDR , . ; ; ; ; ; DCD . LDR PC, IRQ_Handler LDR PC, FIQ_Handler , ;­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­ ; Main code ;­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­ start LDR SP=0x4. ; Set the Stack pointer for ; the Supervisor mode LDR R0, JTAG2 ; Load R0 with 0x55400000 LDR R1 , LDR PC, =start which would branch to symbol start where SFR Pin Function Select Register 1 (Refer to
Philips Semiconductors
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AN10255 LDR SPECIFICATION str 2105 LDR 07 LPC210X 2105 LDR Datasheet LPC210
Abstract: remained within the post-irradiation specification limits but the part is considered low dose rate , AN1792.0 January 14, 2013 Application Note 1792 150 LDR BIAS CH1 LDR BIAS CH3 LDR GND CH1 LDR , ) 100 50 LDR BIAS CH2 LDR BIAS CH4 LDR GND CH2 LDR GND CH4 HDR BIAS CH2 HDR BIAS CH4 HDR GND , ) 4 2 0 LDR BIAS CH1 LDR BIAS CH3 LDR GND CH1 LDR GND CH3 HDR BIAS CH1 HDR BIAS CH3 HDR GND CH1 HDR GND CH3 SPEC LIMIT -2 -4 LDR BIAS CH2 LDR BIAS CH4 LDR GND CH2 LDR GND CH4 Intersil
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ISL70417SEH FN7962

AN10254

Abstract: lpc210x ; section Entry ; Defines entry point ; ­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­ LDR PC, =start LDR PC, Undefined_Addr LDR PC, SWI_Addr LDR PC, Prefetch_Addr LDR PC, Abort_Addr , LPC2104/5/6 User Manual. DCD LDR LDR . . PC, [PC, #­0xFF0] PC, FIQ_Addr Undefined_Addr DCD , executed in the application will be LDR PC,=start which will branch to the assembly startup code which , vector of importance would be the IRQ interrupt. LDR PC, [PC, #­0xFF0] This instruction will load the
Philips Semiconductors
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LPC2106 AN10254 philips assembly location 0xe0008000 arm vector table F030 4000001C

5mm ldr

Abstract: LDR 5mm ) 9 FB 10 COMP 11 LDELAY 80 12 LDR , 2.5V LDELAY 2.5V VSW, (Note 8) 893mW (60 ) CSS LDR 140 /W , /jpn/ LM2655 LM2655 ( ) TJ 25 VIN 10V (LDR) TJ 25 VIN , LDR (>1M) LM2655 MOSFET MOSFET MOSEFT (COMP , MOSFET IC LDR IN LDR C C MOSFET V /IC LM2655 CIN MOSFET LM2655
National Semiconductor
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TSSOP-16 LM2653 MTC16 LM2655MTC-ADJ 5mm ldr LDR 5mm LDR 04 300khz mosfet driver IC Circuit diagram of LDR reference table n mosfet DS101284-04-JP 24VVADJ LMV431

smt LDR

Abstract: specification of ldr Power Inductors(SMT Type) LDR SERIES (SMT Power Inductors without Shiele) F H E A , 0.8 4.9 4.7 1.3 7.5 Specification for LDR3011 Series Inductance Test Frequency , : +886-2-22254982 E-mail: sales@empro.com.tw FAX : +886-2-22254984 http:// www.empro.com.tw LDR SERIES Power Inductors(SMT Type) Specification for LDR3511 Series Inductance Test Frequency. DCR at 25 , 100KHz/0.1V 20.5 0.05 Part Number Marking Specification for LDR4311 Series Part Number
Empro Technology
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smt LDR EMPRO ldr 12mm LDR4311-XXXX LDR5411-XXXX LDR3011-XXXX LDR3511-XXXX 100KH LDR5411

ARMv5

Abstract: 0044D this specification or report a defect in it Please check the ARM Information Center (http , defects in this specification to arm dot eabi at arm dot com. Licence THE TERMS OF YOUR ROYALTY FREE LIMITED LICENCE TO USE THIS ABI SPECIFICATION ARE GIVEN IN SECTION 1.4, Your licence to use this specification (ARM contract reference LEC-ELA-00081 V2.0). PLEASE READ THEM CAREFULLY. BY DOWNLOADING OR OTHERWISE USING THIS SPECIFICATION, YOU AGREE TO BE BOUND BY ALL OF ITS TERMS. IF YOU DO NOT AGREE TO THIS
ARM
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0044D ARM926EJ-S ARM946E-S ARM1136J-S ARM1156T2F-S ARMv5 LEB128 ARM v7 ESPC iar arm inline assembly code ARM1176

NORPS-12 LDR

Abstract: . ISL71091SEH TOTAL DOSE TEST ATTRIBUTES DATA PART DOSE RATE (Note 1) BIAS SAMPLE SIZE LDR , Anneal ISL70419SEH LDR Grounded 12 Anneal Submit Document Feedback 2 AN1949 , -883 TM1019; the actual dose rate for these tests was 65 rad(Si)/s. LDR indicates low dose rate (0.01 rad(Si , passed the 129.5 dB SMD limit at all downpoints. 150 LDR BIAS CH1 SPEC LIMIT LDR BIAS CH2 100 LDR BIAS CH3 INPUT OFFSET VOLTAGE (ÂuV) POST 450k HDR ANNEAL LDR BIAS CH4 LDR GND CH1 50
Intersil
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NORPS-12 LDR

specification of ldr

Abstract: LDR SPECIFICATION !, {R4-R8} ; save APCS register variables on the stack LDR R1, =(IC_ON + DC_ON + WB_ON) AND R0, R0 , stack LDR R0, =Level1tab WRCP15_TTBase R0 LDR R0, =1 WRCP15_DAControl R0 ;TTB address is 2*14 , all TT entries - FAULT ; LDR R0, =0 ; loop count LDR R1, =Level1tab LDR R2, =0 LDR R3 , TTCLRLoop ; increment loop count ; ;Configure DRAM section accesses ; LDR R1, =Level1tab LDR R2, =DRAM_SIZE LDR R3, =0 ;loop count DRAMLoop LDR ADD STR ADD CMP BNE R0, =DRAM_BASE + DRAM_ACCESS
Digital Equipment
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CP15 EBSA-110 21285-aa 21285AA SA-110 21A85 SA-110/21285

ldr 3 pin metal package

Abstract: sensitivity of ldr (LDR) and high dose rate (HDR) total ionizing dose (TID) test results, drift calculations and an , fail at a low dose rate (LDR) that is closer to the dose rate seen in a space application [1]. , outlined in MIL-STD-883, TM1019 [5]. Testing under LDR conditions was not routine, due to the time , applications. It had been proposed that it might be possible to simulate LDR response by irradiating products , margin of two for the parametric drift to qualify bipolar products for LDR environments [8]. This dose
National Semiconductor
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ldr 3 pin metal package LDR resistor 5662-0050101QXA JMX046X24 LDR positive NSC LDR LM136-2

TDC1023

Abstract: 2023N7C SPECIFICATION LDR = HIGH TS = LOW BIN = REFERENCE T REGISTER PRELOADED tPWH tPWL CLK A CLK S , shifted into the B register. Bringing LDR HIGH parallel loads the data into the R reference latch. This , 1 LATCH TFLG 7 LDR R1 R2 R64 BIN T REG CLK T CLK B TS B1 B2 , TMC2023 PRODUCT SPECIFICATION Description (cont.) Applications (cont.) place between the A , register and R latch. When LDR goes HIGH, the contents of register B are copied into the R latch. With
Fairchild Semiconductor
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TDC1023 TMC2023C3V1 2023N7C tmc2023j7v TMC2023N2C TMC2023N7C TMC2023J7V3 TMC2023R3C3 2023R3C3 TMC2023C3V 2023C3V

LM2655

Abstract: LM2655MTC-ADJ LDR Voltage Junction Temperature Range -40°C TJ +125°C Power Dissipation (TA =25°C), (Note , Hysteresis Temperature Typical (Note 6) Limit (Note 5) 25 Units °C Low-side Driver (LDR , Level 0 ISINK LDR Sink Current LDR Voltage = 1V 500 mA ISOURCE LDR Source Current LDR Voltage = 2V 180 mA TRR Rise Time CGS=1000pF 18 ns TF Fall Time , susceptibility using the human body model is 500V for VCB, VSW, LDR, and LDELAY. Note 5: Typical numbers are at
National Semiconductor
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LM2655MTCX-ADJ specification of ldr resistor CSP-9-111C2 CSP-9-111S2

S3C2443

Abstract: LDR SPECIFICATION Specification for detail information. 1.2.2 Sample code ; 1st Wait200us MOV r0,#0x10000 1 SUBS r0,r0,#1 BNE %b1 ; 2nd Set SDR Memory parameter control registers ldr r0,=MEMDATA ldr r1,=BANKCFG ; add r2, r0, #16 ldr r3, [r0], #4 str r3, [r1], #4 cmp r2, r0 bne , ; 3rd Issue a PALL command ldr ldr r1,[r2] bic r1,r1,#(0x3
Samsung Electronics
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S3C2443X S3C2443 samsung K4 ddr samsung confidential s3c2443 datasheet 0x80000033
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