LC865032A LC865032A/28A/24A 3071-DIP64S DIP64S 3159-QFP64E LC865028A LC865024A - Datasheet Archive

 

LC865032A, 865028A, 865024A CMOS LSI LC865032A, 865028A, 865024A 8-Bit Single-Chip Microcontroller Overview Package Dimensions

 

Ordering number: EN 5633 LC865032A LC865032A, 865028A, 865024A CMOS LSI LC865032A LC865032A, 865028A, 865024A 8-Bit Single-Chip Microcontroller Overview Package Dimensions The LC865032A/28A/24A LC865032A/28A/24A microcontrollers are 8-bit singlechip microcontrollers with the following on-chip functional blocks : · CPU : Operable at a minimum bus cycle time of 0.5 µs (microsecond) · On-chip ROM capacity : Up to 32K bytes · On-chip RAM capacity : 512 bytes (LC865032A/28A/24A LC865032A/28A/24A) · 16-bit timer/counter (or two 8-bit timers) · 16-bit timer/PWM (or two 8-bit timers) · 8-channel × 8-bit A/D converter · Two 8-bit synchronous serial-interface circuits · 13-source 10-vectored interrupt system All of the functions above are fabricated on a single chip. 3071-DIP64S 3071-DIP64S unit : mm [LC865032A/28A/24A LC865032A/28A/24A] 0.25 16.8 33 19.5 64 32 5.0max 1 0.51min 3.2 4.0 57.2 0.95 0.48 1.78 1.01 SANYO : DIP64S DIP64S unit : mm 3159-QFP64E 3159-QFP64E [LC865032A/28A/24A LC865032A/28A/24A] 17.2 1.6 14.0 1.6 1.0 Features 0.15 33 0.8 64 17 16 1 0.8 0.35 3.0max : bits bits bits 49 17.2 14.0 1.0 32 1.0 (1) Read-Only Memory (ROM) LC865032A LC865032A 32512 × 8 LC865028A LC865028A 28672 × 8 LC865024A LC865024A 24576 × 8 1.0 48 15.6 0.8 0.1 2.7 SANYO : QFP64E QFP64E (2) Random Access Memory (RAM) : LC865032A/28A/24A LC865032A/28A/24A 512 × 8 bits SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN 33098HA 33098HA (II) No. 5633-1/20 LC865032A LC865032A, 865028A, 865024A (3) Bus cycle time / Instruction cycle time The LC865032A/28A/24A LC865032A/28A/24A microcontrollers are constructed to read ROM twice within one instruction cycle. This results in 1.7 times better performance within the same instruction cycle compared to our 4-bit microcontrollers (the LC66000 LC66000 series). Bus cycle time indicates the speed to read ROM. Bus cycle time Cycle time System clock oscillation Oscillation frequency Supply voltage 0.5 µs 1 µs Ceramic resonator 12 MHz 4.5 to 6.0V 2 µs 4 µs Ceramic resonator 3 MHz 2.7 to 6.0V 7.5 µs 15 µs RC oscillator 800 kHz 2.7 to 6.0V 183 µs 366 µs Crystal oscillator 32.768 kHz 2.7 to 6.0V (4) Ports - Input/output ports : 6 ports (42 pins) Input/output port programmable in nibble units : 1 port (8 pins) (However, when N-channel open-drain output is selected, bit-unit input is possible.) Input/output port each bit programmable : 5 ports (34 pins) Include 15 V withstand N-channel open drain output port : 3 ports (18 pins) - Input ports : 2 ports (13 pins) (5) A/D converter - 8-channel × 8-bit A/D converter (6) Serial-interface - Two 8-bit serial-interface circuits LSB first / MSB first functions switchable - Internal 8-bit band-rate generator in common with two serial-interface circuits (7) Timer - Timer 0 16-bit timer/counter 2-bit prescaler + 8-bit programmable prescaler Mode 0 : Two 8-bit timers with programmable prescaler Mode 1 : 8-bit timer with programmable prescaler + 8-bit counter Mode 2 : 16-bit timer with programmable prescaler Mode 3 : 16-bit counter The resolution of Timer is fixed to tCYC. (tCYC : cycle time) - Timer 1 16-bit timer/PWM Mode 0 : Two 8-bit timers Mode 1 : 8-bit timer + 8-bit PWM Mode 2 : 16-bit timer Mode 3 : Variable-bit PWM (9 to 16 bits) In Mode 0 and Mode1, the resolution of Timer and PWM is fixed to tCYC. In Mode 2 and Mode 3, the resolution of Timer and PWM can be programmed to be tCYC or 1/2 tCYC - Base timer Every 500 ms overflow system for clock applications (using 32.768 kHz crystal oscillator for Base timer clock) Every 976 µs, 3.9 ms, 15.6 ms, 62.5 ms overflow system (using 32.768 kHz crystal oscillator for Base timer clock) - Base timer clock selectable 32.768 kHz crystal oscillator, system clock, and programmable prescaler output of Timer 0 No. 5633-2/20 LC865032A LC865032A, 865028A, 865024A (8) Buzzer output - The buzzer sound frequency is selectable ; 4 kHz, 2 kHz (using 32.768 kHz crystal oscillator for base timer clock) (9) Remote-controlled receiver circuit (shares P73/INT3/T0IN P73/INT3/T0IN pin) - Noise rejection function - Polarity switching (10) Watchdog timer - RC external watchdog timer - Watchdog timer operation can be selected : Interrupt/reset (11) Interrupt system - 13-source 10-vectored interrupts : 1. External interrupt INT0 (including watchdog timer) 2. External interrupt INT1 3. External interrupt INT2, Timer/counter T0L (lower 8 bits) 4. External interrupt INT3, base timer 5. Timer/counter T0H (upper 8-bits) 6. Timer T1L, timer T1H 7. Serial-interface SIO0 8. Serial-interface SIO1 9. A/D converter 10. Port 0 - Built-in interrupt priority control register Microcontroller supports 3 levels of multiple interrupt; low level, high level, and highest level. For the 11 interrupt requests from INT2 through Port 0, high/low level interrupt priority can be specified using the priority control register. Also, for INT0 and INT1, highest/low level interrupt priority can be specified. (12) Real-time service operation Synchronizing with the interrupt request signals, the real-time service starts a 4-byte data transfer between which special function registers within 1-instruction cycle after the request signal occurs, and then completes its operation within 5-instruction cycles. This operation is performed in parallel with CPU operation. (13) Subroutine stack - 128 levels (Max.) : The stack is located in RAM. (14) Multiplication and division 16 bits × 8 bits (7-instruction cycles) 16 bits / 8 bits (7-instruction cycles) (15) 3 oscillation circuits - On-chip RC oscillator circuit for the system clock - On-chip CF oscillator circuit for the system clock - On-chip crystal oscillator circuit for the system clock and the time-base clock XT1 pin can be used as P74. No. 5633-3/20 LC865032A LC865032A, 865028A, 865024A (16) Standby function - HALT mode HALT mode is used to reduce power dissipation. In this mode, program execution is stopped. This mode can be released by an interrupt request signal or initial system reset request signal. - HOLD mode The HOLD mode is used to stop all oscillators RC (internal), CR and Crystal. This mode can be released by the following operations · Set Low level to Reset pin (RES). · Set predefined level to P70/INT0 P70/INT0, P71/INT1 P71/INT1 pins (programmable). · Set Low level to Port 0 pin/pins (programmable). (17) Factory shipment · DIP64S DIP64S , QFP64E QFP64E delivery form (18) Development support tools Evaluation (EVA) chip : EPROM version : One time ROM version : Emulator : LC866098 LC866098 LC86E5032 LC86E5032 LC86P5032 LC86P5032 EVA-86000 EVA-86000 + ECB866600 ECB866600 (Evaluation chip board) + POD865000 POD865000 (POD for DIP64S DIP64S) + POD865010 POD865010 (POD for QFP64E QFP64E) No. 5633-4/20 LC865032A LC865032A, 865028A, 865024A Pin Assignments DIP64S DIP64S 64 63 47 46 45 19 20 21 VSS P51 P50 P47 P46 P45 P44 P43 P42 P41 P40 P37 P36 P35 P34 P06 P10/SO0 P10/SO0 P07 P11/SI0/SB0 P11/SI0/SB0 P13/SO1 P13/SO1 P12/SCK0 P12/SCK0 P14/SI1/SB1 P14/SI1/SB1 Top view 48 P03 44 43 42 41 40 39 38 37 36 35 34 33 22 23 24 25 26 27 28 29 30 31 32 P16/BUZ P16/BUZ P15/SCK1 P15/SCK1 P27 P26 P25 P24 P23 P22 P21 P20 VDDVPP P00 15 16 17 18 P17/PWM P17/PWM P06 P05 P04 P03 P02 P01 P00 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 9 10 11 12 13 14 QFP64E QFP64E P07 P02 P01 1 2 3 4 5 6 7 8 P05 P04 P10/SO0 P10/SO0 P11/SI0/SB0 P11/SI0/SB0 P12/SCK0 P12/SCK0 P13/SO1 P13/SO1 P14/SI1/SB1 P14/SI1/SB1 P15/SCK1 P15/SCK1 P16/BUZ P16/BUZ P17/PWM P17/PWM TEST1 RES XT1/P74 XT1/P74 XT2 VSS CF1 CF2 VDD P80/AN0 P80/AN0 P81/AN1 P81/AN1 P82/AN2 P82/AN2 P83/AN3 P83/AN3 P84/AN4 P84/AN4 P85/AN5 P85/AN5 P86/AN6 P86/AN6 P87/AN7 P87/AN7 P70/INT0 P70/INT0 P71/INT1 P71/INT1 P72/INT2/T0IN P72/INT2/T0IN P73/INT3/T0IN P73/INT3/T0IN P30 P31 P32 P33 34 33 36 35 39 38 37 42 41 40 53 54 28 P23 P22 55 56 26 25 57 24 P82/AN2 P82/AN2 58 59 23 22 P83/AN3 P83/AN3 60 21 P51 P50 P84/AN4 P84/AN4 P85/AN5 P85/AN5 61 62 20 P47 P46 P86/AN6 P86/AN6 63 19 18 17 P44 43 P25 44 P26 30 29 RES 46 45 P27 31 49 47 32 TEST1 50 51 XT1/P74 XT1/P74 XT2 52 11 12 13 P40 P41 14 15 10 P36 P87/AN7 P87/AN7 P35 9 8 1 P81/AN1 P81/AN1 6 7 VDD P80/AN0 P80/AN0 5 CF2 P24 27 4 CF1 2 3 VSS P20 VDDVPP VSS P45 P43 P42 P37 P33 P34 P32 P31 P30 P72/INT2/T0IN P72/INT2/T0IN P73/INT3/T0IN P73/INT3/T0IN P71/INT1 P71/INT1 P70/INT0 P70/INT0 16 64 P21 Top view No. 5633-5/20 LC865032A LC865032A, 865028A, 865024A System Block Diagram IR Interrupt control PLA ROM Stand-by control CF RC Bus PC Clock generator X tal ACC Base timer Bus interface B register SIO0 Port1 C register SIO1 Port7 Timer 0 Port8 Timer 1 Port2 ALU Bus ADC Port3 INT0 to INT3 Noise rejection filter Port4 Real-time service PSW Port5 RAR RAM RAM (128 bytes) Stack pointer PORT 0 Watchdog timer No. 5633-6/20 LC865032A LC865032A, 865028A, 865024A Pin Description Pin name I/O Function description VSS VDD Power supply (+) VDDVPP* Option Power supply (­) Power supply (+) PORT0 P00 to P07 I/O · · · · 8-bit input/output port Input for port 0 interrupt Data direction programmable in nibble units Input for HOLD release · Pull-up resistor : Present / Not present · Output form : CMOS/N-channel open-drain PORT1 P10 to P17 I/O · 8-bit input/output port · Data direction can be specified for each bit. · Other pin functions P10 SIO0 data output P11 SIO0 data input /bus input/output P12 SIO0 clock input/output P13 SIO1 data output P14 SIO1 data input /bus input/output P15 SIO1 clock input/output P16 Buzzer output P17 Timer1 output (PWM output) · Output form : CMOS/N-channel open-drain PORT2 P20 to P27 I/O · 8-bit input/output port · Input/output in bit units Output form : CMOS/N-channel open-drain PORT3 P30 to P37 I/O · 8-bit input/output port · Input/output in bit units · 15 V withstand at N-channel open-drain output · Pull-up resistor : Present / Not present · Output form : CMOS/N-channel open-drain PORT4 P40 to P47 I/O · 8-bit input/output port · Input/output in bit units · 15 V withstand at N-channel open-drain output · Pull-up resistor : Present / Not present · Output form : CMOS/N-channel open-drain PORT5 P50 , P51 I/O · 2-bit input/output port · Input/output in bit units · 15 V withstand at N-channel open-drain output · Pull-up resistor : Present / Not present · Output form : CMOS/N-channel open-drain * Connect as in the following figure to reduce noise into VDD. Short-circuit the VDD terminal to the VDDVPP pin. Short-circuit the two VSS pins. VDD Power supply VDDVPP VSS VSS No. 5633-7/20 LC865032A LC865032A, 865028A, 865024A Pin name I/O PORT7 P70 I/O P71 to P74 I Function description Option · 5-bit input port · Other pin functions P70: INT0 input / HOLD release / N-channel Tr. output for watchdog timer P71: INT1 input / HOLD release input P72: INT2 input / timer 0 event input P73: INT3 input with noise filter/timer 0 event input P74: XT1 input pin for 32.768 kHz crystal oscillator · Interrupt received form, vector address Rising Falling Rising & falling High level Low level Pull-up resistor : Present / Not present (P70,71,72,73) * P74 does not have pull-up resistor option. Vector INT0 Enable Enable Disable Enable Enable 03H INT1 Enable Enable Disable Enable Enable 0BH INT2 Enable Enable Enable Disable Disable 13H INT3 Enable Enable Enable Disable Disable 1BH PORT8 P80 to P87 I · 8-bit input port · Other function A/D input port (8 port pins) RES I Reset pin with pull-up resistor TEST1 O · Test pin Should be left open. · Output fixed HIGH XT1/P74 XT1/P74 I · Input pin for 32.768 kHz crystal oscillator · Other function Input port P74 When not in use, connect to VDD. XT2 O Output pin for 32.768 kHz crystal oscillator When not in use, should be left open. CF1 I Input pin for ceramic resonator oscillator CF2 O Output pin for ceramic resonator oscillator · All port options can be specified for each bit. · State of pins at reset Pin name Input/output mode State of pull-up resistor specified at pull-up option Port 0 P70, 71, 72, 73 Input Fixed pull-up resistor exist Ports 1, 2 Ports 3, 4, 5 Input Programmable pull-up resistor OFF No. 5633-8/20 LC865032A LC865032A, 865028A, 865024A Specifications 1. Absolute Maximum Ratings at Ta = 25°C , VSS = 0 V Parameter Symbol Pins Conditions Ratings VDD [V] Supply voltage VDD max VDD, VDDVPP Input voltage VI(1) Input/output voltage typ Unit max +7.0 · P71, 72, 73, 74 · Port 8 · RES ­0.3 VDD +0.3 VIO(1) · Ports 0, 1, 2 · Ports 3, 4, 5 at CMOS output option ­0.3 VDD +0.3 P 3, 4, 5 at N-ch open-drain output option ­0.3 +15 Peak output current I OPH(1) Ports 0, 1, 2, 3, 4, 5 CMOS output at each pin ­4 Total output current I OAH (1) Ports 0, 1 Total of all pins ­20 I OAH (2) Ports 2, 3, 4, 5 Total of all pins ­20 Peak output current I OPL(1) Ports 0, 1, 2, 3, 4, 5 At each pin 20 I OPL(2) P70 At each pin 15 Total output current I OAL (1) Port 0 P70 Total of all pins 40 I OAL (2) Port 2 Total of all pins 40 I Lowlevel output current ­0.3 VIO(2) Highlevel output current VDD = VDDVPP min OAL (3) V mA Ports 3, 4, 5 Total of all pins 80 Power dissipation (max.) Pd max (1) DIP64S DIP64S Ta = ­30 to +70°C 700 Pd max (2) QFP64E QFP64E Ta = ­30 to +70°C 420 Operating temperature range Topr ­30 +70 Storage temperature range Tstg ­65 +150 mW °C No. 5633-9/20 LC865032A LC865032A, 865028A, 865024A 2. Recommended Operating Ranges at Ta = ­30°C to +70°C, VSS = 0 V Parameter Symbol Pins Conditions Ratings VDD[V] Operating voltage range VDD(1) VDD min typ Unit max 0.98 µs tCYC tCYC 400 µs 4.5 6.0 3.9 µs tCYC tCYC 400 µs 2.7 6.0 VDD RAM and Registers hold voltage at HOLD mode. 2.0 6.0 VDD(2) HOLD voltage VHD Input high-level voltage VIH (1) Port 0 (Schmitt) Output disable 2.7 to 6.0 0.4VDD +0.9 VDD VIH (2) · Ports 1, 2 · P72, 73 (Schmitt) Output disable 2.7 to 6.0 0.75VDD 75VDD VDD VIH (3) · P70 Port input/interrupt · P71 · RES (Schmitt) Output N-channel transistor OFF 2.7 to 6.0 0.75VDD 75VDD VDD VIH (4) P70 Watchdog timer Output N-channel transistor OFF 2.7 to 6.0 0.9VDD VDD VIH (5) · P74 · Port 8 Output N-channel transistor OFF 27 to 6.0 0.75VDD 75VDD VDD VIH (6) Ports 3, 4, 5 of CMOS output (Schmitt) Output disable 4.0 to 6.0 0.75VDD 75VDD VDD 2.7 to 4.0 0.8VDD VDD Ports 3, 4, 5 of opendrain output (Schmitt) Output disable 4.0 to 6.0 0.75VDD 75VDD 13.5 2.7 to 4.0 0.8VDD 13.5 VIL (1) Port 0 (Schmitt) Output disable 2.7 to 6.0 VSS 0.2VDD VIL (2) · Ports 1, 2, 3, 4, 5 · P72, 73 (Schmitt) Output disable 2.7 to 6.0 VSS 0.25V DD VIL (3) · P70 Port input/interrupt · P71 · RES (Schmitt) N-channel transistor OFF 2.7 to 6.0 VSS 0.25V DD VIL (4) P70 Watchdog timer N-channel transistor OFF 2.7 to 6.0 VSS 0.8V DD ­1.0 VIL (5) · P74 · Port 8 Output N-channel transistor OFF 2.7 to 6.0 VSS 0.25V DD 4.5 to 6.0 2.7 to 6.0 0.98 3.9 400 400 V VIH (7) Input low-level voltage Operating cycle time tCYC µs No. 5633-10/20 LC865032A LC865032A, 865028A, 865024A Parameter Symbol Pins Conditions Ratings VDD [V] Oscillation frequency range (Note 1) min typ Unit max FmCF(1) CF1, CF2 · 12 MHz (ceramic 4.5 to 6.0 resonator oscillation). · Refer to Figure 1. 11.76 12 12.24 FmCF(2) CF1, CF2 · 3 MHz (ceramic 2.7 to 6.0 resonator oscillation). · Refer to Figure 1. 2.94 3 3.06 0.8 3.0 FsXtal XT1, XT2 · 32.768 kHz (crystal oscillation). · Refer to Figure 2. 2.7 to 6.0 32.768 tmsCF(1) CF1, CF2 · 12 MHz (ceramic 4.5 to 6.0 resonator oscillation). · Refer to Figure 3. 0.03 0.5 tmsCF(2) CF1, CF2 · 3 MHz (ceramic 4.5 to 6.0 resonator oscillation). · Refer to Figure 3. 2.7 to 6.0 0.2 2 0.2 6 4.5 to 6.0 1 1.5 2.7 to 6.0 1 3 FmRC Oscillation stable time period (Note 1) tssXtal RC oscillation XT1, XT2 · 32.768 kHz (crystal oscillation). · Refer to Figure 3. 2.7 to 6.0 0.4 MHz kHz ms s (Note 1) Refer to Table 1 and Table 2 for oscillation constant. No. 5633-11/20 LC865032A LC865032A, 865028A, 865024A 3. Electrical Characteristics at Ta = ­30°C to +70°C , VSS = 0 V Parameter Symbol Pins Conditions Ratings VDD [V] Input high-level current min typ Unit max Ports 3, 4, 5 of opendrain output · Output disabled · VIN = 13.5 V (including off-state leak current of the output transistor) 2.7 to 6.0 5 I IH(2) · Port 0 without pull-up MOS transistor · Ports 1, 2, 3, 4, 5 · Output disabled · Pull-up MOS transistor OFF. VIN = V DD (including off-state leak current of the output transistor) 2.7 to 6.0 1 I IH(3) · P70, 71, 72, 73 without pull-up MOS transistor · Port 8 VIN = V DD 2.7 to 6.0 1 I IH(4) RES VIN = V DD 2.7 to 6.0 1 I IL (1) · Ports 1, 2, 3, 4, 5 · Port 0 without pull-up MOS transistor · Output disabled · Pull-up MOS transistor OFF. VIN = V SS (including off-state leak current of the output transistor) 2.7 to 6.0 ­1 I IL (2) · P70, 71, 72, 73 without pull-up MOS transistor · Port 8 VIN = V SS 2.7 to 6.0 ­1 I IL (3) RES VIN = V SS 2.7 to 6.0 ­1 Ports 1, 2, 3, 4, 5 of CMOS output IOH = ­1 mA 4.5 to 6.0 VDD­1 IOH = ­0.1 mA 2.7 to 6.0 VDD ­0.5 Ports 1, 2, 3, 4, 5 IOL = 10 mA 4.5 to 6.0 1.5 VOL(2) IOL = 1.6 mA 4.5 to 6.0 0.4 VOL(3) Input low-level current I IH(1) · IOL = 1.0 mA · The current of any unmeasured pin is 1 mA or less. 2.7 to 6.0 0.4 P70 IOL = 1 mA 4.5 to 6.0 0.4 Output high-level voltage VOH(1) Output low-level voltage VOL(1) VOH(2) VOL(4) VOL(5) µA V IOL = 0.5 mA 2.7 to 6.0 Pull-up MOS transistor resistor Rpu · Ports 1, 2, 3, 4, 5 · P70, 71, 72, 73 VOH = 0.9 VDD 4.5 to 6.0 2.7 to 4.5 Hysteresis voltage VHIS · Ports 1, 2, 3, 4, 5 · P70, 71, 72, 73 · RES Output disable 2.7 to 6.0 0.1VDD V All pins · f = 1 MHz Unmeasured input pins are set to VSS level. · Ta = 25°C 2.7 to 6.0 10 pF Pin capacitance CP 0.4 15 25 40 70 70 150 k No. 5633-12/20 LC865032A LC865032A, 865028A, 865024A 4. Serial Input/Output Characteristics at Ta = ­30°C to +70°C, VSS = 0 V Parameter Symbol Pins Conditions Ratings VDD [V] min 2.7 to 6.0 Input clock Output clock Lowlevel pulse width tCKL(1) 2.7 to 6.0 Highlevel pulse width tCKH(1) 2.7 to 6.0 1 tCKCY(2) 2.7 to 6.0 2 Lowlevel pulse width tCKL(2) tCKH(2) max 1 Cycle Serial clock Serial input tCKCY(1) Highlevel pulse width Serial output Unit 2 Cycle typ SCK0, SCK1 SCK0, SCK1 Refer to Figure 5. · Use an external pull-up resistor (1 k ) with opendrain output. tCYC 2.7 to 6.0 1/2tCKCY 2.7 to 6.0 1/2tCKCY · Refer to Figure 5. Data setup time tICK Data hold time tCKI Output delay time (Serial clock is extrnal clock.) tCKO(1) Output delay time (Serial clock is internal clock.) tCKO(2) · SI0, SI1 · SB0, SB1 4.5 to 6.0 2.7 to 6.0 0.1 0.4 · Refer to Figure 5. · SO0, SO1 · SB0, SB1 · Set to the rise of SCK0, SCK1. µs 4.5 to 6.0 2.7 to 6.0 0.1 0.4 · Use an external pull-up resistor (1 k ) with opendrain output. 4.5 to 6.0 7/12tCYC +0.2 2.7 to 6.0 7/12tCYC +1 · Set to the fall of SCK0, SCK1. · Refer to Figure 5. 4.5 to 6.0 1/3tCYC +0.2 2.7 to 6.0 1/3tCYC +1 No. 5633-13/20 LC865032A LC865032A, 865028A, 865024A 5. Pulse Input Conditions at Ta = ­30°C to +70°C , VSS = 0 V Parameter Symbol Pins Conditions Ratings VDD [V] High/low-level pulse width min tPIH(1) tPIL(1) · INT0, INT1 · INT2/T0IN · INT3 · Interrupt acceptable · Timer/counter 0 pulse countable 2.7 to 6.0 INT3/T0IN (Noise rejection filter time constant is 1/1.) Interrupt acceptable 2.7 to 6.0 2 tPIH(3) tPIL(3) INT3/T0IN (Noise rejection filter time constant is 1/16.) Interrupt acceptable 2.7 to 6.0 32 tPIL(4) RES Reset acceptable 2.7 to 6.0 Unit max 1 tPIH(2) tPIL(2) typ tCYC 200 µs 6. A/D Converter Characteristics at Ta = ­30°C to +70°C , VSS = 0 V Parameter Symbol Pins Conditions Ratings VDD [V] Resolution N Absolute precision 4.5 to 6.0 ET min 4.5 to 6.0 typ Unit max 8 bit ±1.5 LSB (Note 2) Conversion time tCAD A/D conversion time = 16 × tCYC (ADCR2 = 0) (Note 3) 4.5 to 6.0 15.68 (tCYC = 0.98 µs) 65.28 (tCYC = 4.08 µs) 31.36 (tCYC = 0.98 µs) 130.56 (tCYC = 4.08 µs) 4.5 to 6.0 VSS VDD V 4.5 to 6.0 4.5 to 6.0 +1 µA ­1 A/D conversion time = 32 × tCYC (ADCR2 = 1) (Note 3) Analog input voltage range VAIN Analog port input current IAINH IAINL (Note 2) (Note 3) AN0 to AN7 VAIN = VDD VAIN = VSS µs Quantizing error (±1/2 LSB) is not included. Conversion time is the period from execution of instruction starting the conversion to completion of shifting the A/D converted value to the register. No. 5633-14/20 LC865032A LC865032A, 865028A, 865024A 7. Current Drain Characteristics at Ta = ­30°C to +70°C, VSS = 0 V Parameter Symbol Current drain during basic operation (Note 4) IDDOP(1) Pins Conditions Ratings VDD [V] IDDOP(2) IDDOP(3) IDDOP(4) IDDOP(5) IDDOP(6) IDDOP(7) VDD min typ Unit max · FmCF = 12 MHz 4.5 to 6.0 for ceramic resonator oscillation. · FsXtal = 32.768 kHz for crystal oscillator. · System clock : CF oscillator · Internal RC oscillator stopped. 10 20 · FmCF = 3 MHz 4.5 to 6.0 for ceramic resonator oscillation. · FsXtal = 32.768 kHz for crystal oscillator. · System clock : CF oscillator · Internal RC oscillator stopped. 2.7 to 4.5 3 7 1.5 5 4.5 to 6.0 0.7 3.0 2.7 to 4.5 0.4 2.5 4.5 to 6.0 35 100 2.7 to 4.5 15 50 · FmCF = 0 Hz (when oscillator stops). · FsXtal = 32.768 kHz for crystal oscillator. · System clock : RC oscillator · FmCF = 0 Hz (when oscillator stops). · FsXtal = 32.768 kHz for crystal oscillator. · System clock : 32.768 kHz · Internal RC oscillator stopped. mA µA No. 5633-15/20 LC865032A LC865032A, 865028A, 865024A Parameter Symbol Pins Conditions Ratings VDD [V] Current drain at HALT mode (Note 4) I DDHALT (1) VDD I DDHALT (3) I DDHALT (4) · HALT mode 4.5 to 6.0 · FmCF = 12 MHz for ceramic resonator oscillation. · FsXtal = 32.768 kHz for crystal oscillatior. · System clock : CF oscillator. · Internal RC oscillator stopped. 5 10 2.2 4.6 0.8 2.5 I DDHALT (7) VDD 4.5 to 6.0 400 1000 2.7 to 4.5 200 4.5 to 6.0 25 100 2.7 to 4.5 8 40 HOLD mode 4.5 to 6.0 0.05 30 2.7 to 4.5 0.02 mA 750 · HALT mode FmCF = 0 Hz (when oscillator stops). · FsXtal = 32.768 kHz for crystal oscillator. · System clock : 32.768 kHz · Internal RC oscillator stopped. I DDHALT (6) I DDHOLD(2) Unit max · HALT mode FmCF = 0 Hz (when oscillator stops). · FsXtal = 32.768 kHz for crystal oscillator. · System clock : RC oscillator I DDHALT (5) I DDHOLD(1) typ · HALT mode 4.5 to 6.0 FmCF = 3 MHz for ceramic resonator oscillation. · FsXtal = 32.768 kHz for crystal oscillator. · System clock : CF oscillator. · Internal RC oscillator stopped. 2.7 to 4.5 I DDHALT (2) Current drain at HOLD mode min µA 20 (Note 4) (Note 4) The currents to output transistors and pull-up MOS transistors are ignored. No. 5633-16/20 LC865032A LC865032A, 865028A, 865024A Oscillation type Supplier Oscillator C1 C2 12 MHz ceramic resonator oscillation Murata CSA12 CSA12.0MTZ 33 pF 33 pF CST12 CST12.0MTW Kyocera 3 MHz ceramic resonator oscillation On chip KBR-12 KBR-12.0M CSA3.00MG040 00MG040 Murata 33 pF 100 pF CST3.00MGW040 00MGW040 Kyocera 33 pF 100 pF On chip KBR-3.0MS 47 pF 47 pF * K rank (±10%) and SL characteristics must be used for C1 and C2. Table 1. Ceramic Resonator Oscillation Guaranteed Constants (Main clock) Oscillation type Supplier C3 C4 Kyocera 32.768 kHz crystal oscillation Oscillator KF-38G-13P0200 KF-38G-13P0200 18 pF 18 pF * J rank (±5%) and CH characteristics must be used for C3 and C4. (For applications which do not need high precision, use K rank (±10%) and SL characteristics.) Table 2. Crystal Oscillation Guaranteed Constants (Sub-clock) Notes · Since the circuit pattern affects the oscillation frequency, place the oscillation-related parts as close to the oscillator pins as possible with the shortest pattern length. · If other oscillators are used, we provide no guarantee for the characteristics. CF1 C1 XT1 CF2 CF C2 Main-clock circuit Figure 1 Ceramic Resonator Oscillator C3 XT2 X tal C4 Sub-clock circuit Figure 2 Crystal Oscillator No. 5633-17/20 LC865032A LC865032A, 865028A, 865024A VDD VDD lower limit 0V Power supply Reset time RES Internal RC resonator oscillation tmsCF CF1, CF2 tssXtal XT1, XT2 Operation mode Reset Unfixed Instruction execution mode HOLD release signal Valid Internal RC resonator oscillation tmsCF CF1, CF2 tssXtal XT1, XT2 Operation mode Instruction execution mode HOLD Figure 3 Oscillation Stable Time VDD VDD RRES RES CRES (Note) Set the values of RES, RRES so that the (Note) Fix the value of CCRES, RRES that is reset untill 200µs, longer. sure to reset time is 200 µs orafter Power supply has been over inferior limit of supply voltage. Figure 4 Reset Circuit No. 5633-18/20 LC865032A LC865032A, 865028A, 865024A 0.5VDD < AC timing point > VDD tCKCY tCKL tCKH SCK0 SCK1 1k tICK tCKI SI0 SI1 tCKO 50pF SO0,SO1 SB0,SB1 < Test load > < Timing > Figure 5 Serial Input/Output Test Conditions tPIL tPIH Figure 6 Pulse Input Timing Conditions No. 5633-19/20 LC865032A LC865032A, 865028A, 865024A Any and all SANYO products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft's control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. Consult with your SANYO representative nearest you before using any SANYO products described or contained herein in such applications. SANYO assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO products described or contained herein. Specifications of any and all SANYO products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer's products or equipment. SANYO Electric Co., Ltd. strives to supply high-quality high-reliability products. However, any and all semiconductor products fail with some probability. It is possible that these probabilistic failures could give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire, or that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO products(including technical data,services) described or contained herein are controlled under any of applicable local export control laws and regulations, such products must not be exported without obtaining the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written permission of SANYO Electric Co. , Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the SANYO product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only ; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of March, 1998. Specifications and information herein are subject to change without notice. No. 5633-20/20