ENN4246 LC7472M 3045B-MFP24 MFP24 71901TN /7232JN 27VDD1 - Datasheet Archive

 

CMOS IC LC7472M On-Screen Video Display Controller for NTSC or PAL-M Overview Package Dimensions The LC7472M is a CMOS, video

 

Ordering number:ENN4246 ENN4246 CMOS IC LC7472M LC7472M On-Screen Video Display Controller for NTSC or PAL-M Overview Package Dimensions The LC7472M LC7472M is a CMOS, video display controller for superimposing text and low-level graphics onto an NTSC or PAL-M compatible television receiver. Up to 240, 8 × 8pixel characters can be displayed under microprocessor control on a 24-character by 10-line display. The LC7472M LC7472M features selectable pixel width and height, and 64 vertical and 64 horizontal display start positions. It also features a flashing enable bit for each character position. The LC7472M LC7472M operates from a 5 V supply and is available in 24-pin MFP. unit:mm 3045B-MFP24 3045B-MFP24 [LC7472M LC7472M] 24 12 2.15 15.3 2.5max 1 · Complete text and graphics video overlay circuitry. · 64-character internal character generator ROM. · 8 × 8-pixel characters. · Three pixel widths and three pixel heights. · Selectable background color. · Built-in synchronization check and separation circuitry. · Approximately 0.5 or 1 s period character flashing option. · NTSC or PAL-M format compatibility. · 8-bit serial input format. · 5 V supply. · 24-pin MFP. 0.15 0.1 Features 0.75 7.9 9.0 10.5 13 0.35 1.27 0.67 SANYO : MFP24 MFP24 Pin Assignment VSS1 1 24 VDD1 XIN 2 23 RST XOUT 3 22 CTRL3 CTRL1 4 21 CTRL2 CSYNOUT 5 20 SEPIN OSCIN 6 19 SEPOUT OSCOUT 7 18 SEPC SYNC 8 17 SYNIN CS 9 16 VDD1 SCLK 10 15 CVIN SIN 11 14 NC VDD2 12 13 CVOUT LC7472M LC7472M (Top View) Any and all SANYO products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft's control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. Consult with your SANYO representative nearest you before using any SANYO products described or contained herein in such applications. SANYO assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges,or other parameters) listed in products specifications of any and all SANYO products described or contained herein. SANYO Electric Co.,Ltd. Semiconductor Company TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN 71901TN 71901TN (KT)/7232JN /7232JN No.4246­1/11 LC7472M LC7472M Block Diagram No.4246­2/11 LC7472M LC7472M Pin Function Number Name 1 VSS1 Description Ground 2 XIN 3 XOUT Crystal oscillator output 4 CTRL1 Crystal oscillator input select. HIGH for external (2fSC) clock input mode 5 CSYNOUT 6 OSCIN 7 OSCOUT 8 SYNC 9 CS 10 SCLK 11 SIN 12 VDD2 13 CVOUT 14 NC 15 CVIN 16 VDD1 Crystal oscillator input Composite synchronization signal output. During reset (RST LOW), crystal oscillator clock is output. No output for internal reset command LC oscillator input. LC circuit for pixel clock generation character output LC oscillator output. LC circuit for pixel clock generation character output External synchronization signal check output. During reset (RST LOW), pixel clock is output. No output for internal reset command Serial data input enable when LOW, with pull-up resistance Clock input for serial data input, with pull-up resistance Serial data input, with pull-up resistance Power supply for composite video image signal level modulation (for analog system) Composite video image signal output No connection Composite video image signal input 5V power supply for digital system 17 SYNCIN Synchronization separation circuit input. If internal sync separation circuit is not used, use SYNCIN to input an external horizontal or composite synchronization signal 18 SEPC Synchronization separation circuit modulator capacitor connection. Leave open if not used 19 SEPOUT Composite synchronization separation circuit output. Outputs SYNCIN signal if internal sync separation is not used. 20 SEPIN 21 CTRL2 Vertical synchronization signal input. Tie to VDD1 if not used NTSC/PAL-M sync signal generation method select input. LOW for NTSC 22 CTRL3 SEPIN input control. VSYNC input signal when LOW 23 RST System reset input, with pull-up resistance 24 VDD1 5V power supply for digital system Specifications Absolute Maximum Ratings at Ta = 25°C Parameter Symbol Maximum supply voltage VDD max Maximum input voltage VO max Allowable power dissipation Conditions Unit VSS­ 0.3 to VSS+7.0 VSS­ 0.3 to VDD+0.3 V CSYNOUT, SYNCJDG, SEPOUT VSS­ 0.3 to VDD+0.3 VIN max Maximum output voltage Ratings VDD1, VDD2 Pd max 350 V V mW Operating temperature Topr ­ 30 to +70 °C Storage temperature Tstg ­ 40 to +125 °C Reommended Operating Conditions at Ta = ­30 to +70°C Parameter Logic supply voltage Analog supply voltage Symbol Conditions VDD1 VDD2 Ratings min typ Unit max 4.5 5.0 5.5 V 4.5 5.0 1.27VDD1 27VDD1 V VIH1 VIH2 RST, CS, SIN, SCLK 0.8VDD1 VDD1+0.3 V CTRL1, CTRL2, CTRL3, SEPIN 0.7VDD1 VDD1+0.3 V VIL1 RST, CS, SIN, SCLK 0.2VDD1 V VIL2 CTRL1, CTRL2, CTRL3, SEPIN VSS­ 0.3 VSS­ 0.3 Depends on optional settings at pins CVIN composite video input voltage RPU VI1 Measured peak to peak 2.0 SYNCIN composite video input voltage VI2 Measured peak to peak 2.0 XIN input voltage VI3 External clock input, fIN=7.159 or 14.302MHz Input high-level voltage Input low-level voltage RST, CS, SIN and SCLK pull-up resistance XIN and XOUT oscillator frequency fOSC1 OSCIN and OSCOUT oscillator frequency fOSC2 25 0.3VDD1 50 0.20 K 2.5 VP-P VP-P VP-P 5.0 NTSC (2fsc) 7.159 PAL-M (4fsc) 14.302 LC oscillator 5 V 90 MHz MHz 10 MHz No.4246­3/11 LC7472M LC7472M Electrical Characteristics at Ta = ­30 to +70°C, VDD1 = 5V, unless otherwise noted Parameter Symbol Logic supply current IDD1 Analog supply current IDD2 IL1 CVIN input leakage current CVOUT output leakage current CTRL1, CTRL2, CTRL3 and OSCIN LOW-level input current RST, CS, SIN, SCLK, CTRL1, SEPIN, CTR2 and CTR3 HIGH-level input current CSYNOUT, SYNC and SEPOUT LOW-level output voltage CSYNOUT, SYNC and SEPOUT HIGH-level output voltage CVOUT SYNC voltage CVOUT pedestal voltage CVOUT LOW-level color bar strobe voltage CVOUT HIGH-level color bar strobe voltage CVOUT LOW-level background color voltage CVOUT HIGH-level background color voltage CVOUT border voltage CVOUT character voltage Conditions Ratings min typ Unit max All outputs open, 7.159MHz crystal oscillator, 8MHz LC oscillator 15 mA VDD2=5V 20 mA 1 µA 1 µA IL2 IIL VI=VSS1 ­ 1. 0 IIH VI=VDD1 1.0 µA VOL1 VDD1=4.5V, IOL=1.0 mA 1.0 V VOH1 VDD1=4.5V, IOH=­ 1.0 mA VRSL VRSH 3.5 V 0.88 V 1.56 1.68 V 1.27 1.39 V 1.75 1.87 1.99 V 1.59 1.71 1.83 V 2.12 2.24 2.36 V 1.58 1.70 1.82 V 2.74 VBK VCHA 1.12 1.15 VDD2=5.0V 1.00 1.44 VSN VPD VCBL VCBH µA 2.86 2.98 V Timing Characteristics at Ta = ­30 to +70°C, VDD1 = 5±0.5V Parameter SCLK input pulsewidth Symbol Conditions Ratings min ty p max Unit tW(SCLK) tW(CS) 200 ns 1 µs 200 ns SIN data input setup time tSU(CS) tSU(SIN) 200 ns CS input hold time SIN data input hold time 8-bit data word write time RAM data write time tH(CS) tH(SIN) tWORD tWT 2 200 4.2 1 µs ns µs µs CS HIGH-level input pulsewidth CS input setup time No.4246­4/11 LC7472M LC7472M Display Control Features and Characteristics Display Control Command Structure The display control commands, COMMAND0 to COMMAND5, are shifted in 8-bit serial units. The first byte of a command consists of an identification code and data. The second byte consists of data only. Once the command identification code in byte 1 has been written, it is saved until Display Control Command Data the next time the first byte is written. If COMMAND1 is written, the display character write mode begins and the first byte does not change. When CS is HIGH, COMMAND0 is set. First byte Command code Command Second byte Data or register storing data Data or register storing data 7 COMMAND0 Display memory (VRAM) write address setting command COMMAND1 Display character data write command COMMAND2 Vertical display position and character size setting command COMMAND3 Horizontal display position and character size setting command COMMAND4 Display control setting command COMMAND5 Synchronization signal control setting command 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 1 0 0 0 V3 V2 V1 V0 0 0 0 H4 H3 H2 H1 H0 1 0 0 1 0 0 0 0 at 0 C5 C4 C3 C2 C1 C0 1 0 1 0 VS21 VS20 VS11 VS10 0 0 VP5 VP 4 VP 3 VP 2 VP 1 VP0 1 0 1 1 HS21 HS20 HS11 HS10 0 0 HP 5 HP4 HP3 HP 2 HP1 HP0 1 1 0 0 TST MOD CB OSC STP SYS RST 0 0 NON EG BK 1 BK 0 RV DSP ON 1 1 0 1 PH1 PH 0 BCL INT 0 0 0 0 SN3 SN2 SN1 SN0 COMMAND0: Display Memory Write Address Setting Command COMMAND0: first byte DA0 to DA7 Register name 0 V0 1 V1 2 V2 3 V3 4 5 6 7 Register Contents Status Function Remarks 0 1 0 1 0 1 0 1 0 0 0 1 Display memory address 0 to 9H COMMAND0 identification code COMMAND0: second byte DA0 to DA7 Register name 0 H0 1 H1 2 H2 3 H3 4 H4 5 6 7 Register Contents Status Function Remarks 0 1 0 1 0 1 0 1 0 1 0 0 0 Display memory address 0 to 17H Second byte identification bit Note On system reset with RST, the status of all registers is set to 0. No.4246­5/11 LC7472M LC7472M COMMAND1: Display Character Data Write Command COMMAND1: first byte DA0 to DA7 Register name Register Contents Status 0 0 1 0 2 3 4 5 6 7 0 0 1 0 0 1 Remarks Function After command is input, display character data write mode is set until CS is set HIGH COMMAND1 identification code COMMAND1: second byte DA0 to DA7 Register name 0 C0 1 C1 2 C2 3 C3 4 C4 5 C5 6 7 at Register Contents Status Remarks Function 0 1 0 1 0 1 0 1 0 1 0 1 0 0 1 Character code 0 to 3FH Character attribute OFF Character attribute ON Note On system reset with RST, the status of all registers is set to 0. COMMAND2: Vertical Display Position and Character Size Setting Command COMMAND2: first byte DA0 to DA7 Register name 0 Register Contents VS10 Status 0 1 0 1 VS11 1 0 2 VS20 1 0 3 VS21 1 4 5 6 7 0 1 0 1 Remarks Function VS11 VS10 Height 0 0 1 1 0 1 0 1 1H/pixel 2H/pixel 3H/pixel 1H/pixel VS21 VS20 Height 0 0 1 1 0 1 0 1 1H/pixel 2H/pixel 3H/pixel 1H/pixel First row vertical character size Second row vertical character size COMMAND2 identification code No.4246­6/11 LC7472M LC7472M COMMAND2: second byte DA0 to DA7 Register name 0 Register Contents VP0 Status 0 Remarks Function Initial vertical coordinate position determined by 1 0 1 VP1 where H is the horizontal synchronization pulse period 1 0 2 VP2 The initial vertical coordinate position is set in 6 bits, VP0 to VP5, where the lsb, VP0, corresponds to 2H 1 0 3 VP3 1 0 4 VP4 1 0 5 VP5 1 6 7 0 0 Second byte identification bit Note On system reset with RST, the status of all registers is set to 0. COMMAND3: Horizontal Display Position and Character Size Setting Command COMMAND3: first byte DA0 to DA7 Register name 0 Register Contents HS10 Status 0 1 0 1 HS11 1 0 2 HS20 1 0 3 HS21 1 4 5 6 7 1 1 0 1 Remarks Function HS11 HS10 Width 0 0 1 1 0 1 0 1 1TC/pixel 2TC/pixel 3TC/pixel 1TC/pixel HS21 HS20 Width 0 0 1 1 0 1 0 1 1TC/pixel 2TC/pixel 3TC/pixel 1TC/pixel First row horizontal character size Second row horizontal character size COMMAND3 identification code No.4246­7/11 LC7472M LC7472M COMMAND3: second byte DA0 to DA7 Register name 0 HP0 1 HP1 2 HP2 3 HP3 4 HP4 5 HP5 6 7 Register Contents Status Function Remarks 0 1 0 1 0 1 0 1 0 1 0 1 0 0 The initial horizontal coordinate position is given by where TC is the OSCIN and OSCOUT operation mode oscillation period The initial horizontal coordinate position is set in 6 bits, HP0 to HP5, where the lsb, HP0, corresponds to 2TC Second byte identification bit Note On system reset with RST, the status of all registers is set to 0. COMMAND4: Display Control Setting Command COMMAND4: first byte DA0 to DA7 Register name 0 SYSRST 1 Register Contents OSCSTP Status 0 Function Resets all registers and turns the display OFF when HIGH A system reset also occurs when CS goes LOW Crystal and LC oscillator circuitry enable when LOW 1 External synchronization is effective only when the character display is OFF Color bar strobe signal is output when LOW When BCL is HIGH only Test operation mode when HIGH Test mode should not be selected during normal operation 0 1 2 CB 3 TSTMOD 4 5 6 7 Remarks 0 1 0 1 0 0 1 1 COMMAND4 identification code COMMAND4: second byte DA0 to DA7 Register name 0 DSPON 1 RV 2 Register Contents BK0 Status 0 1 0 1 Function Character display ON when HIGH Inverse characters ON when HIGH 0 Blinking ON when HIGH 1 3 BK1 4 EG 5 NON 6 7 0 1 0 1 0 1 0 0 Remarks Blinking period 0.5 s Blinking period 1.0 s Border OFF Border ON Interlaced scanning, 262.5 H/field Non-interlaced scanning, 263 H/field When blinking inverse characters, characters alternate between normal and inverse Selects blinking period Second byte identification bit Note On system reset with RST, the status of all registers is set to 0. No.4246­8/11 LC7472M LC7472M COMMAND5: Synchronization Signal Control Setting Command COMMAND5: first byte DA0 to DA7 Register name 0 INT 1 BCL 2 Register Contents PH0 Status 0 External synchronization 1 Internal synchronization 0 1 PH1 PH0 Phase 0 0 1 1 0 1 0 1 /2 1 0 PH1 1 4 5 6 7 1 0 1 1 Only available with internal synchronization Background color when LOW 0 3 Remarks Function 3/2 In phase Phase selection. In PAL-M mode, there is only one background color(blue-black). Otherwise, there are 4 types COMMAND5 identification code COMMAND5: second byte DA0 to DA7 Register name 0 SN0 1 SN1 2 SN2 3 SN3 4 5 6 7 Register Contents Status Remarks Function 0 1 SN3 SN2 SN1 SN0 Detection frequency 0 0 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 No detection 16 times 32 times 64 times 128 times 1 0 1 0 1 0 0 0 0 External, horizontal synchronization signal detection Second byte identification bit Note On system reset with RST, the status of all registers is set to 0. Display Configuration The display is 24 characters by 10 rows large. Up to 240 characters can be displayed, unless the character size is expanded. The display memory address is set as a row address in the range 0 to 9 and a column address in the range 0 to 23. No.4246­9/11 LC7472M LC7472M Composite Video Output Relative carrier amplitude (IRE) Output voltage amplitude (V) 100 3.000 90 2.857 46 2.228 20 1.857 10 1.714 8 1.685 0 1.571 ­20 1.285 ­40 1.000 Note VDD2=5.0V No.4246­10/11 LC7472M LC7472M Specifications of any and all SANYO products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer's products or equipment. SANYO Electric Co., Ltd. strives to supply high-quality high-reliability products. However, any and all semiconductor products fail with some probability. It is possible that these probabilistic failures could give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire, or that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO products(including technical data,services) described or contained herein are controlled under any of applicable local export control laws and regulations, such products must not be expor ted without obtaining the expor t license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written permission of SANYO Electric Co., Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the SANYO product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only ; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of July, 2001. Specifications and information herein are subject to change without notice. PS No.4246­11/11