NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
10BASE-T 100BASE-TX LAN9313-NU 128-PIN LAN9313-NZW 128-VTQFP 128-XVTQFP LAN9313 - Datasheet Archive
Three Port 10/100 Managed Ethernet Switch with MII PRODUCT FEATURES Datasheet Highlights Switch Management High performance and
LAN9313/LAN9313i Three Port 10/100 Managed Ethernet Switch with MII PRODUCT FEATURES Datasheet Highlights Switch Management High performance and full featured 3 port switch with VLAN, QoS packet prioritization, Rate Limiting, IGMP monitoring and management functions Serial management via SPI/I2C or SMI Unique Virtual PHY feature simplifies software development by mimicking the multiple switch ports as a single port PHY Integrated IEEE 1588 Hardware Time Stamp Unit Target Applications Cable, satellite, and IP set-top boxes Digital televisions Digital video recorders VoIP/Video phone systems Home gateways Test/Measurement equipment Industrial automation systems Ports - - - - - - - - - - - - - - - 2 internal 10/100 PHYs with HP Auto-MDIX support 1 MII - PHY mode or MAC mode Fully compliant with IEEE 802.3 standards 10BASE-T 10BASE-T and 100BASE-TX 100BASE-TX support Full and half duplex support Full duplex flow control Backpressure (forced collision) half duplex flow control Automatic flow control based on programmable levels Automatic 32-bit CRC generation and checking 2K Jumbo packet support Programmable interframe gap, flow control pause value Full transmit/receive statistics Auto-negotiation Automatic MDI/MDI-X Loop-back mode Serial Management - SPI/I2C (slave) access to all internal registers - MIIM (MDIO) access to PHY related registers - SMI (extended MIIM) access to all internal registers Key Benefits IEEE 1588 Hardware Time Stamp Unit Ethernet Switch Fabric - 32K buffer RAM - 1K entry forwarding table - Port based IEEE 802.1Q VLAN support (16 groups) Programmable IEEE 802.1Q tag insertion/removal - IEEE 802.1d spanning tree protocol support - QoS/CoS Packet prioritization 4 dynamic QoS queues per port Input priority determined by VLAN tag, DA lookup, TOS, DIFFSERV or port default value Programmable class of service map based on input priority Remapping of 802.1Q priority field on per port basis Programmable rate limiting at the ingress/egress ports with random early discard, per port / priority - IGMP v1/v2/v3 monitoring for Multicast packet filtering - Programmable filter by MAC address SMSC LAN9313/LAN9313i - Port mirroring/monitoring/sniffing: ingress and/or egress traffic on any ports or port pairs - Fully compliant statistics (MIB) gathering counters - Control registers configurable on-the-fly - Global 64-bit tunable clock - Master or slave mode per port - Time stamp on TX or RX of Sync and Delay_req packets per port, Timestamp on GPIO - 64-bit timer comparator event generation (GPIO or IRQ) Other Features - General Purpose Timer - Serial EEPROM interface (I2C master or MicrowireTM master) for non-managed configuration - Programmable GPIOs/LEDs Single 3.3V power supply Available in Commercial & Industrial Temp. Ranges DATASHEET Revision 1.6 (08-18-09) Three Port 10/100 Managed Ethernet Switch with MII Datasheet ORDER NUMBERS: LAN9313-NU LAN9313-NU FOR 128-PIN 128-PIN, VTQFP LEAD-FREE ROHS COMPLIANT PACKAGE (0 TO 70°C TEMP RANGE) LAN9313-NZW LAN9313-NZW FOR 128-PIN 128-PIN, XVTQFP LEAD-FREE ROHS COMPLIANT PACKAGE (0 TO 70°C TEMP RANGE) LAN9313i-NZW FOR 128-PIN 128-PIN, XVTQFP LEAD-FREE ROHS COMPLIANT PACKAGE (-40 TO 85°C TEMP RANGE) 80 ARKAY DRIVE, HAUPPAUGE, NY 11788 (631) 435-6000, FAX (631) 273-3123 Copyright © 2009 SMSC or its subsidiaries. All rights reserved. Circuit diagrams and other information relating to SMSC products are included as a means of illustrating typical applications. Consequently, complete information sufficient for construction purposes is not necessarily given. Although the information has been checked and is believed to be accurate, no responsibility is assumed for inaccuracies. SMSC reserves the right to make changes to specifications and product descriptions at any time without notice. Contact your local SMSC sales office to obtain the latest specifications before placing your product order. The provision of this information does not convey to the purchaser of the described semiconductor devices any licenses under any patent rights or other intellectual property rights of SMSC or others. All sales are expressly conditional on your agreement to the terms and conditions of the most recently dated version of SMSC's standard Terms of Sale Agreement dated before the date of your order (the "Terms of Sale Agreement"). The product may contain design defects or errors known as anomalies which may cause the product's functions to deviate from published specifications. Anomaly sheets are available upon request. SMSC products are not designed, intended, authorized or warranted for use in any life support or other application where product failure could cause or contribute to personal injury or severe property damage. Any and all such uses without prior written approval of an Officer of SMSC and further testing and/or modification will be fully at the risk of the customer. Copies of this document or other SMSC literature, as well as the Terms of Sale Agreement, may be obtained by visiting SMSC's website at http://www.smsc.com. SMSC is a registered trademark of Standard Microsystems Corporation ("SMSC"). Product names and company names are the trademarks of their respective holders. SMSC DISCLAIMS AND EXCLUDES ANY AND ALL WARRANTIES, INCLUDING WITHOUT LIMITATION ANY AND ALL IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE, AND AGAINST INFRINGEMENT AND THE LIKE, AND ANY AND ALL WARRANTIES ARISING FROM ANY COURSE OF DEALING OR USAGE OF TRADE. IN NO EVENT SHALL SMSC BE LIABLE FOR ANY DIRECT, INCIDENTAL, INDIRECT, SPECIAL, PUNITIVE, OR CONSEQUENTIAL DAMAGES; OR FOR LOST DATA, PROFITS, SAVINGS OR REVENUES OF ANY KIND; REGARDLESS OF THE FORM OF ACTION, WHETHER BASED ON CONTRACT; TORT; NEGLIGENCE OF SMSC OR OTHERS; STRICT LIABILITY; BREACH OF WARRANTY; OR OTHERWISE; WHETHER OR NOT ANY REMEDY OF BUYER IS HELD TO HAVE FAILED OF ITS ESSENTIAL PURPOSE, AND WHETHER OR NOT SMSC HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Revision 1.6 (08-18-09) 2 DATASHEET SMSC LAN9313/LAN9313i Three Port 10/100 Managed Ethernet Switch with MII Datasheet Table of Contents Chapter 1 Preface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 1.1 1.2 1.3 General Terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Buffer Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Register Nomenclature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Chapter 2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.1 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.1 System Clocks/Reset/PME Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.2 System Interrupt Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.3 Switch Fabric . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.4 Ethernet PHYs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.5 PHY Management Interface (PMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.6 SPI/I2C Slave Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.7 SMI Slave Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.8 EEPROM Controller/Loader . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.9 1588 Time Stamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.10 GPIO/LED Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3.1 MAC Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3.2 PHY Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3.3 Management Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 19 20 20 21 21 21 21 22 22 22 22 23 23 23 23 Chapter 3 Pin Description and Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.1 Pin Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1.1 128-VTQFP 128-VTQFP Pin Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1.2 128-XVTQFP 128-XVTQFP Pin Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 26 27 28 Chapter 4 Clocking, Resets, and Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 4.1 Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 4.2 Resets. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 4.2.1 Chip-Level Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 4.2.1.1 4.2.1.2 4.2.2 4.2.2.1 Power-On Reset (POR) . 42 nRST Pin Reset . 43 Multi-Module Resets. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Digital Reset (DIGITAL_RST) . 43 4.2.3 Single-Module Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 4.2.3.1 4.2.3.2 4.2.3.3 Port 2 PHY Reset. 44 Port 1 PHY Reset. 44 Virtual PHY Reset . 44 4.2.4 Configuration Straps. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 4.2.4.1 4.2.4.2 Soft-Straps . 45 Hard-Straps. 50 4.3 Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 4.3.1 Port 1 & 2 PHY Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Chapter 5 System Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 5.1 Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2 Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2.1 1588 Time Stamp Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2.2 Switch Fabric Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2.3 Ethernet PHY Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2.4 GPIO Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SMSC LAN9313/LAN9313i 3 DATASHEET 52 52 54 54 55 55 Revision 1.6 (08-18-09) Three Port 10/100 Managed Ethernet Switch with MII Datasheet 5.2.5 5.2.6 5.2.7 General Purpose Timer Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Software Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Device Ready Interrupt. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Chapter 6 Switch Fabric . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 6.1 Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.2 Switch Fabric CSRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.2.1 Switch Fabric CSR Writes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.2.2 Switch Fabric CSR Reads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.2.3 Flow Control Enable Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.3 10/100 Ethernet MACs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.3.1 Receive MAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.3.1.1 57 57 58 59 60 62 62 Receive Counters . 63 6.3.2 Transmit MAC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 6.3.2.1 Transmit Counters . 64 6.4.1.1 6.4.1.2 6.4.1.3 6.4.1.4 6.4.1.5 6.4.1.6 6.4.1.7 Learning/Aging/Migration . 66 Static Entries. 66 Multicast Pruning . 66 Address Filtering . 66 Spanning Tree Port State Override. 66 MAC Destination Address Lookup Priority. 66 Host Access . 66 6.4 Switch Engine (SWE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 6.4.1 MAC Address Lookup Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 6.4.2 6.4.3 Forwarding Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Transmit Priority Queue Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 6.4.3.1 6.4.3.2 6.4.3.3 6.4.3.4 Port Default Priority. 71 IP Precedence Based Priority . 71 DIFFSERV Based Priority. 71 VLAN Priority . 71 6.4.4 6.4.5 6.4.6 6.4.6.1 VLAN Support. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Spanning Tree Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Ingress Flow Metering and Coloring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Ingress Flow Calculation. 74 6.4.7 6.4.8 6.4.9 6.4.10 Broadcast Storm Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IPv4 IGMP Support. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port Mirroring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Host CPU Port Special Tagging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 76 77 77 6.4.10.1 6.4.10.2 Packets from the Host CPU . 77 Packets to the Host CPU . 78 6.5.1.1 Buffer Limits and Flow Control Levels . 78 6.4.11 Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 6.5 Buffer Manager (BM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 6.5.1 Packet Buffer Allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 6.5.2 Random Early Discard (RED). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.5.3 Transmit Queues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.5.4 Transmit Priority Queue Servicing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.5.5 Egress Rate Limiting (Leaky Bucket) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.5.6 Adding, Removing, and Changing VLAN Tags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.5.7 Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.6 Switch Fabric Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 79 79 79 80 83 83 Chapter 7 Ethernet PHYs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 7.1 Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.1.1 PHY Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.2 Port 1 & 2 PHYs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.2.1 100BASE-TX 100BASE-TX Transmit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.2.1.1 7.2.1.2 7.2.1.3 7.2.1.4 7.2.1.5 84 84 85 86 MII MAC Interface . 86 4B/5B Encoder. 86 Scrambler and PISO . 88 NRZI and MLT-3 Encoding . 88 100M Transmit Driver . 88 Revision 1.6 (08-18-09) 4 DATASHEET SMSC LAN9313/LAN9313i Three Port 10/100 Managed Ethernet Switch with MII Datasheet 7.2.1.6 100M Phase Lock Loop (PLL) . 88 7.2.2 100BASE-TX 100BASE-TX Receive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 7.2.2.1 7.2.2.2 7.2.2.3 7.2.2.4 7.2.2.5 7.2.2.6 7.2.2.7 A/D Converter . 89 DSP: Equalizer, BLW Correction and Clock/Data Recovery . 89 NRZI and MLT-3 Decoding . 90 Descrambler and SIPO . 90 5B/4B Decoding . 90 Receiver Errors . 90 MII MAC Interface . 90 7.2.3 10BASE-T 10BASE-T Transmit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 7.2.3.1 7.2.3.2 MII MAC Interface . 91 10M TX Driver and PLL . 91 7.2.4 10BASE-T 10BASE-T Receive. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 7.2.4.1 7.2.4.2 7.2.4.3 7.2.4.4 Filter and Squelch . 91 10M RX and PLL. 91 MII MAC Interface . 92 Jabber Detection. 92 7.2.5 PHY Auto-negotiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 7.2.5.1 7.2.5.2 7.2.5.3 7.2.5.4 7.2.5.5 PHY Pause Flow Control . 94 Parallel Detection. 94 Restarting Auto-Negotiation. 94 Disabling Auto-Negotiation . 94 Half Vs. Full-Duplex . 95 7.2.6 7.2.7 7.2.8 7.2.8.1 HP Auto-MDIX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 MII MAC Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 PHY Management Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 PHY Interrupts . 96 7.2.9 PHY Power-Down Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 7.2.9.1 7.2.9.2 PHY General Power-Down . 97 PHY Energy Detect Power-Down . 97 7.2.10.1 7.2.10.2 7.2.10.3 PHY Software Reset via RESET_CTL. 97 PHY Software Reset via PHY_BASIC_CTRL_x . 97 PHY Power-Down Reset. 97 7.3.1.1 7.3.1.2 7.3.1.3 Parallel Detection. 99 Disabling Auto-Negotiation . 99 Virtual PHY Pause Flow Control . 99 7.2.10 PHY Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 7.2.11 LEDs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.2.12 Required Ethernet Magnetics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.3 Virtual PHY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.3.1 Virtual PHY Auto-Negotiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.3.2 7.3.2.1 98 98 98 98 Virtual PHY in MAC Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Full-Duplex Flow Control. 100 7.3.3 Virtual PHY Resets. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 7.3.3.1 7.3.3.2 Virtual PHY Software Reset via RESET_CTL . 100 Virtual PHY Software Reset via VPHY_BASIC_CTRL . 100 Chapter 8 Serial Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 8.1 Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.2 I2C/Microwire Master EEPROM Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.2.1 EEPROM Controller Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.2.2 I2C EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.2.2.1 8.2.2.2 8.2.2.3 8.2.2.4 8.2.2.5 101 101 102 103 I2C Protocol Overview . 104 I2C EEPROM Device Addressing. 105 I2C EEPROM Byte Read . 106 I2C EEPROM Sequential Byte Reads . 106 I2C EEPROM Byte Writes . 107 8.2.3 Microwire EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 8.2.3.1 8.2.3.2 8.2.3.3 8.2.3.4 8.2.3.5 8.2.3.6 8.2.3.7 8.2.3.8 Microwire Master Commands . 108 ERASE (Erase Location) . 109 ERAL (Erase All). 110 EWDS (Erase/Write Disable) . 110 EWEN (Erase/Write Enable). 111 READ (Read Location) . 111 WRITE (Write Location) . 112 WRAL (Write All). 112 8.2.4 EEPROM Loader . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 8.2.4.1 8.2.4.2 8.2.4.3 8.2.4.4 EEPROM Loader Operation . 113 EEPROM Valid Flag . 115 MAC Address. 115 Soft-Straps . 115 SMSC LAN9313/LAN9313i 5 DATASHEET Revision 1.6 (08-18-09) Three Port 10/100 Managed Ethernet Switch with MII Datasheet 8.2.4.4.1 PHY Registers Synchronization .115 8.2.4.4.2 Virtual PHY Registers Synchronization.116 8.2.4.4.3 LED and Manual Flow Control Register Synchronization .116 8.2.4.5 8.2.4.6 8.2.4.7 Register Data . 116 EEPROM Loader Finished Wait-State. 117 Reset Sequence and EEPROM Loader. 117 8.4.1.1 SPI Read Polling for Reset Complete. 120 8.3 SPI/I2C Slave Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 8.4 SPI Slave Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 8.4.1 SPI Read Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 8.4.2 SPI Write Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.5 I2C Slave Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.5.1 I2C Slave Command Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.5.2 I2C Slave Read Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.5.2.1 8.5.3 120 121 121 122 I2C Slave Read Polling for Reset Complete . 123 I2C Slave Write Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 Chapter 9 MII Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 9.1 Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 9.2 SMI Slave Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 9.2.1 Read Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 9.2.1.1 SMI Read Polling for Reset Complete . 126 9.2.2 Write Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.3 PHY Management Interface (PMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.3.1 EEPROM Loader PHY Register Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.4 MII Mode Multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.4.1 MAC Mode Unmanaged . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.4.2 MAC Mode SMI Managed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.4.3 MAC Mode I2C/SPI Managed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.4.4 PHY Mode Unmanaged . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.4.5 PHY Mode SMI Managed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.4.6 PHY Mode I2C/SPI Managed. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 127 127 128 128 129 130 131 132 133 Chapter 10 IEEE 1588 Hardware Time Stamp Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 10.1 Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.1.1 IEEE 1588 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.1.2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.2 IEEE 1588 Time Stamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.2.1 Capture Locking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.2.2 PTP Message Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.3 IEEE 1588 Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.4 IEEE 1588 Clock/Events. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.5 IEEE 1588 GPIOs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.6 IEEE 1588 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 134 135 136 137 138 139 140 140 140 Chapter 11 General Purpose Timer & Free-Running Clock. . . . . . . . . . . . . . . . . . . . . . . . 141 11.1 11.2 General Purpose Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 Free-Running Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 Chapter 12 GPIO/LED Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 12.1 Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 12.2 GPIO Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 12.2.1 GPIO IEEE 1588 Timestamping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 12.2.1.1 12.2.1.2 IEEE 1588 GPIO Inputs . 143 IEEE 1588 GPIO Outputs . 143 12.2.2.1 GPIO Interrupt Polarity. 143 12.2.2 GPIO Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 Revision 1.6 (08-18-09) 6 DATASHEET SMSC LAN9313/LAN9313i Three Port 10/100 Managed Ethernet Switch with MII Datasheet 12.2.2.2 12.3 IEEE 1588 GPIO Interrupts. 144 LED Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 Chapter 13 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 13.1 System Control and Status Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 13.1.1 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 13.1.1.1 13.1.1.2 13.1.1.3 Interrupt Configuration Register (IRQ_CFG) . 151 Interrupt Status Register (INT_STS). 153 Interrupt Enable Register (INT_EN). 154 13.1.2.1 13.1.2.2 13.1.2.3 13.1.2.4 General Purpose I/O Configuration Register (GPIO_CFG) . 155 General Purpose I/O Data & Direction Register (GPIO_DATA_DIR) . 157 General Purpose I/O Interrupt Status and Enable Register (GPIO_INT_STS_EN). 158 LED Configuration Register (LED_CFG) . 159 13.1.3.1 13.1.3.2 EEPROM Command Register (E2P_CMD) . 160 EEPROM Data Register (E2P_DATA). 163 13.1.4.1 13.1.4.2 13.1.4.3 13.1.4.4 13.1.4.5 13.1.4.6 13.1.4.7 13.1.4.8 13.1.4.9 13.1.4.10 13.1.4.11 13.1.4.12 13.1.4.13 13.1.4.14 13.1.4.15 13.1.4.16 13.1.4.17 13.1.4.18 13.1.4.19 13.1.4.20 13.1.4.21 13.1.4.22 13.1.4.23 13.1.4.24 Port x 1588 Clock High-DWORD Receive Capture Register (1588_CLOCK_HI_RX_CAPTURE_x) . 164 Port x 1588 Clock Low-DWORD Receive Capture Register (1588_CLOCK_LO_RX_CAPTURE_x) . 165 Port x 1588 Sequence ID, Source UUID High-WORD Receive Capture Register (1588_SEQ_ID_SRC_UUID_HI_RX_CAPTURE_x). 166 Port x 1588 Source UUID Low-DWORD Receive Capture Register (1588_SRC_UUID_LO_RX_CAPTURE_x). 167 Port x 1588 Clock High-DWORD Transmit Capture Register (1588_CLOCK_HI_TX_CAPTURE_x). 168 Port x 1588 Clock Low-DWORD Transmit Capture Register (1588_CLOCK_LO_TX_CAPTURE_x) . 169 Port x 1588 Sequence ID, Source UUID High-WORD Transmit Capture Register (1588_SEQ_ID_SRC_UUID_HI_TX_CAPTURE_x) . 170 Port x 1588 Source UUID Low-DWORD Transmit Capture Register (1588_SRC_UUID_LO_TX_CAPTURE_x) . 171 GPIO 8 1588 Clock High-DWORD Capture Register (1588_CLOCK_HI_CAPTURE_GPIO_8). 172 GPIO 8 1588 Clock Low-DWORD Capture Register (1588_CLOCK_LO_CAPTURE_GPIO_8) . 173 GPIO 9 1588 Clock High-DWORD Capture Register (1588_CLOCK_HI_CAPTURE_GPIO_9). 174 GPIO 9 1588 Clock Low-DWORD Capture Register (1588_CLOCK_LO_CAPTURE_GPIO_9) . 175 1588 Clock High-DWORD Register (1588_CLOCK_HI). 176 1588 Clock Low-DWORD Register (1588_CLOCK_LO) . 177 1588 Clock Addend Register (1588_CLOCK_ADDEND) . 178 1588 Clock Target High-DWORD Register (1588_CLOCK_TARGET_HI). 179 1588 Clock Target Low-DWORD Register (1588_CLOCK_TARGET_LO) . 180 1588 Clock Target Reload High-DWORD Register (1588_CLOCK_TARGET_RELOAD_HI) . 181 1588 Clock Target Reload/Add Low-DWORD Register (1588_CLOCK_TARGET_RELOAD_LO). 182 1588 Auxiliary MAC Address High-WORD Register (1588_AUX_MAC_HI) . 183 1588 Auxiliary MAC Address Low-DWORD Register (1588_AUX_MAC_LO) . 184 1588 Configuration Register (1588_CONFIG). 185 1588 Interrupt Status and Enable Register (1588_INT_STS_EN). 189 1588 Command Register (1588_CMD) . 191 13.1.5.1 13.1.5.2 13.1.5.3 13.1.5.4 13.1.5.5 13.1.5.6 13.1.5.7 13.1.5.8 Port 1 Manual Flow Control Register (MANUAL_FC_1). 192 Port 2 Manual Flow Control Register (MANUAL_FC_2). 194 Port 0(External MII) Manual Flow Control Register (MANUAL_FC_MII) . 196 Switch Fabric CSR Interface Data Register (SWITCH_CSR_DATA) . 198 Switch Fabric CSR Interface Command Register (SWITCH_CSR_CMD) . 199 Switch Fabric MAC Address High Register (SWITCH_MAC_ADDRH) . 201 Switch Fabric MAC Address Low Register (SWITCH_MAC_ADDRL) . 202 Switch Fabric CSR Interface Direct Data Register (SWITCH_CSR_DIRECT_DATA) . 204 13.1.6.1 13.1.6.2 PHY Management Interface Data Register (PMI_DATA) . 207 PHY Management Interface Access Register (PMI_ACCESS) . 208 13.1.7.1 13.1.7.2 13.1.7.3 13.1.7.4 13.1.7.5 13.1.7.6 13.1.7.7 13.1.7.8 Virtual PHY Basic Control Register (VPHY_BASIC_CTRL) . 210 Virtual PHY Basic Status Register (VPHY_BASIC_STATUS). 212 Virtual PHY Identification MSB Register (VPHY_ID_MSB) . 214 Virtual PHY Identification LSB Register (VPHY_ID_LSB) . 215 Virtual PHY Auto-Negotiation Advertisement Register (VPHY_AN_ADV). 216 Virtual PHY Auto-Negotiation Link Partner Base Page Ability Register (VPHY_AN_LP_BASE_ABILITY) . 218 Virtual PHY Auto-Negotiation Expansion Register (VPHY_AN_EXP) . 221 Virtual PHY Special Control/Status Register (VPHY_SPECIAL_CONTROL_STATUS) . 222 13.1.8.1 13.1.8.2 13.1.8.3 13.1.8.4 13.1.8.5 13.1.8.6 13.1.8.7 Chip ID and Revision (ID_REV). 224 Byte Order Test Register (BYTE_TEST) . 225 Hardware Configuration Register (HW_CFG). 226 General Purpose Timer Configuration Register (GPT_CFG) . 227 General Purpose Timer Count Register (GPT_CNT) . 228 Free Running 25MHz Counter Register (FREE_RUN). 229 Reset Control Register (RESET_CTL) . 230 13.2.2.1 Port x PHY Basic Control Register (PHY_BASIC_CONTROL_x) . 233 13.1.2 GPIO/LED. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 13.1.3 EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 13.1.4 IEEE 1588 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 13.1.5 Switch Fabric . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 13.1.6 PHY Management Interface (PMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 13.1.7 Virtual PHY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 13.1.8 Miscellaneous. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 13.2 Ethernet PHY Control and Status Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231 13.2.1 Virtual PHY Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231 13.2.2 Port 1 & 2 PHY Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231 SMSC LAN9313/LAN9313i 7 DATASHEET Revision 1.6 (08-18-09) Three Port 10/100 Managed Ethernet Switch with MII Datasheet 13.2.2.2 13.2.2.3 13.2.2.4 13.2.2.5 13.2.2.6 13.2.2.7 13.2.2.8 13.2.2.9 13.2.2.10 13.2.2.11 13.2.2.12 13.2.2.13 Port x PHY Basic Status Register (PHY_BASIC_STATUS_x) . 235 Port x PHY Identification MSB Register (PHY_ID_MSB_x). 237 Port x PHY Identification LSB Register (PHY_ID_LSB_x). 238 Port x PHY Auto-Negotiation Advertisement Register (PHY_AN_ADV_x) . 239 Port x PHY Auto-Negotiation Link Partner Base Page Ability Register (PHY_AN_LP_BASE_ABILITY_x) . 242 Port x PHY Auto-Negotiation Expansion Register (PHY_AN_EXP_x) . 244 Port x PHY Mode Control/Status Register (PHY_MODE_CONTROL_STATUS_x). 245 Port x PHY Special Modes Register (PHY_SPECIAL_MODES_x) . 246 Port x PHY Special Control/Status Indication Register (PHY_SPECIAL_CONTROL_STAT_IND_x) . 248 Port x PHY Interrupt Source Flags Register (PHY_INTERRUPT_SOURCE_x). 250 Port x PHY Interrupt Mask Register (PHY_INTERRUPT_MASK_x) . 251 Port x PHY Special Control/Status Register (PHY_SPECIAL_CONTROL_STATUS_x). 252 13.3.1.1 13.3.1.2 13.3.1.3 13.3.1.4 Switch Device ID Register (SW_DEV_ID) . 264 Switch Reset Register (SW_RESET) . 265 Switch Global Interrupt Mask Register (SW_IMR). 266 Switch Global Interrupt Pending Register (SW_IPR). 267 13.3.2.1 13.3.2.2 13.3.2.3 13.3.2.4 13.3.2.5 13.3.2.6 13.3.2.7 13.3.2.8 13.3.2.9 13.3.2.10 13.3.2.11 13.3.2.12 13.3.2.13 13.3.2.14 13.3.2.15 13.3.2.16 13.3.2.17 13.3.2.18 13.3.2.19 13.3.2.20 13.3.2.21 13.3.2.22 13.3.2.23 13.3.2.24 13.3.2.25 13.3.2.26 13.3.2.27 13.3.2.28 13.3.2.29 13.3.2.30 13.3.2.31 13.3.2.32 13.3.2.33 13.3.2.34 13.3.2.35 13.3.2.36 13.3.2.37 13.3.2.38 13.3.2.39 13.3.2.40 13.3.2.41 13.3.2.42 13.3.2.43 13.3.2.44 Port x MAC Version ID Register (MAC_VER_ID_x) . 268 Port x MAC Receive Configuration Register (MAC_RX_CFG_x) . 269 Port x MAC Receive Undersize Count Register (MAC_RX_UNDSZE_CNT_x) . 270 Port x MAC Receive 64 Byte Count Register (MAC_RX_64_CNT_x). 271 Port x MAC Receive 65 to 127 Byte Count Register (MAC_RX_65_TO_127_CNT_x). 272 Port x MAC Receive 128 to 255 Byte Count Register (MAC_RX_128_TO_255_CNT_x). 273 Port x MAC Receive 256 to 511 Byte Count Register (MAC_RX_256_TO_511_CNT_x). 274 Port x MAC Receive 512 to 1023 Byte Count Register (MAC_RX_512_TO_1023_CNT_x). 275 Port x MAC Receive 1024 to Max Byte Count Register (MAC_RX_1024_TO_MAX_CNT_x) . 276 Port x MAC Receive Oversize Count Register (MAC_RX_OVRSZE_CNT_x) . 277 Port x MAC Receive OK Count Register (MAC_RX_PKTOK_CNT_x). 278 Port x MAC Receive CRC Error Count Register (MAC_RX_CRCERR_CNT_x). 279 Port x MAC Receive Multicast Count Register (MAC_RX_MULCST_CNT_x) . 280 Port x MAC Receive Broadcast Count Register (MAC_RX_BRDCST_CNT_x) . 281 Port x MAC Receive Pause Frame Count Register (MAC_RX_PAUSE_CNT_x) . 282 Port x MAC Receive Fragment Error Count Register (MAC_RX_FRAG_CNT_x). 283 Port x MAC Receive Jabber Error Count Register (MAC_RX_JABB_CNT_x) . 284 Port x MAC Receive Alignment Error Count Register (MAC_RX_ALIGN_CNT_x) . 285 Port x MAC Receive Packet Length Count Register (MAC_RX_PKTLEN_CNT_x) . 286 Port x MAC Receive Good Packet Length Count Register (MAC_RX_GOODPKTLEN_CNT_x) . 287 Port x MAC Receive Symbol Error Count Register (MAC_RX_SYMBOL_CNT_x) . 288 Port x MAC Receive Control Frame Count Register (MAC_RX_CTLFRM_CNT_x) . 289 Port x MAC Transmit Configuration Register (MAC_TX_CFG_x) . 290 Port x MAC Transmit Flow Control Settings Register (MAC_TX_FC_SETTINGS_x) . 291 Port x MAC Transmit Deferred Count Register (MAC_TX_DEFER_CNT_x) . 292 Port x MAC Transmit Pause Count Register (MAC_TX_PAUSE_CNT_x) . 293 Port x MAC Transmit OK Count Register (MAC_TX_PKTOK_CNT_x) . 294 Port x MAC Transmit 64 Byte Count Register (MAC_TX_64_CNT_x) . 295 Port x MAC Transmit 65 to 127 Byte Count Register (MAC_TX_65_TO_127_CNT_x) . 296 Port x MAC Transmit 128 to 255 Byte Count Register (MAC_TX_128_TO_255_CNT_x) . 297 Port x MAC Transmit 256 to 511 Byte Count Register (MAC_TX_256_TO_511_CNT_x) . 298 Port x MAC Transmit 512 to 1023 Byte Count Register (MAC_TX_512_TO_1023_CNT_x) . 299 Port x MAC Transmit 1024 to Max Byte Count Register (MAC_TX_1024_TO_MAX_CNT_x). 300 Port x MAC Transmit Undersize Count Register (MAC_TX_UNDSZE_CNT_x) . 301 Port x MAC Transmit Packet Length Count Register (MAC_TX_PKTLEN_CNT_x) . 302 Port x MAC Transmit Broadcast Count Register (MAC_TX_BRDCST_CNT_x) . 303 Port x MAC Transmit Multicast Count Register (MAC_TX_MULCST_CNT_x) . 304 Port x MAC Transmit Late Collision Count Register (MAC_TX_LATECOL_CNT_x) . 305 Port x MAC Transmit Excessive Collision Count Register (MAC_TX_EXCCOL_CNT_x). 306 Port x MAC Transmit Single Collision Count Register (MAC_TX_SNGLECOL_CNT_x) . 307 Port x MAC Transmit Multiple Collision Count Register (MAC_TX_MULTICOL_CNT_x) . 308 Port x MAC Transmit Total Collision Count Register (MAC_TX_TOTALCOL_CNT_x). 309 Port x MAC Interrupt Mask Register (MAC_IMR_x) . 310 Port x MAC Interrupt Pending Register (MAC_IPR_x) . 311 13.3.3.1 13.3.3.2 13.3.3.3 13.3.3.4 13.3.3.5 13.3.3.6 13.3.3.7 13.3.3.8 13.3.3.9 13.3.3.10 13.3.3.11 13.3.3.12 13.3.3.13 13.3.3.14 13.3.3.15 13.3.3.16 Switch Engine ALR Command Register (SWE_ALR_CMD) . 312 Switch Engine ALR Write Data 0 Register (SWE_ALR_WR_DAT_0) . 313 Switch Engine ALR Write Data 1 Register (SWE_ALR_WR_DAT_1) . 314 Switch Engine ALR Read Data 0 Register (SWE_ALR_RD_DAT_0). 316 Switch Engine ALR Read Data 1 Register (SWE_ALR_RD_DAT_1). 317 Switch Engine ALR Command Status Register (SWE_ALR_CMD_STS) . 319 Switch Engine ALR Configuration Register (SWE_ALR_CFG) . 320 Switch Engine VLAN Command Register (SWE_VLAN_CMD). 321 Switch Engine VLAN Write Data Register (SWE_VLAN_WR_DATA). 322 Switch Engine VLAN Read Data Register (SWE_VLAN_RD_DATA) . 323 Switch Engine VLAN Command Status Register (SWE_VLAN_CMD_STS) . 324 Switch Engine DIFFSERV Table Command Register (SWE_DIFFSERV_TBL_CFG). 325 Switch Engine DIFFSERV Table Write Data Register (SWE_DIFFSERV_TBL_WR_DATA) . 326 Switch Engine DIFFSERV Table Read Data Register (SWE_DIFFSERV_TBL_RD_DATA) . 327 Switch Engine DIFFSERV Table Command Status Register (SWE_DIFFSERV_TBL_CMD_STS) . 328 Switch Engine Global Ingress Configuration Register (SWE_GLOBAL_INGRSS_CFG). 329 13.3 Switch Fabric Control and Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253 13.3.1 General Switch CSRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264 13.3.2 Switch Port 0, Port 1, and Port 2 CSRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268 13.3.3 Switch Engine CSRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312 Revision 1.6 (08-18-09) 8 DATASHEET SMSC LAN9313/LAN9313i Three Port 10/100 Managed Ethernet Switch with MII Datasheet 13.3.3.17 13.3.3.18 13.3.3.19 13.3.3.20 13.3.3.21 13.3.3.22 13.3.3.23 13.3.3.24 13.3.3.25 13.3.3.26 Switch Engine Port Ingress Configuration Register (SWE_PORT_INGRSS_CFG) . 330 Switch Engine Admit Only VLAN Register (SWE_ADMT_ONLY_VLAN). 331 Switch Engine Port State Register (SWE_PORT_STATE). 332 Switch Engine Priority to Queue Register (SWE_PRI_TO_QUE) . 333 Switch Engine Port Mirroring Register (SWE_PORT_MIRROR). 334 Switch Engine Ingress Port Type Register (SWE_INGRSS_PORT_TYP) . 335 Switch Engine Broadcast Throttling Register (SWE_BCST_THROT) . 336 Switch Engine Admit Non Member Register (SWE_ADMT_N_MEMBER). 337 Switch Engine Ingress Rate Configuration Register (SWE_INGRSS_RATE_CFG) . 338 Switch Engine Ingress Rate Command Register (SWE_INGRSS_RATE_CMD). 339 13.3.3.27 13.3.3.28 13.3.3.29 13.3.3.30 13.3.3.31 13.3.3.32 13.3.3.33 13.3.3.34 13.3.3.35 13.3.3.36 13.3.3.37 13.3.3.38 13.3.3.39 13.3.3.40 Switch Engine Ingress Rate Command Status Register (SWE_INGRSS_RATE_CMD_STS) . 341 Switch Engine Ingress Rate Write Data Register (SWE_INGRSS_RATE_WR_DATA). 342 Switch Engine Ingress Rate Read Data Register (SWE_INGRSS_RATE_RD_DATA) . 343 Switch Engine Port 0 Ingress Filtered Count Register (SWE_FILTERED_CNT_MII) . 344 Switch Engine Port 1 Ingress Filtered Count Register (SWE_FILTERED_CNT_1) . 345 Switch Engine Port 2 Ingress Filtered Count Register (SWE_FILTERED_CNT_2) . 346 Switch Engine Port 0 Ingress VLAN Priority Regeneration Table Register (SWE_INGRSS_REGEN_TBL_MII) . 347 Switch Engine Port 1 Ingress VLAN Priority Regeneration Table Register (SWE_INGRSS_REGEN_TBL_1) . 348 Switch Engine Port 2 Ingress VLAN Priority Regeneration Table Register (SWE_INGRSS_REGEN_TBL_2) . 349 Switch Engine Port 0 Learn Discard Count Register (SWE_LRN_DISCRD_CNT_MII) . 350 Switch Engine Port 1 Learn Discard Count Register (SWE_LRN_DISCRD_CNT_1) . 351 Switch Engine Port 2 Learn Discard Count Register (SWE_LRN_DISCRD_CNT_2) . 352 Switch Engine Interrupt Mask Register (SWE_IMR). 353 Switch Engine Interrupt Pending Register (SWE_IPR). 354 13.3.4.1 13.3.4.2 13.3.4.3 13.3.4.4 13.3.4.5 13.3.4.6 13.3.4.7 13.3.4.8 13.3.4.9 13.3.4.10 13.3.4.11 13.3.4.12 13.3.4.13 13.3.4.14 13.3.4.15 13.3.4.16 13.3.4.17 13.3.4.18 13.3.4.19 13.3.4.20 13.3.4.21 13.3.4.22 13.3.4.23 13.3.4.24 13.3.4.25 13.3.4.26 13.3.4.27 Buffer Manager Configuration Register (BM_CFG) . 356 Buffer Manager Drop Level Register (BM_DROP_LVL). 357 Buffer Manager Flow Control Pause Level Register (BM_FC_PAUSE_LVL). 358 Buffer Manager Flow Control Resume Level Register (BM_FC_RESUME_LVL) . 359 Buffer Manager Broadcast Buffer Level Register (BM_BCST_LVL). 360 Buffer Manager Port 0 Drop Count Register (BM_DRP_CNT_SRC_MII) . 361 Buffer Manager Port 1 Drop Count Register (BM_DRP_CNT_SRC_1) . 362 Buffer Manager Port 2 Drop Count Register (BM_DRP_CNT_SRC_2) . 363 Buffer Manager Reset Status Register (BM_RST_STS) . 364 Buffer Manager Random Discard Table Command Register (BM_RNDM_DSCRD_TBL_CMD) . 365 Buffer Manager Random Discard Table Write Data Register (BM_RNDM_DSCRD_TBL_WDATA) . 366 Buffer Manager Random Discard Table Read Data Register (BM_RNDM_DSCRD_TBL_RDATA). 367 Buffer Manager Egress Port Type Register (BM_EGRSS_PORT_TYPE) . 368 Buffer Manager Port 0 Egress Rate Priority Queue 0/1 Register (BM_EGRSS_RATE_00_01) . 370 Buffer Manager Port 0 Egress Rate Priority Queue 2/3 Register (BM_EGRSS_RATE_02_03) . 371 Buffer Manager Port 1 Egress Rate Priority Queue 0/1 Register (BM_EGRSS_RATE_10_11) . 372 Buffer Manager Port 1 Egress Rate Priority Queue 2/3 Register (BM_EGRSS_RATE_12_13) . 373 Buffer Manager Port 2 Egress Rate Priority Queue 0/1 Register (BM_EGRSS_RATE_20_21) . 374 Buffer Manager Port 2 Egress Rate Priority Queue 2/3 Register (BM_EGRSS_RATE_22_23) . 375 Buffer Manager Port 0 Default VLAN ID and Priority Register (BM_VLAN_MII) . 376 Buffer Manager Port 1 Default VLAN ID and Priority Register (BM_VLAN_1) . 377 Buffer Manager Port 2 Default VLAN ID and Priority Register (BM_VLAN_2) . 378 Buffer Manager Port 0 Ingress Rate Drop Count Register (BM_RATE_DRP_CNT_SRC_MII) . 379 Buffer Manager Port 1 Ingress Rate Drop Count Register (BM_RATE_DRP_CNT_SRC_1) . 380 Buffer Manager Port 2 Ingress Rate Drop Count Register (BM_RATE_DRP_CNT_SRC_2) . 381 Buffer Manager Interrupt Mask Register (BM_IMR) . 382 Buffer Manager Interrupt Pending Register (BM_IPR) . 383 13.3.3.26.1Ingress Rate Table Registers .340 13.3.4 Buffer Manager CSRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 356 Chapter 14 Operational Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 385 14.1 Absolute Maximum Ratings*. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.2 Operating Conditions* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.3 Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.4 DC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.5 AC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.5.1 Equivalent Test Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.5.2 Reset and Configuration Strap Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.5.3 Power-On Configuration Strap Valid Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.5.4 Microwire Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.5.5 SPI Slave Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.6 Clock Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 385 385 386 387 388 388 389 390 391 392 393 Chapter 15 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 394 15.1 15.2 128-VTQFP 128-VTQFP Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 394 128-XVTQFP 128-XVTQFP Package Outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 396 Chapter 16 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 398 SMSC LAN9313/LAN9313i 9 DATASHEET Revision 1.6 (08-18-09) Three Port 10/100 Managed Ethernet Switch with MII Datasheet List of Figures Figure 2.1 Figure 2.2 Figure 3.1 Figure 3.2 Figure 5.1 Figure 6.1 Figure 6.2 Figure 6.3 Figure 6.4 Figure 6.5 Figure 6.6 Figure 6.7 Figure 6.8 Figure 6.9 Figure 7.1 Figure 7.2 Figure 7.3 Figure 7.4 Figure 8.1 Figure 8.2 Figure 8.3 Figure 8.4 Figure 8.5 Figure 8.6 Figure 8.7 Figure 8.8 Figure 8.9 Figure 8.10 Figure 8.11 Figure 8.12 Figure 8.13 Figure 8.14 Figure 8.1 Figure 8.2 Figure 8.3 Figure 8.4 Figure 8.5 Figure 9.1 Figure 9.2 Figure 9.3 Figure 9.4 Figure 9.5 Figure 9.6 Figure 10.1 Figure 10.2 Figure 13.1 Figure 13.2 Figure 14.1 Figure 14.2 Figure 14.3 Figure 14.4 Figure 14.5 Internal LAN9313/LAN9313i Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 System Block Diagrams - MAC/PHY Modes of Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . 25 LAN9313 LAN9313 128-VTQFP 128-VTQFP Pin Assignments (TOP VIEW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 LAN9313/LAN9313i 128-XVTQFP 128-XVTQFP Pin Assignments (TOP VIEW) . . . . . . . . . . . . . . . . . . . . 27 Functional Interrupt Register Hierarchy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Switch Fabric CSR Write Access Flow Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Switch Fabric CSR Read Access Flow Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 ALR Table Entry Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Switch Engine Transmit Queue Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Switch Engine Transmit Queue Calculation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 VLAN Table Entry Structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Switch Engine Ingress Flow Priority Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Switch Engine Ingress Flow Priority Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Hybrid Port Tagging and Un-tagging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Port x PHY Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 100BASE-TX 100BASE-TX Transmit Data Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 100BASE-TX 100BASE-TX Receive Data Path. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Direct Cable Connection vs. Cross-Over Cable Connection . . . . . . . . . . . . . . . . . . . . . . . . . 95 EEPROM Access Flow Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 I2C Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 I2C EEPROM Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 I2C EEPROM Byte Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 I2C EEPROM Sequential Byte Reads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 I2C EEPROM Byte Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 EEPROM ERASE Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 EEPROM ERAL Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 EEPROM EWDS Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 EEPROM EWEN Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 EEPROM READ Cycle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 EEPROM WRITE Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 EEPROM WRAL Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 EEPROM Loader Flow Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 SPI Reads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 SPI Writes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 I2C Slave Addressing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 I2C Slave Reads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 I2C Slave Writes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 MII Mux Management Path Connections - MAC Mode Unmanaged . . . . . . . . . . . . . . . . . . 128 MII Mux Management Path Connections - MAC Mode SMI Managed . . . . . . . . . . . . . . . . 129 MII Mux Management Path Connections - MAC Mode I2C/SPI Managed . . . . . . . . . . . . . 130 MII Mux Management Path Connections - PHY Mode Unmanaged . . . . . . . . . . . . . . . . . . 131 MII Mux Management Path Connections - PHY Mode SMI Managed . . . . . . . . . . . . . . . . . 132 MII Mux Management Path Connections - PHY Mode I2C/SPI Managed . . . . . . . . . . . . . . 133 IEEE 1588 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 IEEE 1588 Message Time Stamp Point. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 LAN9313/LAN9313i Base Register Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 Example SWITCH_MAC_ADDRL, SWITCH_MAC_ADDRH, and EEPROM Setup . . . . . . 203 Output Equivalent Test Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 388 nRST Reset Pin Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 389 Power-On Configuration Strap Latching Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 390 Microwire Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 391 SPI Slave Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 392 Revision 1.6 (08-18-09) 10 DATASHEET SMSC LAN9313/LAN9313i Three Port 10/100 Managed Ethernet Switch with MII Datasheet Figure 15.1 Figure 15.2 Figure 15.3 Figure 15.4 LAN9313 LAN9313 128-VTQFP 128-VTQFP Package Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LAN9313 LAN9313 128-VTQFP 128-VTQFP Recommended PCB Land Pattern. . . . . . . . . . . . . . . . . . . . . . . . . . LAN9313/LAN9313i 128-XVTQFP 128-XVTQFP Package Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . LAN9313/LAN9313i 128-XVTQFP 128-XVTQFP Recommended PCB Land Pattern . . . . . . . . . . . . . . . . SMSC LAN9313/LAN9313i 11 DATASHEET 394 395 396 397 Revision 1.6 (08-18-09) Three Port 10/100 Managed Ethernet Switch with MII Datasheet List of Tables Table 1.1 Buffer Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table 1.2 Register Bit Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Table 2.1 LAN9313/LAN9313i Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Table 3.1 LAN Port 1 Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Table 3.2 LAN Port 2 Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Table 3.3 LAN Port 1 & 2 Power and Common Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Table 3.4 LAN Port 0(External MII) Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Table 3.5 Dedicated Configuration Strap Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Table 3.6 EEPROM Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Table 3.7 Serial Management Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Table 3.8 Miscellaneous Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Table 3.9 PLL Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Table 3.10 Core and I/O Power and Ground Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Table 3.11 No-Connect Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Table 4.1 Reset Sources and Affected LAN9313/LAN9313i Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Table 4.2 Soft-Strap Configuration Strap Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Table 4.3 Hard-Strap Configuration Strap Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Table 6.1 Switch Fabric Flow Control Enable Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Table 6.2 Spanning Tree States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Table 6.3 Typical Ingress Rate Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Table 6.4 Typical Broadcast Rate Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Table 6.5 Typical Egress Rate Settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Table 7.1 Default PHY Serial MII Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Table 7.2 4B/5B Code Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Table 7.3 PHY Interrupt Sources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 Table 8.1 I2C/Microwire Master Serial Management Pins Characteristics. . . . . . . . . . . . . . . . . . . . . . 101 Table 8.2 I2C EEPROM Size Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 Table 8.3 Microwire EEPROM Size Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 Table 8.4 Microwire Command Set for 7 Address Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 Table 8.5 Microwire Command Set for 9 Address Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 Table 8.6 Microwire Command Set for 11 Address Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 Table 8.7 EEPROM Contents Format Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 Table 8.8 EEPROM Configuration Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 Table 8.9 SPI / I2C Slave Serial Management Pins Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 Table 8.10 Supported SPI Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 Table 9.1 SMI Frame Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 Table 9.2 MII Management Frame Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 Table 10.1 IEEE 1588 Message Type Detection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 Table 10.2 Time Stamp Capture Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 Table 10.3 PTP Multicast Addresses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 Table 10.4 Typical IEEE 1588 Clock Addend Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 Table 12.1 LED Operation as a Function of LED_CFG[9:8] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 Table 13.1 System Control and Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 Table 13.2 SWITCH_MAC_ADDRL, SWITCH_MAC_ADDRH, and EEPROM Byte Ordering . . . . . . . . 202 Table 13.3 Switch Fabric CSR to SWITCH_CSR_DIRECT_DATA Address Range Map . . . . . . . . . . . . 204 Table 13.4 Virtual PHY MII Serially Adressable Register Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 Table 13.5 Emulated Link Partner Pause Flow Control Ability Default Values . . . . . . . . . . . . . . . . . . . . 219 Table 13.6 Emulated Link Partner Default Advertised Ability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 Table 13.7 Port 1 & 2 PHY MII Serially Adressable Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .