L9826 DIN40839 ISO7637 - Datasheet Archive

 

Octal Low-Side Driver for resistive and inductive loads with serial/parallel input control, output protection and diagnostic

 

L9826 L9826 Octal Low-Side Driver for resistive and inductive loads with serial/parallel input control, output protection and diagnostic OUTPUTS CURRENT CAPABILITY UP TO 450mA RON = 2.2 at TJ = 25°C PARALLEL CONTROL INPUTS FOR OUTPUTS 1 AND 2 SPI CONTROL FOR OUTPUTS 1 TO 8 RESET FUNCTION WITH RESET SIGNAL AT NRES PIN OR UNDERVOLTAGE AT VCC INTRINSIC OUTPUT VOLTAGE CLAMPING AT TYP. 50V OVERCURRENT SHUTDOWN AT OUTPUTS 3 TO 8 SHORT CIRCUIT CURRENT LIMITATION AND SELECTIVE THERMAL SHUTDOWN AT OUTPUTS 1 AND 2 OUTPUT STATUS DATA AVAILABLE ON THE SPI SO20 (16+2+2) Table 1. Order Codes Part Number Package L9826 L9826 SO20 DESCRIPTION The L9826 L9826 is a Octal Low-Side Driver Circuit, dedicated for automotive applications. Output voltage clamping is provided for flyback current recirculation, when inductive loads are driven. Chip Select and Serial Peripheral Interface for outputs control and diagnostic data transfer. Parallel Control inputs for two outputs. BLOCK DIAGRAM VCC VCC NON1 OUT1 1 3 S 2 IOL Latch / Driver Q1 R Overtemperature Detection + Fault Latch Diag1 - VDG CH1 NON2 CLK VCC SDI CH2 Output Latch VCC SPI Interface NCS Q2 Diag2 Shift Register VCC V CC SDO OUT3 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 VCC Reset Q3 S Latch / Driver IOL R + Diag1 Diag3 Diag2 Diag3 Diag4 Q4 Diag5 Diag4 Diag6 Diag7 Q5 Diag8 Diag5 - VDG CH3 CH4 CH5 Q6 Diag6 Reset Undervoltage RESET CH6 Q7 Diag7 CH7 Q8 Diag8 GND NRES OUT2 CH8 OUT4 OUT5 OUT6 OUT7 OUT8 GND April 2004 1/12 L9826 L9826 PIN FUNCTION N° Pin Description 1 Out 6 output 6 2 Out 1 output 1 3 NRes asynchronous reset 4 NCS chip select (active low) 5 GND device ground 6 GND device ground 7 NON1 control input 1 8 SDO serial data output 9 Out 8 output 8 10 Out 3 output 3 11 Out 5 output 5 12 Out 2 output 2 13 SDI serial data input 14 CLK serial clock 15 GND device ground 16 GND device ground 17 NON2 control input 2 18 VCC supply voltage 19 Out 7 output 7 20 Out 4 output 4 PIN CONNECTIONS (Top view) OUT6 1 20 OUT4 OUT1 2 19 OUT7 nRES 3 18 Vcc NCS 4 17 NON2 GND 5 16 GND GND 6 15 GND NON1 7 14 CLK SDO 8 13 SDI OUT8 9 12 OUT2 OUT3 10 11 OUT5 PINCON_L9826 L9826 2/12 L9826 L9826 ABSOLUTE MAXIMUM RATINGS For voltages and currents applied externally to the device Symbol VCC Parameter Test Condition Max. Unit -0.3 7 V -0.3 7 V -20 20 mA Continuous output voltage -0.7 45 V Output current 2) -2 1.0 A 10 mJ Supply voltage Min. Typ. Inputs and data lines (NONx, NCS, CLK, SDI, nRes) VIN Voltage (NONx, NCS, CLK, SDI, nRes) IIN Protection diodes current 1) T 1ms Outputs (Out1 . Out8) VOUTc IOUT EOUTcl Output clamp energy IOUT 150mA Notes: 1. All inputs are protected against ESD according to MIL 883C; tested with HBM at 2KV. It corresponds to a dissipated energy E 0,2mJ. 2. Transient pulses in accordance to DIN40839 DIN40839 part 1, 3 and ISO 7637 Part 1, 3. For currents determined within the device: Symbol Parameter Test Condition Min. Typ. Max. Unit Output current (Out1, Out2) ILIM A Output current (Out3 . Out8) ISCB A Outputs (Out1 . Out8) IOUT I OUTi i = 1-8 Total average-current all outputs Tamb = 60°C 2.0 A 3) 3. When operating the device with short circuit at more than 2 outputs at the same time, damage due to electrical overstress may occur. THERMAL DATA Symbol Parameter Test Condition Min. Typ. 150 Max. 165 Unit Thermal shutdown TJSC Thermal shutdown threshold °C Thermal resistance RthjA-one Single output (junction ambient) 90 °C/W RthjA-all All outputs (junction ambient) 75 °C/W Rthj-pin Junction to Pin 18 °C/W 3/12 L9826 L9826 ELECTRICAL CHARACTERISTCS (4.5V VCC 5,5V; -40°C TJ 150°C; unless otherwise specified) Symbol Parameter Test Condition Min. Typ. Max. Unit Supply voltage IccSTB Standby current without load (nRes = Low) 70 µA IccOPM Operating mode IOUT1 . 8 = 500mA SPI - CLK = 3MHz NCS = LOW SDO no load 5 mA ICC during reverse output current Iout = -2A 100 mA Undervoltage Reset Reset of all registers and disable of all outputs 3 4 V ICC VDDRES Inputs (NONx. NCS, CLK, SDI, nRes) VINL Low level -0.3 0.2·VCC V VINH High level 0.7·VCC VCC+0,3 V Vhyst Hysteresis voltage IIN Input current 0.85 NONx, NCS, CLK, SDI VIN = VCC V 10 NRES (VIN = 0V) -10 50 RIN Pullup resistance (NONx, NCS, CLK, SDI) Pulldown resistance (NRes) CIN Input capacitance Guaranteed by design µA µA 250 k 10 pF Serial data outputs VSDOH High output level ISDO = -4mA VSDOL Low output level ISDO = 3,2mA ISDOL Tristate leakage current NCS = high; 0V VSDO VCC CSDO Output capacitance VCC -0.4 V 0.4 V 10 µA fSDO = 300kHz, Guaranteed by design 10 pF IOUTL1 - 8 Leakage current OUTx = OFF; VOUTx = 25V; VCC = 5V 100 µA IOUTL1 - 8 Leakage current OUTx = OFF; VOUTx = 16V; VCC = 5V 100 µA IOUTL1 - 8 Leakage current OUTx = OFF; VOUTx = 16V; VCC = 1V 10 µA 62 V 3.0 -10 Outputs OUT 1 . 8 Vclp RDSon 4/12 Output clamp voltage 1mA Iclp Ioutp; Itest = 10mA with correlation On resistance OUT 1 . 8 IOUT = 250mA; Tj = +150°C 45 L9826 L9826 ELECTRICAL CHARACTERISTCS (continued) Symbol COUT Parameter Output capacitance Test Condition Min. Typ. Unit 300 VOUT = 16V; f = 1MHz guaranteed by design Max. pF Outputs short circuit protection ISBC Overcurrent shutoff threshold OUT3 . OUT8 0.45 1.1 A ILIM Short circuit current limitation OUT1; OUT2 0.5 1.1 A tSCB Delay shutdown 12 µs 0.32·V 0.4·VC V CC C 0.2 3,0 Diagnostics VDG Diagnostic threshold voltage IOL Open load detection sink current Vout = VDG 20 100 µA tdf Diagnostic detection filter time for output 1 & 2 on each diagnostic condition 15 50 µs Outputs timing tdon1 Turn ON delay of OUT 1 and 2 NON1, 2 = 50% to VOUT = 0,9·Vbat NCS = 50% to VOUT = 0,9·Vbat (VBAT = 16V, RL = 500) 5 µs tdon2 Turn ON delay of OUT 3 to 8 NCS = 50% to VOUT = 0,9·Vbat (VBAT = 16V, RL = 500) 10 µs tdoff Turn OFF delay of OUT 1 to 8 NCS = 50% to VOUT = 0,1·Vbat NON1, 2 = 50% to VOUT = 0,1·Vbat (VBAT = 16V, RL = 500) 10 µs dUon1/dt Turn ON voltage slew-rate For output 3 to 8; 90% to 30% of Vbat; RL = 500; Vbat = 16V 0.7 3.5 V/µs dUon2/dt Turn ON voltage slew-rate For output 1 and 2; 90% to 30% of Vbat; RL = 500; Vbat = 16V 2 10 V/µs dUoff1/dt Turn OFF voltage slew-rate For output 1 to 8; 30% to 90% of Vbat; RL = 500; Vbat = 16V 2 10 V/µs dUoff2/dt Turn OFF voltage slew-rate For output 1 to 8; 30% to 80% of Vbat; RL = 500; Vbat = 0.9 · Vclp 2 15 V/µs 3 MHz Serial diagnostic link (Load capacitor at SDO = 100pF) fclk Clock frequency tclh Minimum time CLK = HIGH 160 ns tcll Minimum time CLK = LOW 160 ns tpcld Propagation delay CLK to data at SDO valid tcsdv NCS = LOW to data at SDO active 50% duty cycle 4,9V VCC 5,1V 100 ns 100 ns 5/12 L9826 L9826 ELECTRICAL CHARACTERISTCS (continued) Symbol Parameter Test Condition Min. Typ. Max. Unit Setup time CLK to NCS change H/L 100 ns 100 ns 20 ns tsclch CLK low before NCS low thclcl CLK change L/H after NCS = low tscld SDI input setup time CLK change H/L after SDI data valid thcld SDI input hold time SDI data hold after CLK change H/L tsclcl CLK low before NCS high 150 ns thclch CLK high after NCS high 150 ns tpchdz NCS L/H to output data float NCS pulse filter time 20 100 ns ns Multiple of 8 CLK cycles inside NCS period FUNCTIONAL DESCRIPTION General The L9826 L9826 integrated circuit features 8 power low-side-driver outputs. Data is transmitted to the device using the Serial Peripheral Interface, SPI protocol. Outputs 1 and 2 can be controlled parallel or serial. The power outputs features voltage clamping function for flyback current recirculation and are protected against short circuit to Vbat. The diagnostics recognizes two outputs fault conditions: 1) overcurrent for outputs 3 to 8 , overcurrent and thermal overload for outputs 1 and 2 in switch-on condition and 2) open load or short to GND in switch-off condition for all outputs. The outputs status can be read out via the serial interface. The chip internal reset is a OR function of the external nRes signal and internally generated undervoltage nRes signal. Output Stages Control Each output is controlled with its latch and with common reset line, which enables all eight outputs. Outputs 1 and 2 can be controlled also by its NON1, NON2 inputs. It allows PWM control independently on the SPI. These inputs features internal pull-up resistors to assure that the outputs are switched off, when the inputs are open. The control data are transmitted via the SDI input, the timing of the serial interface is shown in Fig. 1. The device is selected with low NCS signal and the input data are transferred into the 8 bit shift register at every falling CLK edge. The rising edge of the NCS latches the new data from the shift register to the drivers. 6/12 L9826 L9826 Figure 1. Timing of the Serial Interface. NCS tsclch thclcl tclh tcll tsclcl thclch CLK tcsdv tpcld SDO tpchdz not defined D8 D1 thcld tscld SDI D8 D7 D1 The SPI register data are transferred to the output latch at rising NCS edge. The digital filter between NCS and the output latch ensures that the data are transferred only after 8 CLK cycles or multiple of 8 CLK cycles since the last NCS falling edge. The NCS changes only at low CLK. Outputs Control Tables : Outputs 1, 2: Outputs 3 to 8: NON1, 2 1 0 0 1 SPI-bit 1, 2 0 0 1 1 SPI-bit 3 . 8 0 1 Output 1, 2 off on on on Output 3 . 8 off on Figure 2. Output Control register structure MSB Q2 LSB Q4 Q6 Q8 Q1 Q3 Q5 Q7 Control-bit output 7 Control-bit output 5 Control-bit output 3 Control-bit output 1 Control-bit output 8 Control-bit output 6 Control-bit output 4 Control-bit output 2 7/12 L9826 L9826 Power outputs characteristics for flyback current, outputs short circuit protection and diagnostics For output currents flowing into the circuit the output voltages are limited. The typical value of this voltage is 50V. This function allows that the flyback current of a inductive load recirculates into the circuit; the flyback energy is absorbed in the chip. Output short circuit protection for outputs 3 to 8 (dedicated for loads without inrush current): when the output current exceeds the short circuit threshold, the corresponding output overload latch is set and the output is switched off immediately. Output short circuit protection for outputs 1 and 2 (dedicated for loads with inrush current, as lamps): when the load current would exceed the short circuit limit value, the corresponding output goes in a current regulation mode. The output current is determined by the output characteristics and the output voltage depends on the load resistance. In this mode high power is dissipated in the output transistor and its temperature increases rapidly. When the power transistor temperature exceeds the thermal shutdown threshold, the overload latch is set and the corresponding output switched off. For the load diagnostic in output off condition each output features a diagnostic current sink, typ 60µA. Diagnostics The output voltage at all outputs is compared with the diagnostic threshold, typ 0,38 · VCC. Outputs 1 and 2 features dedicated fault latches. The output status signal is filtered and latched. The fault latches are cleared during NCS low. The latch stores the status bit, so the first reading after the error occurred might be wrong. The second reading is right. Diagnostic Table for outputs 1 and 2 in parallel controlled mode: Output 1, 2 Output-voltage Status-bit Output-mode off > DG-threshold high correct operation off < DG-threshold low fault condition 2) on < DG-threshold high correct operation on > DG-threshold low fault condition 1) Fault condition 1) "output short circuit to Vbat" : the output was switched on and the voltage at the output exceeds the diagnostics threshold. The output operates in current regulation mode or has been switched off due to thermal shutdown. The status bit is low. Fault condition 2) "open load" or "output short circuit to GND" : the output is switched off and the voltage at the output drops below the diagnostics threshold, because the load current is lower than the output diagnostic current source, the load is interrupted. The diagnostic bit is low. For outputs 3 to 8 the output status signals, are fed directly to the SPI register. Diagnostic Table for outputs 1 to 8 in SPI controlled mode: Output 1 . 8 Status-bit off > DG-threshold high correct operation off < DG-threshold low fault condition 2) on < DG-threshold low correct operation on 8/12 Output-voltage Output-mode > DG-threshold high fault condition 1) L9826 L9826 The fault condition 1) "output short circuit to Vbat" : the output was switched on and the voltage at the output exceeded the diagnostics threshold due to overcurrent, the output overload latch was set and the output has been switched off. The diagnostic bit is high. Fault condition 2) "open load" or "output short circuit to GND" is the same as of outputs 1 and 2. At the falling edge of NCS the output status data are transferred to the shift register. When NSC is low, data bits contained in the shift register are transferred to SDO output et every rising CLK edge. Figure 3. The Pulse Diagram to Read the Outputs Status Register NCS CLK SDO SDI MSB 6 MSB 5 6 4 5 3 4 2 3 1 2 LSB 1 LSB Figure 4. The Structure of the Outputs Status Register MSB LSB Diag2Diag4 Diag6 Diag8 Diag1Diag3 Diag5Diag7 Diagnostic-bit output 7 Diagnostic-bit output 5 Diagnostic-bit output 3 Diagnostic-bit output 1 Diagnostic-bit output 8 Diagnostic-bit output 6 Diagnostic-bit output 4 Diagnostic-bit output 2 9/12 L9826 L9826 APPLICATION INFORMATION The typical application diagram is shown in Fig. 5. Figure 5. Typical Application Circuit Diagram for the L9826 L9826 Circuit. VCC VOLTAGE REGULATOR VBAT VCC VCC NON1 OUT1 1 3 S 2 IOL Latch / Driver Q1 R Overtemperature Detection + Fault Latch Diag1 - VDG CH1 NON2 CLK VCC SDI CH2 Output Latch VCC SPI Interface NCS Q2 Diag2 Shift Register VCC VCC SDO OUT3 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 nRES VCC Reset IOL R - VDG CH3 CH4 CH5 Q7 Diag7 CH7 Q8 Diag8 Reset CH6 CH8 OUT4 OUT5 OUT6 OUT7 OUT8 R, L loads GND NRES SDI SDO Latch / Driver Q6 Diag6 L9826 L9826 CLOCK S + Undervoltage RESET NCS2 . 7 Q3 Diag1 Diag3 Diag2 Diag3 Diag4 Q4 Diag5 Diag4 Diag6 Diag7 Q5 Diag8 Diag5 GND µP OUT2 L9826 L9826 For higher current driving capability two outputs of the same kind can be paralleled. In this case the maximum flyback energy should not exceed the limit value for single output. The immunity of the circuit with respect to the transients at the output is verified during the characterization for Test Pulses 1, 2 and 3a, 3b, DIN40839 DIN40839 or ISO7637 ISO7637 part 3. The Test Pulses are coupled to the outputs with 200pF series capacitor. All outputs withstand testpulses without damage. The correct function of the circuit with the Test Pulses coupled to the outputs is verified during the characterization for the typical application with R = 30 to 100, L= 0 to 600mH loads. The Test Pulses are coupled to the outputs with 200pF series capacitor. 10/12 L9826 L9826 mm inch DIM. MIN. TYP. MAX. MIN. TYP. MAX. A 2.35 2.65 0.093 0.104 A1 0.10 0.30 0.004 0.012 B 0.33 0.51 0.013 0.200 C 0.23 0.32 0.009 0.013 D (1) 12.60 13.00 0.496 0.512 E 7.40 7.60 0.291 OUTLINE AND MECHANICAL DATA 0.299 e 1.27 0.050 H 10.0 10.65 0.394 0.419 h 0.25 0.75 0.010 0.030 L 0.40 1.27 0.016 0.050 k ddd 0° (min.), 8° (max.) 0.10 0.004 (1) "D" dimension does not include mold flash, protusions or gate burrs. Mold flash, protusions or gate burrs shall not exceed 0.15mm per side. SO20 0016022 D 11/12 L9826 L9826 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. 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