ICL7126 ICL7106 ICL7126CPL ICL7126RCPL 1-888-INTERSIL 45/RC CREF33 ICL8069

® January 1998 Features S IG N DES NEW t FO R r D t er a N D E 7 1 3 6 o r t C e n /t s c E O M M e e I C L l S up po i l . c

ICL7126 ICL7126 ® January 1998 Features S IG N DES NEW t FO R r D t er a N D E 7 1 3 6 o r t C e n /t s c E O M M e e I C L l S up po i l . c om S REC rs ic a . i nt e N OT ch n r Te or w w w ou SIL t act con -INTER 8 1- 88 Description · 8,000 Hours Typical 9V Battery Life · Guaranteed Zero Reading for 0V Input on All Scales · True Polarity at Zero for Precise Null Detection · 1pA Typical Input Current · True Differential Input and Reference · Direct LCD Display Drive - No External Components Required · Pin Compatible With the ICL7106 ICL7106 · Low Noise - Less Than 15µVP-P · On-Chip Clock and Reference · Low Power Dissipation Guaranteed Less Than 1mW · No Additional Active Circuits Required Ordering Information PART NUMBER 3 1/2 Digit, Low Power, Single-Chip A/D Converter TEMP. RANGE ( oC) PKG. NO. PACKAGE ICL7126CPL ICL7126CPL 0 to 70 40 Ld PDIP E40.6 ICL7126RCPL ICL7126RCPL 0 to 70 40 Ld PDIP (Note) E40.6 The ICL7126 ICL7126 is a high performance, very low power 31/2-digit, A/D converter. All the necessary active devices are contained on a single CMOS IC, including seven segment decoders, display drivers, reference, and clock. The ICL7126 ICL7126 is designed to interface with a liquid crystal display (LCD) and includes a backplane drive. The supply current of 100µA is ideally suited for 9V battery operation. The ICL7126 ICL7126 brings together an unprecedented combination of high accuracy, versatility, and true economy. It features auto-zero to less than 10µV, zero drift of less than 1µV/oC, input bias current of 10pA maximum, and rollover error of less than one count. The versatility of true differential input and reference is useful in all systems, but gives the designer an uncommon advantage when measuring load cells, strain gauges and other bridge-type transducers. And finally the true economy of single power operation allows a high performance panel meter or multi-meter to be built with the addition of only 10 passive components and a display. The ICL7126 ICL7126 can be used as a plug-in replacement for the ICL7106 ICL7106 in a wide variety of applications, changing only the passive components. NOTE: "R" indicates device with reversed leads. Pinout ICL7126 ICL7126 (PDIP) TOP VIEW V+ 1 40 OSC 1 D1 2 39 OSC 2 C1 3 38 OSC 3 B1 4 37 TEST A1 5 36 REF HI F1 6 35 REF LO G1 7 E1 8 34 CREF+ 33 CREF- D2 9 32 COMMON C2 10 31 IN HI B2 11 30 IN LO A2 12 29 A-Z F2 13 28 BUFF E2 14 27 INT D3 15 26 V- B3 16 25 G2 (10's) F3 17 24 C3 E3 18 23 A3 (1000) AB4 19 22 G3 POL (MINUS) 20 21 BP/GND (1's) (10's) (100's) CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2002. All Rights Reserved 1 (100's) File Number 3084.3 ICL7126 ICL7126 Absolute Maximum Ratings Thermal Information Supply Voltage V+ to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15V Analog Input Voltage (Either Input) (Note 1) . . . . . . . . . . . . V+ to VReference Input Voltage (Either Input) . . . . . . . . . . . . . . . . . V+ to VClock Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TEST to V+ Thermal Resistance (Typical, Note 2) JA (oC/W) PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300oC Operating Conditions Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . .0oC to 70oC CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 1. Input voltages may exceed the supply voltages provided the input current is limited to ±100µA. 2. JA is measured with the component mounted on an evaluation PC board in free air. Electrical Specifications TA = 25oC, VREF = 100mV, fCLOCK = 48kHz (Notes 1, 3) PARAMETER TEST CONDITIONS MIN TYP MAX UNITS -000.0 ±000.0 +000.0 Digital Reading 999 999/100 0 1000 Digital Reading SYSTEM PERFORMANCE Zero Input Reading V IN = 0.0V, Full Scale = 200mV Ratiometric Reading V lN = VREF , VREF = 100mV Rollover Error -VIN = +VlN 200mV Difference in Reading for Equal Positive and Negative Inputs Near Full Scale - ±0.2 ±1 Counts Linearity Full Scale = 200mV or Full Scale = 2V Maximum Deviation from Best Straight Line Fit (Note 5) - ±0.2 ±1 Counts Common Mode Rejection Ratio VCM = ±1V, VIN = 0V, Full Scale = 200mV (Note 5) - 50 - µV/V Noise V IN = 0V, Full Scale = 200mV (Peak-To-Peak Value Not Exceeded 95% of Time) (Note 5) - 15 - µV Leakage Current Input V lN = 0V (Note 5) - 1 10 pA Zero Reading Drift V lN = 0V, 0oC To 70oC (Note 5) - 0.2 1 µV/oC Scale Factor Temperature Coefficient VIN = 199mV, 0oC To 70oC, (Ext. Ref. 0ppm/×oC) (Note 5) - 1 5 ppm/oC V+ Supply Current V IN = 0V (Does Not Include COMMON Current) - 70 100 µA COMMON Pin Analog Common Voltage 25k Between Common and Positive Supply (With Respect to + Supply) 2.4 3.0 3.2 V Temperature Coefficient of Analog Common 25k Between Common and Positive Supply (With Respect to + Supply) (Note 5) - 80 - ppm/oC Peak-To-Peak Segment Drive Voltage Peak-To-Peak Backplane Drive Voltage V+ = to V- = 9V (Note 4) 4 5.5 6 V Power Dissipation Capacitance vs Clock Frequency - 40 - pF NOTES: 3. Unless otherwise noted, specifications are tested using the circuit of Figure 1. 4. Back plane drive is in phase with segment drive for `off' segment, 180 degrees out of phase for `on' segment. Frequency is 20 times conversion rate. Average DC component is less than 50mV. 5. Not tested, guaranteed by design. 2 ICL7126 ICL7126 Typical Application Schematics + IN - 9V - + 750 R5 R1 240k 1M 0.047µF A3 23 BP 21 20 POL C3 24 17 F3 G3 22 G2 25 16 B3 19 AB4 V- 26 15 D3 18 E3 INT 27 14 E2 A-Z 29 BUFF 28 IN HI 31 DISPLAY 13 F2 0.01 0.22µF C3 IN LO 30 COM 32 CREF+ 34 REF LO 35 TEST 37 C2 R2 C 1 0.1µF REF HI 36 OSC 3 38 180k OSC 2 39 OSC 1 40 R4 10k C4 50pF CREF- 33 R3 180k C5 B1 A1 F1 G1 E1 D2 4 5 6 7 8 9 12 A2 C1 3 11 B2 D1 2 10 C2 V+ 1 ICL7126 ICL7126 C1 = 0.1µF C2 = 0.22µF C3 = 0.047µF C4 = 50pF C5 = 0.01µF R1 = 240k R2 = 180k R3 = 180k R4 = 10k R5 = 1M DISPLAY FIGURE 1. ICL7126 ICL7126 TEST CIRCUIT AND TYPICAL APPLICATION WITH LCD DISPLAY COMPONENTS SELECTED FOR 200mV FULL SCALE + SET REF = 100.0mV 9V - + IN R1 R5 240k 1M C5 C3 0.15µF INT 27 V- 26 G2 25 C3 24 A3 23 G3 22 BP 21 15 D3 16 B3 17 F3 18 E3 19 AB4 20 POL DISPLAY 14 E2 BUFF 28 A-Z 29 IN LO 30 0.33µF C2 R2 180k 0.01 IN HI 31 COM 32 CREF- 33 REF HI 36 C1 0.1µF REF LO 35 TEST 37 OSC 3 38 OSC 2 39 180k OSC 1 40 R4 10k C4 50pF CREF+ 34 R3 A1 F1 G1 E1 D2 5 6 7 8 9 13 F2 B1 4 12 A2 C1 3 11 B2 D1 2 10 C2 V+ 1 ICL7126 ICL7126 DISPLAY FIGURE 2. ICL7126 ICL7126 CLOCK FREQUENCY 16kHz, 1 READING/S 3 C1 = 0.1µF C2 = 0.33µF C3 = 0.5µF C4 = 50pF C5 = 0.01µF R1 = 240k R2 = 180k R3 = 180k R4 = 10k R5 = 1M ICL7126 ICL7126 (Continued) + IN - 9V - Typical Application Schematics + 750 R5 1M 0.047µF BP 21 20 POL C3 24 17 F3 A3 23 G2 25 16 B3 G3 22 V- 26 15 D3 19 AB4 INT 27 14 E2 A-Z 29 DISPLAY BUFF 28 180k C3 13 F2 0.01 IN HI 31 C2 R2 IN LO 30 COM 32 CREF- 33 C1 0.1µF REF LO 35 TEST 37 REF HI 36 OSC 3 38 180k OSC 2 39 OSC 1 40 R4 10k C4 50pF CREF+ 34 R3 0.22µF C5 18 E3 R1 240k B1 A1 F1 G1 E1 D2 4 5 6 7 8 9 12 A2 C1 3 11 B2 D1 2 10 C2 V+ 1 ICL7126 ICL7126 DISPLAY FIGURE 3. CLOCK FREQUENCY 48kHz, 3 READINGS/S 4 C1 = 0.1µF C2 = 0.22µF C3 = 0.047µF C4 = 50pF C5 = 0.01µF R1 = 240k R2 = 180k R3 = 180k R4 = 10k R5 = 1M ICL7126 ICL7126 Design Information Summary Sheet · DISPLAY COUNT · OSCILLATOR FREQUENCY V IN COUNT = 1000 × -V R EF fOSC = 0.45/RC 45/RC COSC > 50pF; ROSC > 50k fOSC (Typ) = 48kHz · CONVERSION CYCLE · OSCILLATOR PERIOD tCYC = tCL0CK x 4000 tCYC = tOSC x 16,000 when fOSC = 48KHz; tCYC = 333ms tOSC = RC/0.45 · INTEGRATION CLOCK FREQUENCY fCLOCK = fOSC /4 · COMMON MODE INPUT VOLTAGE · INTEGRATION PERIOD (V- + 1V) < VlN < (V+ - 0.5V) tINT = 1000 x (4/fOSC) · AUTO-ZERO CAPACITOR · 60/50Hz REJECTION CRITERION 0.01µF < C AZ < 1µF tINT /t60Hz or tlNT / t50Hz = Integer · REFERENCE CAPACITOR · OPTIMUM INTEGRATION CURRENT 0.1µF < CREF < 1µF IINT = 4µA · VCOM · FULL-SCALE ANALOG INPUT VOLTAGE Biased between V+ and V-. VlNFS (Typ) = 200mV or 2V · VCOM V+ - 2.8V · INTEGRATE RESISTOR Regulation lost when V+ to V- < 6.8V. If VCOM is externally pulled down to (V + to V -)/2, the VCOM circuit will turn off. VINFS R IN T = -I IN T · ICL7126 ICL7126 POWER SUPPLY: SINGLE 9V · INTEGRATE CAPACITOR V+ - V- = 9V Digital supply is generated internally VTEST V+ - 4.5V ( t I NT ) ( IINT ) C IN T = -VI NT · ICL7126 ICL7126 DISPLAY: LCD · INTEGRATOR OUTPUT VOLTAGE SWING Type: Direct drive with digital logic supply amplitude. ( t I NT ) ( IINT ) V IN T = -C I NT · VINT MAXIMUM SWING: (V- + 0.5V) < VINT < (V+ - 0.5V), VINT (Typ) = 2V 5 ICL7126 ICL7126 Typical Integrator Amplifier Output Waveform (INT Pin) AUTO ZERO PHASE (COUNTS) 2999 - 1000 SIGNAL INTEGRATE PHASE FIXED 1000 COUNTS DE-INTEGRATE PHASE 0 - 1999 COUNTS TOTAL CONVERSION TIME = 4000 x tCLOCK = 16,000 x tOSC Detailed Description Specifically the digital reading displayed is: Analog Section VIN Display Count = 1000 - . VREF Figure 4 shows the Functional Diagram of the Analog Section for the ICL7126 ICL7126. Each measurement cycle is divided into three phases. They are (1) auto-zero (A-Z), (2) signal integrate (INT) and (3) de-integrate (DE). Differential Input The input can accept differential voltages anywhere within the common mode range of the input amplifier, or specifically from 0.5V below the positive supply to 1V above the negative supply. In this range, the system has a CMRR of 86dB typical. However, care must be exercised to assure the integrator output does not saturate. A worst case condition would be a large positive common mode voltage with a near full-scale negative differential input voltage. The negative input signal drives the integrator positive when most of its swing has been used up by the positive common mode voltage. For these critical applications the integrator output swing can be reduced to less than the recommended 2V fullscale swing with little loss of accuracy. The integrator output can swing to within 0.5V of either supply without loss of linearity. Auto-Zero Phase During auto-zero three things happen. First, input high and low are disconnected from the pins and internally shorted to analog COMMON. Second, the reference capacitor is charged to the reference voltage. Third, a feedback loop is closed around the system to charge the auto-zero capacitor CAZ to compensate for offset voltages in the buffer amplifier, integrator, and comparator. Since the comparator is included in the loop, the A-Z accuracy is limited only by the noise of the system. In any case, the offset referred to the input is less than 10µV. Signal Integrate Phase During signal integrate, the auto-zero loop is opened, the internal short is removed, and the internal input high and low are connected to the external pins. The converter then integrates the differential voltage between IN HI and IN LO for a fixed time. This differential voltage can be within a wide common mode range: up to 1V from either supply. If, on the other hand, the input signal has no return with respect to the converter power supply, IN LO can be tied to analog COMMON to establish the correct common mode voltage. At the end of this phase, the polarity of the integrated signal is determined. De-Integrate Phase The final phase is de-integrate, or reference integrate. Input low is internally connected to analog COMMON and input high is connected across the previously charged reference capacitor. Circuitry within the chip ensures that the capacitor will be connected with the correct polarity to cause the integrator output to return to zero. The time required for the output to return to zero is proportional to the input signal. 6 ICL7126 ICL7126 CREF RINT + REF HI 34 36 CREF V+ REF LO 35 A-Z CREF33 CREF33 28 A-Z 1 A-Z - + 2.8V DE- DE+ INT 27 INTEGRATOR - 31 INT CINT 29 + 1µA IN HI CAZ BUFFER V+ 6.2V INPUT HIGH A-Z A-Z COMMON DE+ 32 - DE- INPUT LOW A-Z AND DE(±) IN LO 30 INT COMPARATOR + N 26 V- FIGURE 4. ANALOG SECTION OF ICL7126 ICL7126 7 + TO DIGITAL SECTION ICL7126 ICL7126 Differential Reference V+ The reference voltage can be generated anywhere within the power supply voltage of the converter. The main source of common mode error is a roll-over voltage caused by the reference capacitor losing or gaining charge to stray capacity on its nodes. If there is a large common mode voltage, the reference capacitor can gain charge (increase voltage) when called up to de-integrate a positive signal but lose charge (decrease voltage) when called up to de-integrate a negative input signal. This difference in reference for positive or negative input voltage will give a roll-over error. However, by selecting the reference capacitor large enough in comparison to the stray capacitance, this error can be held to less than 0.5 count worst case. (See Component Value Selection.) V+ REF HI 6.8V ZENER REF LO ICL7126 ICL7126 IZ V- FIGURE 5A. Analog COMMON V+ This pin is included primarily to set the common mode voltage for battery operation or for any system where the input signals are floating with respect to the power supply. The COMMON pin sets a voltage that is approximately 2.8V more negative than the positive supply. This is selected to give a minimum end-of-life battery voltage of about 6.8V. However, analog COMMON has some of the attributes of a reference voltage. When the total supply voltage is large enough to cause the zener to regulate (