500 MILLION PARTS FROM 12000 MANUFACTURERS

DATASHEET SEARCH ENGINE

Search Stock

Shift+Click on the column header for multi-column sorting 
Part
Manufacturer
Supplier
Stock
Best Price
Price Each
Ordering
Part : MPCC-2-24-2-L-64-24.00-D-NUS Supplier : Samtec Manufacturer : Samtec Stock : 6 Best Price : $32.00 Price Each : $32.00
Part : MPCC-2-24-2-L-64-24.00-S Supplier : Samtec Manufacturer : Samtec Stock : 6 Best Price : $20.00 Price Each : $20.00
Shipping cost not included. Currency conversions are estimated. 

L64240

Catalog Datasheet MFG & Type PDF Document Tags

TCC-1W

Abstract: fir02 BARREL1.Q-BARREL1.4 BARREL0.0-BARRELÛ.4 10 2 164240,1 L64240.1 L64240.2 164240,2 L64240.3 L64240.3 L64240.0 164240,1 L64240.2 L64240.3 A ll A ll A ll A ll A ll A ll A ll A ll A ll A ll L6424Q.Q L64240.1 L64240.2 , disabled. tPRS = 45 ns (L64240-16) o r 55 ns (L64240-12) W C M IL, w h e n fo rm a t a d ju st enabled. *A , : Commercial (TA = 0°C to 70°C, VDD = 4.75 V to 5.25 V) L64240-20 Symbol tCYCLE tPW H tPW L tDIS tDIH tPRS , * 5 2 8* 2 8* L64246-15 M ax *A ssum e fo rm a t a dju st b lo ck disabled. tPRS = 35 ns (L64240-20
-
OCR Scan
TCC-1W fir02 L64210/L64211 155-P MIL-STD-883C

images of pin configuration of IC 74138

Abstract: L64240 : Commercial (TA = 0°C to 70°C, VDD = 4.75 V to 5.25 V) L64240-20 L64240-15 Symbol Parameter Min Max Min , .39 Initialization of System DI0-DI3 DI4-DI7 (sxu) (uxu) L64240.2 (8x8) DI0-DI3 DI4-0I7 (sxu) (uxu) L64240.3 (8x8) D0 , .0-BARREL1.4 10 L64240.1 BARREL0.0-BARREL0.4 2 L64240.2 BARREL1 0-BARREL1.4 10 L64240.2 BARREL0.0-BARREL1.4 2 L64240.3 BARREL1.0-BARREL1.4 10 L64240.3 BARRELO.O-BARRELO.4 2 L64240.0 0 UTD EL.0-0 UTD EL.3 1 1-cycle delay introduced in variable length delay. L64240.1 OUTDEL.O-OUTDEL.3 2 2-cycle delay. L64240.2
-
OCR Scan
images of pin configuration of IC 74138 DI-74 L64240-15IWCCOM 74138 decoder 18 x 16 barrel shifter 4 bit barrel shifter circuit for left shift opera
Abstract: (TA =0°C to 70°C, VDD = 4.75 V to 5.25 V) L64240-15 L64240-20 Symbol tCYCLE Parameter , format adjust block disabled. tP R S = 45 ns (L64240-16) or 55 n$ (L64240-12) W C M IL, when format , . Non-zero value useful for format adjustment. L64240.2 BARREL0.0-BARREL1.4 2 L64240.3 BARREL1.0-BARREL1.4 10 L64240.3 BARRELO.O-BARRELO.4 2 L64240.0 0UTDEL0-0UTDEL.3 L64240.1 0UTDEL.0-0UTDEL.3 2 2-cycle delay. L64240.2 OUTOEL.O-OUTDEL.3 3 3 -
OCR Scan
Abstract: V| L64240-20 Symbol tCYCLE Parameter Minimum Clock (CLK) Cycle Time M in L64240-15 , 25 5 7 "Assume format adjust block disabled. tPfiS = 35 ns (L64240-20) or 45 ns (L64240-15 , V) L64240-12 L64240-16 Parameter Symbol tCYCLE M ax Min Minimum Clock (CLK , ) DI4-DI7 (u x u) DI0-DI3 (s X u) L64240.Q (8 x8 ) PR L64240.1 (8 x8 ) DO PR DO , L64240.2 BARREL1.0â'" BARREL1.4 10 L64240.2 BARREL0.0-BARREL1.4 2 L64240.3 BARREL1 -
OCR Scan
0S013

CXD 4191

Abstract: H9925 parallel and are driving the output buses or when driving the bidirectional lines of the L64240 before the L64240 has been initial­ ized. RESET Sets the internal shift registers to access the first
LSI Logic
Original
L64032 CXD 4191 H9925 jd 1803 b 107 jd 1803 data jd 1803 19 B H14000 DB05-000019-00
Abstract: output busses or when driving the bidirectional lines of the L64240 before the L64240 has been -
OCR Scan
L64212 L64200
Abstract: b u s e s o r w h e n d riving the b id irectio nal line s of the L64240 b efore the L64240 h a s b -
OCR Scan

95Pin

Abstract: Processor DIO DM L64220 L64230 DO DI6 L64240 DI7 Example No. 1: L64210 Configured for 4-Bit Operation
-
OCR Scan
95Pin

D037

Abstract: L64240 _ Blank From Camera or Frame Buffer 8^ L64220 L64230 L64240 Example No. 1: L64210 Configured
-
OCR Scan
D037 L64211
Abstract: L64220, L64230 and L64240 is shown. In this system, the processors can be connected in any order and -
OCR Scan
L64210/164211

SE115

Abstract: to control the interconnection of the L64220, L64230 and L64240 is shown. In this system, the
-
OCR Scan
SE115 L64270 L64270-40 L64270-30 Z43/I011 DI10/I010 DI40/I040