L64210/L64211 L64210 L64211 L64200 L64210/11 L64210-20 LS4211-20 L64210-15 - Datasheet Archive

 

LSI L64210/L64211 Variable-Length Video Shift Registers Description The L64210 and L64211 are two high-speed Variable-Length

 

LOGIC LSI L64210/L64211 L64210/L64211 Variable-Length Video Shift Registers Description The L64210 L64210 and L64211 L64211 are two high-speed Variable-Length Video Shift Registers. These devices can be used individually or as video line delays for the L64200 L64200 series filter processors. The L64210 L64210 provides four individual 8-bit shift registers, each with a length of up to 1032, and is packaged in a 68-pin Plastic Leaded Chip Carrier or Ceramic Pin Grid Array. The L64211 L64211 provides eight individual 8-bit shift registers, each with a length adjustable to 516 and is packaged in a 120-pin Plastic or Ceramic Pin Grid Array. H L64210 L64210 Chip Features Variable-length video shift register Acts as a variable-length line delay, reformatting serial (raster-scanned video) data into a 2-D video signal for image processing Can work individually or with any of the LSI Logic L64200 L64200 series filter processors L64210 L64210 contains four separate 8-bit shift registers whose length can be varied from 24 to 1032 L64211 L64211 contains eight separate 8-bit shift registers whose length can be varied from 12 to 516 High data rates Commercial Military 20 MHz 16 MHz 15 MHz 12 MHz Control available to blank (force to zero) data outputs during horizontal video blanking intervals Control available to blank (force to zero) data inputs, which could be used to ignore invalid data during vertical video blanking intervals Input data can be sent to all eight internal shift registers simultaneously L64210 L64210 is available in a 68-pin PLDCC (Plastic Leaded Chip Carrier) or CPGA (Ceramic Pin Grid Array) package L64211 L64211 is available in a 120-pin PPGAor CPGA (Plastic or Ceramic Pin Grid Array) package Architecture The L64211 L64211 contains eight individual 8-bit variable-length shift registers which can be used as video line delays. The L64210 L64210 has every other shift register output connected to external package pins and effectively has four individual 8-bit shift registers. The length of the shift registers is controlled by the value residing in the level-triggered LENGTH latch register controlled by an active LOW WE input. The length of each of the eight shift registers of the L64211 L64211 can be varied from 12 to 516 bits by loading the LENGTH register according to: Number of Shifts = (4* LENGTH) + 8. where 0 is an illegal input. Since the L64210 L64210 internally cascades two shift registers together, each of the resulting four registers can be varied from 24 to 1032 bits long, and its length is determined by the equation: Number of Shifts = (8 • LENGTH) + 16. ©1987,1988,1989, 1990, 1991 LSI Logic Corporation. All rights reserved. 32 Powered by ICminer.com Electronic-Library Service CopyRight 2003 L64210/L64211 L64210/L64211 Variable-Length Video Shift Registers LSI logic Architecture (Continued) In a video or image-processing system, the length of each shift register is normally setto the number of pixels per video line. When used in this fashion (as a video line delay or as a front end to any of the LSI Logic real-time image-processing chips), the line delay ouputs the pixels vertically adjacent to (in the same column as) the input pixel. In the case of the L64211 L64211,the outputs of the eight line delays will be eight pixels in a vertical line. To accommodate the horizontal and vertical blanking periods of a video signal, provision is made to disable the shift register. The SHIFT/ HOLD input causes the system clock to be disabled^ ie data is not shifted. The MASK and FLUSH controls allow the outputs and inputs respectively of the device to be forced to zero. Block Diagram weD-^ CI.O-CI 6 I LENGTH SHIFT/HOLD D~ CLKO- o FLUSH O- DlO^- o =0 I SHIFT/HOLD To All Shift Registers Variable-Length Shift Register Delay = (4 • LENGTH} + 8 Variable-Length Shift Register Delay = (4 • LENGTHI + 8 Variable-Length Shift Register Delay = (4 • LENGTHI + 8 Variable-Length Shift Register Delay = (4 «LENGTHI+ 8 Variable-Length Shift Register Delay = (4 • LENGTH) + 8 Variable-Length Shift Register Delay = (4 • LENGTH) + 8 Variable-Length Shift Register Delay = (4 • LENGTHI + 8 ] , Variable-Length Shift Register J Delay = (4-LENGTHI+ 8 ALLLINESl 33 Powered by ICminer .com Electronic-Library Service CopyRight 2003 L64210/L64211 L64210/L64211 Variable-Length Video Shift Registers lsi logic Pin Listing and Description DI Eight-bit input data bus. Data inputs are loaded into the first stage of the shift register at the rising edge of CLK while SHIFT/HOLD is HIGH. CLK System clock. Active at the rising edge. FLUSH When FLUSH is LOW, zeros are forced into the shift register. This action overrides the data on Dl bus. If FLUSH is connected to the vertical blanking signal in a video system, the input will be blank during the blanking period. CI O to CI.7 Control input bus. This bus is common to all L64200 L64200 series devices. On the L64210/11 L64210/11, the bus feeds into two control registers, LENGTH and MASK. SHIFT/HOLD Disables the action of the CLK input and forces the shift register outputs LOW when MASK is LOW. When SHIFT/HOLD is connected to the horizontal blanking signal in a video system, data will not be loaded during the horizontal blanking period. DOXY Data output buses where X and Y represent the output bus number and bit numbers, respectively. The L64210 L64210 has 4 8-bit output buses, while the L64211 L64211 has 8 8-bit output buses. ALLLINES When ALLLINES is LOW, data from Dl bus (overridden by FLUSH) is fed into all eight shift registers simultaneously. ALLLINES is intended as a test function; in normal operation it should be held HIGH. WE Active-LOW Write Enable for the CjJLENGTH and MASK control) inputs. When WE is LOW, new data is written into the LENGTH and MASK registers. LENGTH becomes active at the next rising edge of CLK. TEST Internal LSI Logic test input. Should be held HIGH or left unconnected by user. Loading of Control Words The L64210 L64210 and L64211 L64211 are configured by writing an 8-bit control word to the LENGTH and MASK registers. The LENGTH register, accessed through CI.O - CI.6 is a number between 0 and 127 which controls the length of the individual shift registers. For the L64210 L64210 each of the four shift registers will be of length (8 • LENGTH) + 16. For the L64211 L64211 the length of each of the eight shift registers will be (4 «LENGTH)+ 8. The value written into LENGTH becomes active on the next rising edge of the clock after it has been written. The value in this register must be greater than zero for correct operation. The MASK register, which is accessed through CI.7, controls the masking of the outputs. If a zero is written into MASK then the effect of the SHIFT/HOLD input will be to force all data outputs to zero. If a one is written into MASK then the effect of the SHIFT/HOLD input will be to freeze the current value on the outputs. Both the MASKjnd LENGTH registers are loaded when WE is LOW. Blanking Periods Typically the horizontal blanking signal of a video system will be tied to the SHIFT/HOLD input. This disables the clock and hence disables data input to the device, during the blanking period. If MASK has been set LOW then this will also have the effect of setting to zero -ie blanking -the data outputs. If MASK is LOW and SHIFT/HOLD is taken LOW then the delay from SHIFT/HOLD going LOW to the data outputs being valid (ie zero) is 20 ns. When SHIFT/HOLD is taken HIGH again, the delay to data outputs being valid is 15 ns. The vertical blanking signal might be connected to the FLUSH input, causing zeros to be input into the device during this period. This means that any spurious data during vertical blanking will be ignored, leaving only zero data values between frames. For operation as a standard shift register, both FLUSH and MASK should be held high. 34 Powered by ICminer .com Electronic-Library Service CopyRight 2003 lsi logic: L64210/L64211 L64210/L64211 Variable-Length Video Shift Registers Data Retention The shift registers in the L64210 L64210 and L64211 L64211 are constructed from DRAM cells. These ORAM cells are refreshed only when a new data value is written into that location. In the worst case, ie with the shift registers set to their maximum length, there will be 512 cycles, plus anytime when SHIFT/HOLD is held LOW, between successive writes to a location. The DRAM used will retain data for 200 usees. Care must be taken to ensure that the cumulative time between accesses does not exceed this limit. The maximum values given in the AC Switching Characteristics for tCYCLE and tWSL are an example of meeting this requirement: the total time elapsed between successive writes to the same memory location is given by (512 • 200) + 100,000 = 200,400 ns. In practice, the designer may trade off the parameters of LENGTH, tCYCLE and tWSL as long as this 200 usee limit is observed. AC Timing Coefficient/Control Section WE tSC -tWPE(min)- Input Timing SHIFT/HOLD CLK FLUSH Input into SR DO Data Shifted a Total of (8 • LENGTH) +16 OR (A • LENGTHI +8 Cycles L64210 L64210 L64211 L64211 35 Powered by ICminer.com Electronic-Library Service CopyRight 2003 L64210/L64211 L64210/L64211 Variable-Length Video Shift Registers lsi lock: AC Switching Characteristics: Commercial (TA = 0°C to 70°C, VDD = 4.75 Vto 5.25 V) Symbol Parameter L64210-20 L64210-20 LS4211-20 LS4211-20 L64210-15 L64210-15 L64211-15 L64211-15 tCYCLE Clock cycle time 50 400* 65 400* tPWH(min) Min clock pulse width HIGH 20 30 tPWL(min) Mir clock pulse width LOW 20 30 tSI Input data set-uptime 15 20 tHI Input data hold time 5 10 tWPE WE pulse width 20 30 tSC CI input set-up time 10 15 tHC CI input hold time 10 15 tSF FLUSH input set-up time 15 20 tHF Flush input hold time 5 10 tOD Output delay time 33 40 tSSH SHIFT/HOLD set-uptime 2 3 tHSH SHIFT/HOLD hold time 0 0 tWSL SHIFT/HOLD width LOW 200,000* 200,000 AC Switching Characteristics: Military (TA = 55°C to 125°C, VDD = 4.5 V to 5.5 V) Symbol Parameter L64210-16 L64210-16 L64211-16 L64211-16 L64210-12 L64210-12 L54211-12 L54211-12 tCYCLE Clock cycle time 60 400* 75 400* tPWH(min) Min clock pulse width HIGH 25 35 tPWLIminl Min clock pulse width LOW 25 35 tSI Input data set-up time 20 25 tHI Input data hold time 10 15 tWPE WE pulse width 30 35 tSC CI input set-up time 15 20 tHC CI input hold time 15 20 tSF FLUSH input set-up time 20 25 tHF Flush input hold time 10 15 tOD Output delay time 35 55 tSSH SHIFT/HOLD set-uptime 3 4 tHSH SHIFT/HOLD hold time 0 0 tWSL SHIFT/HOLD width LOW 200,000* 200,000 All units are in ns, output loading = 50 pF. * Assuming SHIFT/HOLD always HIGH, LENGTH = 127. * Assuming LENGTH = 1 (see text for further information!. 36 Powered by ICminer.com Electronic-Library Service CopyRight 2003 L64210/L64211 L64210/L64211 Variable-Length Video Shift Registers lsi lock: Ordering Characteristics Absolute Maximum Ratings (Reference to GND) Parameter Symbol Limits Unit DC supply voltage VDD -0.3 to +7 V Input voltage VIN -0.3 to VOD + 0.3 V DC input current UN ±10 mA Storage temperature range TSTG -65 to + 150 °C Recommended Operating Conditions Parameter Symbol Limits Unit DC supply voltage VDD +3 to +6 V Operating ambient temperature range TA - 55 to + 125 °C Military Commercial TA 0 to + 70 °c DC Characteristics: Specified at VDD = 5 V over the specified temperature and voltage ranges'" Symbol Parameter Condition Min Typ Max Units VIL Low level input voltage 0.8 V VI H High level input voltage Commercial temperature range Military temperature range 2.0 2.25 V V un Input current VIN = VDD -150 200 HA V0H High level output voltage Comm Mil 2.4 4.5 V I0H = -4 mA -3.2 mA VOL Low level output voltage Comm Mil 0.2 0.4 V I0L = 4 mA 3.2 mA I0S Output short circuit current"1 VDD = Max, VO = VDD 15 130 mA VDD = Max, VO = OV -5 -100 mA IDDQ Quiescent supply current VIN = VDD or VSS 10 mA IDD Operating supply current tCYCLE = 50 ns 300 mA CIN Input capacitance Any Input 5 pF COUT Output capacitance Any Output 10 pF Notes: 1. Military temperature range is -55°C to + 125°C, ± 10% power supply; commercial temperature range is 0°C to 70°C, ±5% power supply. 2. Not more than one output should be shorted at a time. Duration of short circuit test must not exceed one second. 37 Powered by ICminer.com Electronic-Library Service CopyRight 2003 L64210/L64211 L64210/L64211 Variable-Length Video Shift Registers LSI logic: L64210 L64210 Pinout Diagram 68-Pin Plastic Leaded Chip Carrier (PLCC) 302.7 302.6 302.5 302.4 3023 302.2 302.1 302.0 3ND /DO 301.7 301.6 301.5 301.4 301.3 CSI o 9 8 7 6 5 4 3 2 ; 1 ;68 67 66 65 64 63 62 68-Pin Grid Array (PGA) D02.7 D02.6 D02.4 DO 2.2 D02.0 VDD DOt.6 D01.4 D01.2 GND VDD D02.5 D02.3 D02.1 GND D01.7 D01.5 D01.3 D01.1 DO 1.0 D03.1 â-¡03.0 X «- Extra Pin VDD GND D03.3 â-¡03.2 D00.6 D00.7 D03.5 D03.4 Top View D00.4 D00.5 D03.7 â-¡03.6 D00.2 D00.3 GND VDD DOO.O D00.1 Cll CIO VDD GND CI3 CI2 DM DIO CI4 CI5 ALL LINES CI7 TEST GND CLK â-¡I6 DI4 DI3 DI2 CI6 WE FLUSH VDD SHIFT/ HOLD DI7 â-¡I5 GND VDD 38 Powered by ICminer.com Electronic-Library Service CopyRight 2003 L64210/L64211 L64210/L64211 Variable-Length Video Shift Registers LSI logic: L64211 L64211 Pinout Diagram 120-Pin Ceramic Pin Grid Array (CPGA) 1 2 3 4 5 6 7 8 9 10 11 12 13 NC D05.6 D05.5 D05.3 NC D05.0 NC VDD NC NC D03.4 D03.1 003.0 VDD NC DO 5.7 D05.4 D05.2 NC NC NC NC D03.5 D03.3 NC VDD D07.1 D07.0 NC NC NC D05.1 GND D03.7 NC D03.2 NC NC D01.7 D07.4 D07.2 GND X Extra Pin GND D01.6 D01.4 D07.6 D07.5 D07.3 D01.5 D01.3 D01.2 NC NC D07.7 Top View D01.1 DOI.O DOO.O D06.6 NC D06.7 DOO.2 D01.0 D00.1 D06.5 D06.4 VDD D00.6 D00.5 D00.4 GND D06.3 006.1 D02.0 GND D00.7 D06.2 D06.0 CI2 DIO D02.1 VDD CIO CI3 CI5 D04.6 004.3 WE VDD D02.7 TOUT DI4 DI3 D02.3 002.2 CM CI6 ALL LINES 004 4 D04.1 C17 TEST CLK D02.5 DI7 GND DI2 011 CI4 DO 4.7 D04.5 D04.2 D04.0 FLUSH GND SHIFT/ HOLD 002.6 D02.4 DI6 DI5 VDD 39 Powered by ICminer.com Electronic-Library Service CopyRight 2003 lsi logic L64210/L64211 L64210/L64211 Variable-Length Video Shift Registers Application Examples Recommended Application in a Video System Vertical Blank +5V Horizontal Blank From Camera or Frame Buffer FLUSH DOO MASK DOl L64211 L64211 SHIFT/HOLD D06 Dl D07 LSI Logic Video Filter Processor DIO DM L64220 L64220 L64230 L64230 DO DI6 L64240 L64240 DI7 Example No. 1: L64210 L64210 Configured for 4-Bit Operation Eight Individual 1 K x 4 Shift Registers DOO.x DOI.x D02.X D03.X D03.0 Thru D03.3 Fed Into DI4 Thru DI7 Output of Data Output Shift Register Pins 0 DOO.O.DOO.3 1 D01.0.D01.3 2 D02.0.D02.3 3 D03.0.D03.3 4 D00.4.D00.7 5 D01.4.D01.7 6 D02.4. .D02.7 7 D03.4. .D03.7 Powered by ICminer 40 .com Electronic-Library Service CopyRight 2003 lsi logic L64210/L64211 L64210/L64211 Variable-Length Video Shift Registers Application Examples Example No. 2: L64210 L64210 Set-Up for Binary Operation (Continued) 32 Individual 1 K x 1 Shift Registers Output of Data Output Shift Register Pins 0 000.0 1 D01.0 2 002.0 3 D03.0 4 D00.1 * » * * * * 29 001.7 30 D02.7 31 D03.7 41 Powered by ICminer .com Electronic-Library Service CopyRight 2003 L64210/L64211 L64210/L64211 Variable-Length Video Shift Registers lsi logic: Application Examples Example No. 3: Expansion to Larger Shift Example No. 4: Expansion to Larger Shift (Continued) Registers. Eight 1 K x 8 Shift Registers Registers. Four 2 K x 8 Shift Registers Using Two L64210s Using Two L64210s 42 Powered by ICminer.com Electronic-Library Service CopyRight 2003 lsi logic: L64210/L64211 L64210/L64211 Variable-Length Video Shift Registers Application Examples Example No. 5: Expansion to Larger Shift Registers. (Continued) Four 1 K x 16 Shift Registers Using Two L64210s 43 Powered by ICminer.com Electronic-Library Service CopyRight 2003 lsi lock: L64210/L64211 L64210/L64211 Variable-Length Video Shift Registers Packaging 68-pin Plastic Leaded Chip Carrier: See MC Package In Package Selector Guide 68-pin Ceramic Pin Grid Array: See FB Package in Package Selector Guide 120-pin Ceramic Pin Grid Array: See FD Package in Package Selector Guide 120-pin Plastic Pin Grid Array: See ND Package in Package Selector Guide Ordering Information L64210 L64210 L64211 L64211 M -XX T - Speed in MHz Temperature Range/Flow Option C = Commercial (0°C to 70°C) M = Military (-55°C to +125°C), Processed to MIL-STD-883C MIL-STD-883C Level B Package Code G = Ceramic Pin Grid Array N = Plastic Pin Grid Array J = Plastic Leaded Chip Carrier Device Type Video Shift Register 44 Powered by ICminer.com Electronic-Library Service CopyRight 2003