L5993 DIP16 SO16N L5993D BCD60II D97IN765 D97IN783 PIN10 PIN13 L4981A D97IN766 - Datasheet Archive

 

® CONSTANT POWER CONTROLLER PRODUCT PREVIEW CURRENT-MODE CONTROL PWM SWITCHING FREQUENCY UP TO 1MHz LOW START-UP CURRENT

 

L5993 L5993 ® CONSTANT POWER CONTROLLER PRODUCT PREVIEW CURRENT-MODE CONTROL PWM SWITCHING FREQUENCY UP TO 1MHz LOW START-UP CURRENT (< 120µA) CONSTANT OUTPUT POWER VS. SWITCHING FREQUENCY HIGH-CURRENT OUTPUT DRIVE SUITABLE FOR POWER MOSFET (1A) FULLY LATCHED PWM LOGIC WITH DOUBLE PULSE SUPPRESSION PROGRAMMABLE DUTY CYCLE 100% AND 50% MAXIMUM DUTY CYCLE LIMIT PROGRAMMABLE SOFT START PRIMARY OVERCURRENT FAULT DETECTION WITH RE-START DELAY PWM UVLO WITH HYSTERESIS IN/OUT SYNCHRONIZATION LATCHED DISABLE INTERNAL 100ns LEADING EDGE BLANKING OF CURRENT SENSE PACKAGE: DIP16 DIP16 AND SO16N SO16N MULTIPOWER BCD TECHNOLOGY DIP16 DIP16 ORDERING NUMBERS: L5993 L5993 (DIP16 DIP16) L5993D L5993D (SO16) line or DC-DC power supply applications using a fixed frequency current mode control. Based on a standard current mode PWM controller this device includes some features such as programmable soft start, IN/OUT synchronization, disable (to be used for over voltage protection and for power management), precise maximum Duty Cycle Control, 100ns leading edge blanking on current sense, pulse by pulse current limit, overcurrent protection with soft start intervention and "constant power" function for cotrolling throughput power in multisync monitor SMPS. DESCRIPTION This primary controller I.C., developed in BCD60II BCD60II technology, has been designed to implement off BLOCK DIAGRAM SYNC DC DIS 2 VCC DC-LIM 1 RCT SO16N SO16N 15 VREF 8 4 TIMING 25V + 3 14 Vref + - 15V/10V T - - PWM UVLO 9 DIS VC + 2.5V C-POWER + 16 13V 10 BLANKING S OUT Q R PWM OVER CURRENT ISEN SS 13 FAULT SOFT-START + 1.2V VREF OK CLK DIS 11 PGND + 7 2.5V E/A - 2R 1V 5 VFB R 12 SGND 6 COMP D97IN765 D97IN765 December 1998 This is preliminary information on a new product now in development. Details are subject to change without notice. 1/22 L5993 L5993 ABSOLUTE MAXIMUM RATINGS Symbol VCC IOUT Ptot Tj Tstg Parameter Supply Voltage (ICC < 50mA) (*) Output Peak Pulse Current Analog Inputs & Outputs (6,7) Analog Inputs & Outputs (1,2,3,4,5,15,14, 13, 16) Power Dissipation @ Tamb = 70°C (DIP16 DIP16) @ Tamb = 50°C (SO16) Junction Temperature, Operating Range Storage Temperature, Operating Range Value selflimit 1.5 -0.3 to 8 -0.3 to 6 1 0.83 -40 to 150 -55 to 150 Unit V A V V W W °C °C Value 80 120 Unit °C/W °C/W (*) maximum package power dissipation limits must be observed PIN CONNECTION SYNC 1 16 C-POWER RCT 2 15 DC-LIM DC 3 14 DIS VREF 4 13 ISEN VFB 5 12 SGND COMP 6 11 PGND SS 7 10 OUT VCC 8 9 VC D97IN783 D97IN783 THERMAL DATA Symbol Rth j-amb Parameter Thermal Resistance Junction -Ambient (DIP16 DIP16) Thermal Resistance Junction -Ambient (SO16) PIN FUNCTIONS N. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Name SYNC RCT DC VREF VFB COMP SS VCC VC OUT PGND SGND ISEN DIS DC-LIM 16 C-POWER 2/22 Function Synchronization. A synchronization pulse terminates the PWM cycle and discharges Ct Oscillator pin for external C t, Rt components Duty Cycle control 5.0V +/-1.5% reference voltage at 25°C Error Amplifier Inverting input Error Amplifier Output Soft start pin for external capacitor Css Supply for internal "Signal" circuitry Supply for Power section High current totem pole output Power ground Signal ground Current sense Disable. It must never be left floating. Tie to SGND if not used. Connecting this pin to Vref, DC is limited to 50%. If it is left floating or grounded no limitation is imposed Constant Power vs. Switching Frequency. Connect a capacitor to SGND. The pin must be connected to VREF if not used. L5993 L5993 ELECTRICAL CHARACTERISTICS (VCC = 15V; Tj = 0 to 105°C; unless otherwise specified.) Symbol Parameter Test Condition Min. Typ. Max. 4.925 Unit REFERENCE SECTION Tj = 25°C; IO = 1mA 5.0 5.075 V VCC = 12 to 20V; Tj = 25°C 2.0 10 mV Load Regulation TS Output Voltage Line Regulation VRef IO = 1 to 10mA; Tj = 25°C 2.0 10 mV Temperature Stability 0.4 Total Variation Short Circuit Current Vref = 0V Power Down/UVLO IOS Line, Load, Temperature 4.80 VCC = 8.5V; Isink = 0.5mA 5.0 mV/°C 5.130 V 150 mA 0.2 0.5 V 100 100 105 107 kHz kHz 0 0 % % 30 OSCILLATOR SECTION Initial Accuracy R T = 13.3k; CT = 1nF at T j = 25°C at Tj = 0 to 70°C 95 93 Duty Cycle pin 3 = 0,7V, pin 15 = Vref pin 3 = 0.7V, pin 15 = OPEN Duty Cycle pin 3 = 3.2V, pin 15 = Vref pin 3 = 3.2V, pin 15 = OPEN 47 93 Duty Cycle Accuracy pin 3 = 2.79V, pin 15 = OPEN 75 80 Oscillator Ramp Peak 2.8 Oscillator Ramp Valley 0.75 % % 85 % 3.0 3.2 V 0.9 1.05 V 0.2 3.0 2.42 2.5 2.58 µA V 60 90 dB 85 dB ERROR AMPLIFIER SECTION Input Bias Current VFB to GND Input Voltage VCOMP = VFB GOPL Open Loop Gain VCOMP = 2 to 4V SVR Supply Voltage Rejection VCC = 12 to 20V V OL Output Low Voltage Isink = 2mA, VFB = 2.7V VOH Output High Voltage Isou rce = 0.5mA, VFB = 2.3V Output Source Current VCOMP > 4V, VFB = 2.3V Output Sink Current VCOMP > 1.1V, VFB = 2.7V VI IO V 3 mA 5 6 0.5 1.3 2 6 mA 1.7 4 MHz 8 Unit Gain Bandwidth SR 1.1 V/µs Slew Rate V PWM CURRENT SENSE SECTION Ib Input Bias Current Maximum Input Signal VCOMP = 5V 3 Isen = 0 IS 0.92 Delay to Output 15 µA 1.0 1.08 V 70 SS Charge Current ISSD SS Discharge Current SS Saturation Voltage 3.15 V/V 20 26 µA VSS = 0.6V VSSSAT ns 3 14 ISSC 100 2.85 Gain SOFT START DC = 0% VSSCLAMP µA 10 0.6 SS Clamp Voltage V 7 V 100 ns LEADING EDGE BLANKING Internal Masking Time OUTPUT SECTION V OL Output Low Voltage VOH Output High Voltage IO = 250mA 1.0 V VOUT CLAMP Output Clamp Voltage IO = 20mA; VCC = 12V 10 10.5 V IO = 200mA; VCC = 12V 9 10 V 13 V IO = 5mA; VCC = 20V 3/22 L5993 L5993 ELECTRICAL CHARACTERISTICS (continued.) Symbol Parameter Test Condition Min. Typ. Max. Unit OUTPUT SECTION Collector Leakage VCC = 20V VC = 24V 2 20 µA Fall Time C O = 1nF C O = 2.5nF 20 35 60 ns ns Rise Time C O = 1nF C O = 2.5nF 50 70 100 ns ns UVLO Saturation VCC = 0V to VCCON; Isink = 10mA 1.0 V SUPPLY SECTION VCCON Startup voltage 14 15 16 V VCCOFF Minimum Operating Voltage 9 10 11 V 4.5 5 40 75 120 µA 9 13 mA 7.0 10 mA 25 30 V Vhys ULVO Hysteresis IS Start Up Current Before Turn-on at: VCC = VCCON - 0.5V Iop Operating Current C T = 1nF,RT = 13.3k, CO =1nF Iq Quiescent Current (After turn on), CT = 1nF, R T = 13.3k, C O = 0nF Zener Voltage VZ SYNCHRONIZATION SECTION I8 = 20mA 21 V Master Operation V1 Clock Amplitude ISOURCE = 0.8mA 4 I1 Clock Source Current Vclock = 3.5V 3 V 7 mA Slave Operation Sync Pulse V1 Low Level 1 V High Level V VSYNC = 3.5V Sync Pulse Current I1 3.5 0.5 mA OVER CURRENT PROTECTION Fault Threshold Voltage Vt DISABLE SECTION 1.1 V 2.5 2.6 V VCC = 15V 330 µA Pin1 = open Shutdown Current ISH 1.3 2.4 Shutdown threshold 1.2 2.35 V CONSTANT POWER Reference for E/A clamp V 16 Figure 1. Quiescent current vs. input voltage. Iq [mA] 30 350 V14 = 0, Pin2 = open Tj = 25°C 20 Iq [µA] 300 8 250 6 200 4 150 0.2 0.15 V14 = Vref Tj = 25 °C 100 0.1 50 0.05 0 0 0 4/22 Figure 2. Quiescent current vs. input voltage (after disable). 4 8 12 16 Vcc [V] 20 24 28 0 4 8 12 16 Vcc [V] 20 24 L5993 L5993 Figure 3. Quiescent current vs. input voltage. Iq [m A ] 9 .0 Figure 4. Quiescent current vs. input voltage and switching frequency. Iq [m A ] 36 V 1 4 = 0 , V 5 = V re f R t = 4 .5 K o h m ,T j = 2 5 °C 8 .5 C o = 1 n F, T j = 2 5 ° C 30 D C = 0% 1M hz 24 5 00K hz 300K hz 8 .0 1M H z 18 100K hz 50 0K H z 12 30 0K H z 7 .5 1 00K H z 6 7 .0 0 8 10 12 14 16 18 V c c [V ] 20 22 24 Figure 5. Quiescent current vs. input voltage and switching frequency. 8 10 12 14 16 V cc [ V ] 18 20 22 Figure 6. Reference voltage vs. load current. Vref [V] Iq [mA] 36 5.1 Co = 1nF, Tj = 25°C 30 DC = 100% Vcc=15V 5.05 Tj = 25°C 24 1MHz 18 500K Hz 5 30 0K Hz 4.95 12 10 0KHz 6 4.9 0 0 8 10 12 14 16 Vcc [V] 18 20 5 10 22 15 20 25 Iref [mA] Figure 7. Vref vs. junction temperature. Figure 8. Vref vs. junction temperature. Vref [V]) Vref [V] 5.1 5.1 Vcc = 15V Vcc = 15V 5.05 5.05 Iref= 20mA Iref = 1mA 5 5 4.95 4.95 4.9 -50 -25 0 25 50 Tj (°C) 75 100 125 150 4.9 -50 -25 0 25 50 Tj (°C) 75 100 125 150 5/22 L5993 L5993 Figure 9. Vref SVRR vs. switching frequency. Figure 10. Output saturation. Vsat = V SVRR (dB) [V] 10 16 Vcc = Vc = 15V Vcc=15V 120 14 Vp-p=1V Tj = 25°C 12 80 10 40 8 6 0 1 10 100 1000 fsw (Hz) 0 10000 0.2 0.4 0.6 0.8 Isource [A] 1 1.2 Figure 12. UVLO Saturation Figure 11. Output saturation. Ipin10 [mA] V s at = V [V ] 10 2 .5 50 2 Vcc < Vccon beforeturn-on 40 V c c = Vc = 15 V Tj = 25°C 1 .5 30 1 20 0 .5 10 0 0 0.2 0.4 0 .6 0 .8 1 1 .2 0 0 200 400 Is ink [A ] 600 800 Vpin10 [mV] 1,000 1,200 1,400 Figure 14. Switching frequency vs. temperature Figure 13. Timing resistor vs. switching frequency. fsw (KHz) fsw (KHz) 5000 320 Vcc = 15V, V15 =0V 2000 Rt= 4.5Kohm, Ct = 1nF Tj = 25°C 1000 310 Vcc = 15V, V15=Vref 500 100pF 200 300 220pF 100 470pF 50 20 290 1 nF 2.2nF 5 .6nF 10 10 20 Rt (kohm) 6/22 30 40 280 -50 -25 0 25 50 Tj (°C) 75 100 125 150 L5993 L5993 Figure 15. Switching frequency vs. temperature. Figure 16. Dead time vs Ct. fsw (KHz) 320 Dead time [ns] 1,500 Rt= 4.5Kohm, Ct = 1nF 310 Rt =4.5Kohm V15 = 0V Vcc = 15V, V15= 0 1,200 900 300 V15 = Vref 600 290 300 280 -50 -25 0 25 50 Tj (°C) 75 100 125 150 Figure 17. Maximum Duty Cycle vs Vpin3. 2 4 6 8 Timing capacitor Ct [nF] 10 Figure 18. Delay to output vs junction temperature. DC Control Voltage Vpin3 [V] 3.5 Delay to output (ns) 42 V15 = 0V V15 = Vref 3 40 38 2.5 36 2 34 Rt = 4.5Kohm, 32 Ct = 1nF 1.5 PIN10 PIN10 = OPEN 1V pulse on PIN13 PIN13 30 1 0 10 20 30 40 50 60 70 Duty Cycle [%] 80 90 100 28 -50 -25 0 25 50 75 100 125 150 Tj (°C) Figure 19. E/A frequency response. G [dB] Phase 140 150 120 100 100 80 50 60 0 40 20 0.01 0.1 1 10 100 f (KHz) 1000 10000 100000 7/22 L5993 L5993 CONSTANT POWER FUNCTION Pulse-by-pulse current limitation prevents peak primary current from exceeding a given level. This, in turn, limits the maximum power deliverable to the output or, in other words, the power capability of a converter. The capability, however, depends on switching frequency: for example, in a discontinuous current mode flyback they are just proportional. In SMPS' of raster-scanned CRT displays the switching frequency is usually synchronized to the raster line scan signal of the display in order to increase noise immunity. More and more often, CRT displays are required to operate within a range of different video frequencies (e.g. from 31 kHz to 64 kHz), thus also the switching frequency of the SMPS will vary in that range. In case of some failure, the power throughput may be excessive without necessarily tripping the pulse-by-pulse current limitation circuit because of a high operating frequency. For the sake of safety, it would be then desirable to design the power stage of a converter (power MOSFET, transformer, catch diode) so as to be able to withstand the maximum power throughput under failure conditions. However, this is a considerable increase of size and cost. The "Constant Power" function of the L5993 L5993 allows to overcome this problem. The device changes the threshold of its pulse-by-pulse current limitation circuit so as to maintain fairly constant the power capability of a flyback converter despite the changes of the switching frequency. This is accomplished by clamping the output of the error amplifier (VCOMP) to a value which decreases as the frequency of the signal fed into pin 1 (SYNC) builds up. The frequency-to-voltage conversion needed to achieve this functionality is performed by detecting the peak voltage of the (synchronized) oscillator with a peak-holding circuit. One external capacitor only is required. It is important to point out that shape, amplitude and duration of the synchronization pulses are of no concern with this technique. APPLICATION INFORMATION Detailed Pin Functions Description Pin 1. SYNC (In/Out Synchronization). This function allows the IC's oscillator either to synchronize other controllers (master) or to be synchronized to an external frequency (slave). As a master, the pin delivers positive pulses during the falling edge of the oscillator (see pin 2). In slave operation the circuit is edge triggered. Refer to fig. 21 to see how it works. When several IC work in parallel no master-slave designation is needed because the fastest one becomes automatically the master. During the ramp-up of the oscillator the pin is pulled low by a 600µA internal sink current generator. During the falling edge, that is when the pulse is released, the 600µA pull-down is disconnected. The pin becomes a generator whose source capability is typically 7mA (with a voltage still higher than 3.5V). In fig. 20, some practical examples of synchronizing the L5993 L5993 are given. Pin 2. RCT (Oscillator). A resistor (RT) and a capacitor (CT), connected as shown in fig. 21 set the operating frequency fosc of the oscillator. CT is charged through RT until its voltage reaches 3V, then is quickly internally discharged. As the voltage has dropped to 1V it starts being charged again. The frequency can be established with the aid of fig. 13 diagrams or considering the approximate relationship: fosc 1 CT (0.693 RT + KT) (1) where KT is defined as: 90, V15 = VREF KT = (2) 160 V15 = GND/OPEN and is linked to the duration of the falling edge of the sawtooth: Td 30 10-9 + KT CT (3) Td is also the duration of the sync pulses deliv- Figure 20. Sinchronizing the L5993 L5993. RT SYNC L5993 L5993 1 4 VREF 2 RT RCT L4981A L4981A (MASTER) 16 L5993 L5993 2 17 L5993 L5993 (SLAVE) SYNC 1 18 (a) 4 4 2 RCT CT 8/22 VREF SYNC 1 VREF RCT 2 L5993 L5993 1 (MASTER) RT L4981A L4981A (SLAVE) SYNC SYNC 16 17 18 RCT ROSC COSC CT (b) ROSC CT D97IN766 D97IN766 (c) COSC L5993 L5993 Figure 21. Oscillator and synchronization internal schematic. SYNC 1 VREF 4 R1 D CLAMP RT R R3 RCT 600µA R2 + 2 Q CLK D1 CT 50 D97IN500A D97IN500A ered at pin 1 and defines the upper extreme of the duty cycle range, Dx (see pin 15 for Dx definition and calculation). In case V15 is connected to VREF, however, the switching frequency of the system will be a half f osc . If the IC is to be synchronized to an external oscillator, RT and CT should be selected for a fosc lower than the master frequency in any condition (typically, 10-20% ), depending on the tolerance of RT and CT . Pin 3. DC (Duty Cycle Control). By biasing this pin with a voltage between 1 and 3 V it is possible to set the maximum duty cycle between 0 and the upper extreme Dx (see pin 15). If Dmax is the desired maximum duty cycle, the voltage V3 to be applied to pin 3 is: (2-Dmax) V3 = 5 - 2 (4) Dmax is determined by internal comparison between V3 and the oscillator ramp (see fig. 22), thus in case the device is synchronized to an external frequency fext (and therefore the oscillator amplitude is reduced), (4) changes into: V3 = 5 - 4 exp - Dmax (5) RT CT fext A voltage below 1V will inhibit the driver output stage. This could be used for a not-latched device disable, for example in case of overvoltage protection (see application ideas). Figure 22. Duty cycle control. V REF 4 DC 3 R1 RT 3µA 23K R2 28K RCT 2 + TO PWM LOGIC - CT D97IN711 D97IN711 If no limitation on the maximum duty cycle is required (i.e. DMAX = DX), the pin can be left floating because an internal pull-up (see fig. 22) holds the voltage above 3V. Anyway, to prevent disturbances due to noise pick up, it is recommended to connect the pin to VREF. Pin 4. VREF (Reference Voltage). The device is provided with an accurate voltage reference (5V±1%) able to deliver some mA to an external circuit. A small film capacitor (0.1 µF typ.), connected between this pin and SGND, is recommended to ensure the stability of the generator and to prevent noise from affecting thereference. Before device turn-on, this pin has a sink current capability of 0.5mA. 9/22 L5993 L5993 Pin 5. VFB (Error Amplifier Inverting Input). The feedback signal is applied to this pin and is compared to the E/A internal reference (2.5V). The E/A output generates the control voltage which fixes the duty cycle. The E/A features high gain-bandwidth product, which allows to broaden the bandwidth of the overall control loop, high slew-rate and current capability, which improves its large signal behavior. Usually the compensation network, which stabilizes the overall control loop, is connected between this pin and COMP (pin 6). Figure 23. Regulation characteristic and related quantities VOUT IQpk A D.C.M. C.C.M. 1-2 ·IQpk IQpk(max) B C TON D Pin 6. COMP (Error Amplifier Output). Usually, this pin is used for frequency compensation and the relevant network is connected between this pin and VFB (pin 5). Compensation networks towards ground are not possible since the L5993 L5993 E/A is a voltage mode amplifier (low output impedance). See application ideas for some example of compensation techniques. Pin 7. SS (Soft-Start). At device start-up, a capacitor (Css) connected between this pin and SGND (pin 12) is charged by an internal current generator, ISSC, up to about 7V. During this ramp, the E/A output is clamped by the voltage across Css itself and allowed to rise linearly, starting from zero, up to the steady-state value imposed by the control loop. The maximum time interval during which the E/A is clamped, referred to as soft-start time, is approximately: Tss 3 Rsense IQpk Css ISSC (6) where Rsense is the current sense resistor (see pin 13) and IQpk is the switch peak current (flowing through Rsense), which depends on the output TON(min) D97IN495 D97IN495 ISHORT IOUT(max) IOUT load. Usually, CSS is selected for a TSS in the order of milliseconds. As mentioned before, the soft-start intervenes also in case of severe overload or short circuit on the output. Referring to fig. 23, pulse-by-pulse current limitation is somehow effective as long as the ON-time of the power switch can be reduced (from A to B). After the minimum ON-time is reached (from B onwards) the current is out of control. To prevent this risk, a comparator trips an overcurrent handling procedure, named 'hiccup' mode operation, when a voltage above 1.2V (point C) is detected on current sense input (ISEN, pin 13). Basically, the IC is turned off and then soft-started as long as the fault condition is detected. As a result, the operating point is moved abruptly to D, creating a foldback effect. Fig. 24 illustrates the operation. The oscillation frequency appearing on the soft- Figure 24. Hiccup mode operation. IOUT SHORT ISEN FAULT SS 5V 7V 0.5V Thic 10/22 D98IN986 D98IN986 time L5993 L5993 start capacitor in case of permanent fault, referred to as 'hiccup" period, is approximately given by: 1 Thic 4.5 ISSC + 1 Css (7) ISSD Since the system tries restarting each hiccup cycle, there is not any latchoff risk. "Hiccup" keeps the system in control in case of short circuits but does not eliminate power components overstress during pulse-by-pulse limitation (from A to C). Other external protection circuits are needed if a better control of overloads is required. Pin 8. VCC (Controller Supply). This pin supplies the signal part of the IC. The device is enabled as VCC voltage exceeds the start threshold and works as long as the voltage is above the UVLO threshold. Otherwise the device is shut down and the current consumption is extremely low ( 330 min (Hz) is the minimum synchronizing fre- where min quency. When this function is not used, pin 16 has to be connected directly to pin 4. Considering the ordinary design criteria for the transformer, the circuit usually works well without any adjustment. Anyway, the variations of the maximum power limit on varying the switching frequency and/or the mains voltage can be minimized by modifying one or more of the following parameters: - Primary inductance; - Transformer turns ratio; - Oscillator free-running frequency; - Sense resistor. A trial process is required, involving the parameters that are more practicable to modify. In fact, the optimum behavior is achieved for a specific 13/22 L5993 L5993 combination of the above parameters and depends both on the mains voltage range and the synchronization frequency range. An additional "fine tuning" can be achieved by adding a small DC offset (in the ten mV) on the current sense pin (13, ISEN). For wide range mains applications it is anyway recommended to compensate the propagation delay of the current sense path (PWM comparator + latch + driver) with the circuit shown in the "Application Ideas" section, fig. 41. Layout hints Generally speaking a proper circuitboard layout is vital for correct operation but is not an easy task. Careful component placing, correct traces routing, appropriate traces widths and, in case of high voltages, compliance with isolation distances are the major issues. The L5993 L5993 eases this task by putting two pins at disposal for separate current returns of bias (SGND) and switch drive currents (PGND) The matter is complex and only few important points will be here reminded. 1) All current returns (signal ground, power 14/22 ground, shielding, etc.) should be routed separately and should be connected only at a single ground point. 2) Noise coupling can be reduced by minimizing the area circumscribed by current loops. This applies particularly to loops where high pulsed currents flow. 3) For high current paths, the traces should be doubled on the other side of the PCB whenever possible: this will reduce both the resistance and the inductance of the wiring. 4) Magnetic field radiation (and stray inductance) can be reduced by keeping all traces carrying switched currents as short as possible. 5) In general, traces carrying signal currents should run far from traces carrying pulsed currents or with quickly swinging voltages. From this viewpoint, particular care should be taken of the high impedance points (current sense input, feedback input, .). It could be a good idea to route signal traces on one PCB side and power traces on the other side. 6) Provide adequate filtering of some crucial points of the circuit, such as voltage references, IC's supply pins, etc. R05 10K C09 0.01µF R17 1K C06 5600pF ZD02 5.6V R05 10K R04 470K LF01 Q02 KTC1815Y KTC1815Y C07 1µF C01 0.1µF 7 1 5 2 3 4 ZD01 20V R03 10K C02 0.1µF 15 16 C11 1µF L5993 L5993 14 R13 5.1K Q01 KSP45 KSP45 R01 2.2 6 11 12 13 10 8 R06 27 R12 33K 9 R02 220K D05 BYW13 BYW13 -1000 R18 22K D97IN619 D97IN619 C08 470pF R21 470 C05 470pF R11 1K R09 5.6K R08 22 C04 470µF R10 0.22 R07 47 D02 1N4148 1N4148 D04 RGP100 RGP100 C03 220µF 400V BD01 8 3 7 Q51 TL431 TL431 PC01 R54 1K Q01 STP6 NA60FI NA60FI C10 0.1µF 200V 10 11 13 12 15 14 16 17 D53 D52 R58 1.2K R53 4.7K R55 18K VR51 10K C58 47µF 25V R52 47 C55 470µF 16V C54 220µF 100V C61 0.022µF D56 C56 470µF 25V C57 470µF 25V D55 D54 R51 C53 R19 4.7M R20 4.7M 18 1 R56 100 C59 0.01µF C52 10µF 100V +50V R73 Q73 R71 Q71 Q74 16V NOR R74 R75 OFF -12V SWITCHED 14V SWITCHED 14V UNSWITCHED HEATER CONTROL 6.3V GND 50V H/V DEF. CONTROL SUSPEND OFF Q75 ZD71 16V C74 NOR SUSPEND Q72 R72 C71 C62 100µF 100V 80V APPLICATION IDEAS Here follows a series of ideas/suggestions aimed at SYNC IN P1 AC IM F01 AC 250V T3.15A C11 4700pF 4KV C12 L5993 L5993 either improving performance or solving common application problems of L5993 L5993 based supplies. Figure 31. Typical application circuit for 15" Multisync monitor (70W) 15/22 L5993 L5993 Figure 32. Isolated MOSFET Drive & Current Transformer Sensing in 2-switch Topologies VIN ISOLATION BOUNDARY VC 9 10 OUT L5993 L5993 ISEN 13 12 PGND 11 SGND D97IN769 D97IN769 Figure 33. Low consumption start-up VIN 2.2M 33K STD1NB50-1 STD1NB50-1 T VCC 47K 20V VREF 4 SELF-SUPPLY WINDING 8 L5993 L5993 12 11 D97IN770A D97IN770A Figure 34. Bipolar Transistor Drive VIN VC VCC 9 8 10 13 L5993 L5993 OUT ISEN 11 PGND D97IN771 D97IN771 16/22 L5993 L5993 Figure 35. Typical E/A compensation networks. From VO + 2.5V 1.3mA Ri VFB Rd Cf 2R + 5 - EA R Rf COMP 12 6 SGND Error Amp compensation circuit for stabilizing any current-mode topology except for boost and flyback converters operating with continuous inductor current. From VO + 2.5V 1.3mA RP Ri CP 5 VFB - EA R Rf Cf Rd 2R + 6 COMP 12 SGND D97IN507 D97IN507 Error Amp compensation circuit for stabilizing current-mode boost and flyback topologies operating with continuous inductor current. Figure 36. Feedback with optocoupler VOUT 6 COMP L5993 L5993 5 TL431 TL431 VFB D97IN772 D97IN772 Figure 37. Slope compensation techniques VREF RT I R SLOPE VREF 4 RT RCT 2 CT ISEN RSENSE OUT R RCT I R 2 C SLOPE L5993 L5993 R SLOPE ISEN 12 SGND OPTIONAL 10 CT L5993 L5993 13 4 RSENSE 13 L5993 L5993 12 12 SGND 13 RSLOPE ISEN RSENSE SGND OPTIONAL OPTIONAL D97IN773 D97IN773 17/22 L5993 L5993 Figure 38. Protection against overvoltage/feedbackdisconnection (latched) RSTART RSTART VCC DIS VCC VZ 8 12 8 DIS L5993 L5993 14 11 SGND L5993 L5993 14 12 2.2K PGND 11 SGND D97IN774 D97IN774 PGND D98IN906 D98IN906 Figure 39. Protection against overvoltage/feedback disconnection (not latched) Figure 40. Device shutdown on overcurrent RSTART Ipk VREF 4 max R1 VREF DC VCC 4 14 R2 L5993 L5993 3 11 12 PGND 11 2.5 RSENSE I DIS L5993 L5993 8 12 ISEN 13 RSENSE SGND OPTIONAL D97IN776 D97IN776 D97IN775 D97IN775 Figure 41. Constant power in pulse-by-pulse current limitation (flyback discontinuous) VIN 80 ÷ 400VDC 400VDC Lp R FF 6 OUT R FF = 6·10 10 L5993 L5993 11 PGND 12 13 R·Lp RSENSE ISEN R R SENSE SGND D97IN777 D97IN777 Figure 42. Voltage mode operation. DC 3 L5993 L5993 COMP 6 SGND 12 13 ISEN D97IN778 D97IN778 18/22 · 1- Ipk R2 R1 L5993 L5993 Figure 43. Device shutdown on mains undervoltage. VIN 80÷400VDC 400VDC R1 VREF 4 L5993 L5993 3 5.1 R2 10K 12 SGND 11 PGND D97IN779 D97IN779 Figure 44. Constant power "Fine Tuning". SGND L5993 L5993 12 4 10 13 VREF R ISEN RA RSENSE OPTIONAL D97IN780 D97IN780 Figure 45. Synchronization to flyback pulses (for monitors). SYNC L5993 L5993 4 1K 5.1V 12 SGND D97IN781 D97IN781 Figure 46. Switching frequency halving on absence of sync. signal (for monitor). 1K (R1//R2)·C>> 5.1V SYNC VREF R1 f C 1 f min 1 4 L5993 L5993 R2 DC-LIM 15 12 SGND D97IN782 D97IN782 19/22 L5993 L5993 mm DIM. MIN. a1 0.77 MAX. 0.51 B TYP. inch MIN. TYP. MAX. OUTLINE AND MECHANICAL DATA 0.020 1.65 0.030 0.065 b 0.5 0.020 b1 0.25 0.010 D 20 0.787 E 8.5 0.335 e 2.54 0.100 e3 17.78 0.700 F 7.1 0.280 I 5.1 0.201 L Z 20/22 3.3 0.130 1.27 DIP16 DIP16 0.050 L5993 L5993 mm DIM. MIN. TYP. A a1 inch MAX. MIN. TYP. 1.75 0.1 0.25 a2 MAX. OUTLINE AND MECHANICAL DATA 0.069 0.009 0.004 1.6 0.063 b 0.35 0.46 0.014 0.018 b1 0.19 0.25 0.007 0.010 C 0.5 c1 0.020 45° (typ.) D (1) 9.8 10 0.386 0.394 E 5.8 6.2 0.228 0.244 e 1.27 0.050 e3 8.89 0.350 F (1) 3.8 4 0.150 0.157 G 4.6 5.3 0.181 0.209 L 0.4 1.27 0.016 0.050 M S 0.62 0.024 SO16 Narrow 8°(max.) (1) D and F do not include mold flash or protrusions. Mold flash or potrusions shall not exceed 0.15mm (.006inch). 21/22 L5993 L5993 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics © 1998 STMicroelectronics ­ Printed in Italy ­ All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - France - Germany - Italy - Japan - Korea - Malaysia - Malta - Mexico - Morocco - The Netherlands Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A. http://www.st.com 22/22