L3000N L3030 PLCC44 L3000N/L3030 FLEXIWATT15 L3000NSO D94TL125 PWSO20 L3000 - Datasheet Archive

 

L3030 SUBSCRIBER LINE INTERFACE KIT . . . . . . . . . . . . . . . . PRELIMINARY DATA PROGRAMMABLE DC FEEDING RESIS-TANCE AND

 

L3000N L3000N L3030 L3030 SUBSCRIBER LINE INTERFACE KIT . . . . . . . . . . . . . . . . PRELIMINARY DATA PROGRAMMABLE DC FEEDING RESIS-TANCE AND LIMITING CURRENT (four values available) THREE OPERATING MODES : STAND-BY, CONVERSATION, RINGING NORMAL/BOOST BATTERY, DIRECT/REVERSE POLARITY SIGNALLING FUNCTION (off-hook/GND-key) FILTERED OFF-HOOK DETECTION IN STAND-BY (10ms) QUICK OFF-HOOK DETECTION IN CONVERSATION (< 1ms) FOR LOW DIAL PULSE DETECTION DISTORTION HYBRID FUNCTION RINGING GENERATION WITH QUASI ZERO OUTPUT IMPEDANCE, ZERO CROSSING INJECTION (no ext. relay needed) AND RING TRIP DETECTION AUTOMATIC RINGING STOP WHEN OFFHOOK IS DETECTED PARALLEL AND SERIAL DIGITAL INTERFACES TELETAXE SIGNAL INJECTION (2VRMS/5VRMS) LOW NUMBER OF EXTERNAL COMPONENTS GOOD REJECTION OF THE NOISE ON BATTERY VOLTAGE (20dB at 10Hz and 35dB at 1kHz) POSSIBILITY TO WORK ALSO WITH HIGH COMMON MODE CURRENTS INTEGRATED THERMAL PROTECTION WITH THERMAL OVERLOAD INDICATION SURFACE MOUNT PACKAGE (PLCC44 PLCC44 + PowerSO-20) DESCRIPTION The ST SLIC KIT (L3000N/L3030 L3000N/L3030) is a set of solid state devices designed to integrate main of the functions needed to interface a telephone line. It consists of 2 integrated devices : the L3000N L3000N line interface circuit and the L3030 L3030 control unit. This kit performs the main features of the BORSHT functions : - Battery feed - Ringing - Signalling - Hybrid January 1995 PLCC44 PLCC44 FLEXIWATT15 FLEXIWATT15 PowerSO-20 ORDERING NUMBERS : L3030 L3030 (PLCC44 PLCC44) L3000N L3000N (FLEXIWATT15 FLEXIWATT15) L3000NSO L3000NSO (PowerSO-20) Additional functions, such as battery reversal, extra battery use, line overvoltage sensing and meteringpulse injection are also featured ; most external characteristics, as AC and DC impedances,are programmable with external components. The SLIC injects ringing in balanced mode and for that, as well as for the operation in battery boosted, a positive battery voltage shall be available on the subscriber card. As the right ringing signal amplification both in voltage and in current is provided by SLIC, the ring signal generatorshall only provide a low level signal (0.285Vrms). This kit is fabricated using a 140V Bipolar technology for L3000N L3000N and a 12V Bipolar I2L technology for L3030 L3030. L3030 L3030 is available PLCC44 PLCC44 and L3000N L3000N in both FLEXIWATT15and PowerSO-20 for surface mount application. This kit is suitable for all the following applications: C.O. (Central Office), DLC (Digital Loop Carrier) and high range PABX (Private Automatic Branch Exchange). 1/28 L3000N L3000N - L3030 L3030 PIN CONNECTIONS (top view) FLEXIWATT15 FLEXIWATT15 PLCC44 PLCC44 10 11 V B- V BIM 9 12 AGND VBVIN 8 13 REF VDD 7 14 C1 BGND 6 15 C2 V B+ 5 16 IT MNT 4 17 IL TIP 3 18 N.C. N.C. 2 19 RING VB- 1 20 V B- D94TL125 D94TL125 PowerSO-20 2/28 L3000N L3000N - L3030 L3030 PIN DESCRIPTION (L3000N L3000N) FLEX. N° ° 1 PSO N° ° 3 2 3 4 4 5 6 MNT VB+ BGND 5 6 7 7 8 9 VDD VIN VBIM 8 VB­ 9 10 1, 10 11, 20 12 13 AGND REF 11 12 13 14 15 16 C1 C2 IT 14 17 IL 15 19 RING ­ 2, 18 N.C. Name TIP Description A line termination output with current capability up to 100mA (Ia is the current sourced from this pin). Positive Supply Voltage Monitor Positive Battery Supply Voltage Battery ground relative to the VB+ and the VB­ supply voltages. It is also the reference ground for TIP and RING signals. Positive Power Supply + 5V 2 wire unbalanced voltage input. Output voltage without current capability, with the following functions : - give an image of the total battery voltage scaled by 40 to the low voltage part. - filter by an external capacitor the noise on VB­. Negative Battery Supply Voltage Analog Ground. All input signals and the VDD supply voltage must be referred to this pin. Voltage reference output with very low temperature coefficient. The connected resistor sets internal circuit bias current. Digital signal input (3 levels) that defines device status with pin 12. Digital signal input (3 levels) that defines device status with pin 11. High precision scaled transversal line current signal. Ia + Ib IT = 100 Scaled longitudinal line current signal. Ib - Ia IL = 100 B line termination output with current capability up to 100mA (Ib is the current sunk into this pin). Not connected Notes: 1) Unless otherwise specified all the diagrams in this datasheet refers to the FLEXIWATT15 FLEXIWATT15 pin connection. 2) All informations relative to the PowerSO-20 package option should be considered as advanced information on a new product now in development or undergoing evaluation. Details are subject to change without notice. 3/28 L3000N L3000N - L3030 L3030 PIN DESCRIPTION (L3030 L3030) Pin Symbol 1 TST 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 REF AGND VSS VDD N.C. CZS ACF ZAC 4/28 TST VOUT CM RC IT RDC EIA NCS DIO DCKL DGND N.C. N.C. N.C. CI C1 C2 N.C. N.C. IL CRTS TTXIN RGTTX TTXF ZB TST TX RX/RG VBIM TST Function This pin is connected internally for test purpose. It should not be used as a tie point for external components. Bias Set Analog Ground ­ 5V + 5V Not connected. AC Feedback Input AC Line Impedance Synthesis AC Impedance Adjustement These pins are connected internally for test purpose. It should not be used as a tie point for external components. Two wire unbalanced output. Capacitor Multiplier Input DC Feedback Input Transversal Line Current DC Feeding System Read/write Command Chip Select Command Data Input/output Clock Signal Digital Ground Not connected. Not connected. Not connected. Input/output Changing Command State Control Signal 1 State Control Signal 2 Not connected. Not connected. Longitudinal Line Current Ringtrip Det. & TTX Shaping Teletaxe Signal Input TTX Filter Level Compensation TTX Filter Input Balancing Network These pins are connected internally for test purpose. It should not be used as a tie point for external components. 4W Sending Output 4W Receiving and Ring Input Battery Image Input These pins are connected internally for test purpose. It should not be used as a tie point for external components. L3000N L3000N - L3030 L3030 L3000N L3000N BLOCK DIAGRAM L3030 L3030 BLOCK DIAGRAM 5/28 L3000N L3000N - L3030 L3030 ABSOLUTE MAXIMUM RATINGS Symbol Vb­ Vb + |Vb­| + |Vb+| Vdd Vss Vagnd ­ Vbgnd Tj Tstg Parameter Negative Battery Voltage Positive Battery Voltage Total Battery Voltage Positive Supply Voltage Negative Supply Voltage Max. Voltage between Analog Ground and Battery Ground Max. Junction Temperature Unit V V V V V V °C ­ 55 to + 150 Storage Temperature Value ­ 80 80 140 +6 ­6 5 + 150 °C Value Unit THERMAL DATA Symbol Parameter L3000N L3000N HIGH VOLTAGE Flexiwatt PWSO20 PWSO20 R th j-case Thermal Resistance Junction to Case Max. 4 Typ. 2 °C/W Rth j-amb Thermal Resistance Junction to Ambient Max. 50 Max. 60 °C/W L3030 L3030 LOW VOLTAGE Rth j-amb Max. Resistance Junction to Ambient °C/W 80 OPERATING RANGE Symbol Toper Vb­ Vb+ Vb­ + Vb+ Vdd Vss Imax Parameter Operating Temperature Range Min. 0 Typ. Max. 70 Negative Battery Voltage Positive Battery Voltage Total Battery Voltage Positive Supply Voltage Negative Supply Voltage Total Line Current (IL + IT) ­ 70 0 ­ 48 + 72 120 ­ 24 + 75 130 + 5.5 ­ 4.5 85 FUNCTIONAL DESCRIPTION L3000N L3000N - High Voltage Circuit The L3000N L3000N line interface provides a battery feeding for telephone lines and ringing injection. The IC contains a state decoder that under external control can force the following operational modes : standby, conversation and ringing. In addition Power down mode can be forced connecting the bias current resistor to VDD or leaving it open. Two pins, IL and IT, carry out the information concerning line status which is detected by sensing the line current into the output stage. The L3000N L3000N amplifies both the AC and DC signals entering at pin 6 (VIN) by a factor equal to 40. Separate grounds are provided : - Analog ground as a reference for analog signals - Battery ground as a reference for the output stages 6/28 + 4.5 ­ 5.5 Unit °C V V V V V mA The two ground should be shorted togetherat a low impedance point. L3030 L3030 - Control Unit The L3030 L3030 low voltage control unit controls L3000N L3000N line interface module, giving the proper information to set line feed characteristic, to inject ringing and TTX signal and synthetizes the line and balance impedances. An on chip digital interface allows a microprocessor to control all the operations. L3030 L3030 defines working states of line interface and also informs the card controller about line status. L3000N L3000N - Working States In order to carry out the different possible operations, the L3000N L3000N has several different working states.Each state is definedby the voltagerespectively applied by pins 27 and 28 of L3030 L3030 to the pins 11 and 12 of L3000N L3000N. Three different voltage levels (­ 3, 0, + 3) are available at each connection, so defining nine possible L3000N L3000N - L3030 L3030 Table 1. Pin 28 of L3030 L3030 / Pin 12 of L3000N L3000N +3 +3 0 (C2) ­3 Conversation in Normal Battery Direct Polarity Conversation in Normal Battery Reverse Polar 0 Not allowed. Conversation in Boost Battery Direct Polarity Conversation in Boost Battery Reverse Polar ­3 Pin 27 of L3030 L3030 Pin 11 of L3000 L3000 Stand-by Not allowed. Ringing with Direct Polarity Not allowed. states as listed in Table. 1. Appropriate combinations of two pins define the three modes of the ST SLIC, that are : a) Stand-by (SBY) b) Conversation (CVS), Normal and Reverse polarity c) Ringing (RING) d) Boost Battery (BB), Normal and Reverse polarity A fifth status, Power down (PD), can be set disconnecting the bias resistor (RH) from pin 10 of L3000N L3000N by means of an external transistor. The main difference between Stand-by and Power down is that in SBY the power consumption on the voltage battery VB­ (­ 48V) is reduced but the L3000N L3000N DC feeding and monitoring circuits are still active. In PD the power consumption on VB- is reduced to zero, and the L3000N L3000N is completely switched off. The SBY status should be used when the telephone is in On hook and PD status only in emergency condition when it is mandatory to cut any possible dissipation but no operation are requested. OPERATING MODES Stand-by (SBY) Mode In this mode, the bias currents of both L3000N L3000N and L3030are reduced as only some parts of the two circuits are completely active, control interface and current sensors among them. The current supplied to the line is limited at 7mA, and the slope of the DC characteristic corresponds to : 2 R = x (RFS + 2RP) 3 The Line voltage in on Hook condition is just the battery voltage minus the voltage drop (approx. 15V) of the output stage amplifiers (see Fig. 1). Figure 1 : DC Characteristics in Stand-by Mode. 7/28 L3000N L3000N - L3030 L3030 The AC characteristic is just the resistance of the two serial resistors RP. In Stand-by mode the battery polarity is just in direct condition, that is the TIP wire more positive than the RING one ; boost battery is not achievable. There are two possible line conditions where the SLIC is expected to be in stand-by mode : 1) ON-HOOK (Iline < 5mA). Normal on-hook condition. 2) OFF-HOOK (Iline > 7mA). Handset is unhooked, the SLIC is waiting for command to activate conversation. When the SLIC is in stand-by mode, the power dissipation of L3000N L3000N does not exceed 120mW (from -48V) eventually increased of a certain amount if some current is flowing into the line. The power dissipation of L3030 L3030 in the same condition, is typically 120mW. The Stand-by Mode is set when the byte sent to the L3030 L3030 Serial Digital Interface has the first two bits (BIT0R and BIT1R) equal to "0". Setting to 0 all the 8 bits of the command sent to the digital interface of L3030 L3030, the bias currents of both L3000N L3000N and L3030 L3030 are reduced and only some parts of the two circuits are active similarly to the stand-by mode ; in this situation, named powerdown denial, the line sensors are disabled (ON/OFF-HOOK line conditions cannot be recognized) and the current supplied to the line is limited at 0.25mA. Conversation (CVS) or Active Mode In conversationmode it is possible to select between two different DC Characteristics by the BIT5R of the Serial Interface. 1) Normal Battery (NB) 2) Boost Battery (BB) It is also possible to select (BIT4R) the polarity of the DC line voltage and (BIT6R-BIT7R) one of the four values of limiting current (25mA or 30mA or 45mA or 70mA). Battery reverse can take place either before or during conversation. As far as the DC characteristic in Normal Battery is concerned, three different feeding conditions are present : a) current limiting region ; the DC impedance of the SLIC is very high (> 20 Kohm) and therefore the system works like a current generator,thecurrent value being set through the digital interface (25/30/45/70mA). b) standard feeding system region ; the characteristic is equal to a ­ 48V (­ 60V) battery (note 1), in series with two resistors, whose value is set by external components (see external component list of L3030 L3030). c) low impedance region ; the battery value is reduced to 33V (45V) and the serial resistance is reduced to the value specified in stand by mode, 2 that is : x (RFS + 2RP) 3 Switching between the three region is automatic without discontinuity, and depends on the loop resistance. Fig. 2 shows the DC characteristic in normal battery condition. When the boostbattery conditionis activatedthe low impedance region can never be reached by the sy- Figure 2 : DC Characteristic (n.b.) ILIM = 25/30/45/70 mA. Note : 8/28 1. This value of voltage battery, named apparent battery, is fixed internally by the control unit and is independent of the actual battery value. So, the voltage drop in the low impedance region is 15V. It is also possible to increase up to 25V this value setting BIT3R to 1. L3000N L3000N - L3030 L3030 stem ; in this case the internal dropout voltage is equal to 30V. Fig. 3 shows the DC characteristic in boost battery condition. In conversation mode, on request of control processor, whatever condition is set (normal or boost battery, direct or reverse polarity), you can inject the 12kHz (or16kHz) signal (permanently appliedat the pin 33 with 950mVrms typ. amplitude), as metering pulses. A patented automatic control system adjust the level of the metering signal, across the line, to 2Vrms setting BIT3 = 0, or to 5Vrms setting BIT3 = 1 ; this, regardless of the line impedance. Moreover the metering signal is ramped at the beginning and at the end of each pulse to prevent undesirable clicking noise ; the slope is determined by the value of CINT (see the external component list of L3030 L3030). The SLIC also provides, in the transmit direction (from line to 4-wire side), an amplifier to insert an external notch filter (series resonator) for suppressing the 12/16kHz residual signal. Fig. 4 shows a suggested notch Filter configuration. The metering pulses can be injected with a DC line current equal to zero (ON-HOOK Operation). If teletax is not used the notch filter can be replaced by a 1K resistor. Inconversationmode the AC impedanceat the line terminals, ZML, is synthetizedby the externalcomponents ZAC and RP, according to the following formula : ZML = ZAC + (RP1 + RP2) Depending on the characteristic of the ZAC network, ZML can be either a pure resistance or a complex impedance,so allowingST SLICto meetdifferent standards as far as the return loss is concerned. The capacitor CCOMP guarantees stability to the system. The two-to-four wire conversion is achieved by means of a Wheatstone bridge configuration, the sides of which being : 1) the line impedance (Zline), 2) the SLIC impedance at line terminals (ZML), 3) the networkZA connectedbetween pin36 and 41 of L3030 L3030 (see external component list of L3030 L3030), 4) the network ZB between pin 36 and ground that shall copy the line impedance. For a perfect balancing, the following equation shall be verified : ZA ZML = ZB Zline It is important to underline that ZA and ZB are not obliged to be equal to ZML and to Zline, but they both may be multiplied by a factor (up to ten) so allowing use of smaller capacitors. In conversation,the L3000Ndissipatesabout 250mW forits own operation;the dissipationdependingonthe current supplied to the line shall be added. The fig 5 and fig 6 show the DC characteristic for two different Feeding resistance. 2 x 200 Ohm and 2 x 400 respectively. Figure 3 : DC Characteristic (b.b.) ILIM = 25/30/45/70mA. Figure 4 : External Teletaxe Filter. f= L= 1 2 LxC R2 x R4 xR5 xC2 R3 9/28 L3000N L3000N - L3030 L3030 Figure 5 : DC Characteristic for 2 x 200 ohm Feeding System. Figure 6 : DC Characteristic for 2 x 400 ohm Feeding System. Figure 7 : Line Current Versus Loop Resistance, RFS = 200, RP = 30, VB­ = ­48V. 10/28 L3000N L3000N - L3030 L3030 Ringing Mode When ringing is selected (BIT2R = 1, BIT0R = 0), the control unit L3030 L3030 presets the L3000N L3000N to operate between ­ 48V (­ 60V) and + 72V (+ 60V) battery. Then,setting BIT1 = 1, a low level signal (0.285Vrms with frequency range 16-66Hz) applied to pin 41, is amplified and injected in balanced mode to the line throughL3000N with a superimposed DC voltage of 24V. The impedance to the line is given by the two external resistors and the 24V DC polarity can only be direct. The first and the last ringing cycles are synchronized by L3030 L3030 so that ringing always starts and stops at zero crossing. Ring trip detection is performed autonomouslyby the SLIC, without any particular command, using a patented system ; when handset is lifted, SLIC suspends the ringing signal just remaining in the ringing mode. In this condition, the control unit L3030 L3030 checks that the loop is closed for a time equal to two periods of the ringing signal ; if the closure is confirmed, a flag (BIT0T = 1) is set and the SLIC waits the new command from the control processor. Whereas the loop closure is not confirmed, the ringing signal is newly appliedto the line, without setting BIT0T. DIGITAL INTERFACE Functional Description The L3030 L3030 states and functions are controlled by central processor through five wires defining a digital interface.It is possible to select the interface working mode between SERIAL or PARALLEL (pin 33 tied to a voltage between 4 and 5V). 1) Serial Mode The five wires of the digital interface have the following functions : - clock (DCLK), entering at pin 21 - data in/data out (DIO), exchanged at pin 20 - input/outputselect (EIA), entering at pin 18 - chip select (NCS), entering at pin 19 - change NCS from in to out (CI), entering at pin 26 (note 1) The maximum clock frequency is 600Khz. When EIA signal is low data are transferred from the card controller into I/O registers of the L3030 L3030 selected by NCS signal tied at low level ; then data are latched for execution. In this phase a complete 8 bit word is loaded into internal register and consequently NCS signal must remain low for the corresponding 8 clock pulses (DCLK). The EIA signal must remain at low level at least for the time in which NCS signal remain low. The device load data in input register during the positive edge of clock signal (DCLK) and store the contents of the register on the positive edge of NCS signal. When EIA signal is high data are transferred from the L3030 L3030 selected by NCS tied to low level to the card controller. The L3030 L3030 status is described by five bits contained in the output register ; the NCS signalcan remain low for five or less clock pulses depending if the card controller want to read the complete L3030 L3030 status or only a part of it. Fig. 8, 9 show the completewrite and read operation timing. Table 1 shows the meaning of each bit of an I/O data. 11/28 L3000N L3000N - L3030 L3030 Table 1 : Serial Mode. Meaning Value Data in (note 2) BIT0R = Impedance (note 3) 0 - Stand-by/ringing 1 - Conversation BIT1R = TTX & Ring Timing (note 4) 0 - Timing off 1 - Timing on BIT2R = Ring (note 5) 0 - TTX Signal Injection 1 - Ring Signal Injection BIT3R = TTX Level 0 - Low Amplitude (2VRMS ) 1 - High Amplitude (5VRMS) BIT4R = Battery Polarity 0 - Normal Polarity 1 - Reverse Polarity BIT5R = Extra Feeding 0 - Normal Battery 1 - Boosted Battery BIT6R BIT7R Current Limiting 0 25mA 0 0 30mA 1 1 45mA 1 1 70mA 0 Data Out (note 6) BIT0T = Line Supervision 0 - On Hook 1 - Off Hook BIT1T = Ground Key 1 - Long. Line Current < 17mA 0 - Long. Line Current > 17mA BIT2T = Internal Line Current Limiter (note7) 0 - Off 1 - On BIT3T = Line Voltage 0 - Normal 1 - Minus of Half Battery BIT4T = Thermal Overload (note 8) 1 - Off 0 - On Notes : 1. When CI si gnal is tied t o low l evel, NCS si gnal is the chip select input ; wi th C I signal at high l evel, the N CS signal becomes an output that carry out the logical sum of the f ollowi ng bi ts : BIT 0T, BIT 1T. 2. The descri ption of the commands is referred to the syst em L3030 L3030 + LINE IN TE RFAC E module. 3. To set SBY mode w ith Ilim = 7mA : B IT0R = 0 and at least one of the tw o last bit s ( BIT 6R ; B IT7R) must be set to 1. 4. TTX and RING si gnals are inj ected i nto the line i nterf ace modul e wi th BIT1R to "1". 5. To set R ING mode at least one of the thr ee last bits (B IT5R, BIT 6R, BI T7R) must be set to 1, in addi tion BIT0R must be set to 0. 6. The descri ption of the commands is referred to the syst em L3030 L3030 + LINE IN TE RFAC E module. 7. The bit BIT2T is set to 1 when the SLIC is operati ng in Conversation Mode and into the lim iti ng current region (short loop). 8. The bit BIT4T i s set to 1 when the j unct ion temperature of L3000N L3000N i s about 140°C. 12/28 L3000N L3000N - L3030 L3030 Figure 8 : Writing Operation Timing (serial mode). Figure 9 : Reading Operation Timing (serial mode). 13/28 L3000N L3000N - L3030 L3030 2) Parallel Mode In this operating mode the signals at the inputs are immediately executed, without any external clock timing ; allthe internal registers are bypassed.The informations sent back on pins 19 and 20, display in real time the setting of internal circuits, that means line status. In the table 2 the correspondence between the interface wires in the parallel mode and equivalent bit in serial mode is pointed out ; where there isn't this correspondence, the internal setting is shown. This operating mode is enabled connecting pin 33 to a voltage in the range from 4V to 5V. The five wire have the following functions : - power down/feeding (EIA), entering at pin 18 - timing (CI), entering at pin 26 - ring (DCLK), entering at pin 21 - on-hook/off-hook(NCS), outgoing at pin 19 - ground-key (DIO), outgoing at pin 20 Table 2 : Parallel Mode. Pin Rif. 18 EIA Meaning (note 1) Eq. Bit of Ser. Interf. PD/feeding BIT0R Value 0 : High Impedance 1 : Low Impedance 26 CI 21 DCKL Timing BIT1R Ring BIT2R 0 : Ring Timing Off 1 : Ring Timing On 0 : No Ring 1 : Ring Injection BIT3R 0 : Low Amplitude BIT4R 0 : Normal Polarity BIT5R 0 : Normal Battery BIT6R 0: 1: BIT7R 19 NCS On-hook/off-hook BIT0T Line Curr. = 30mA 0 : On-hook 1 : Off-hook 20 DIO Ground Key BIT1T 1 : Long. Curr. < 17mA 0 : Long. Curr. > 17mA BIT2T BIT3T BIT4T Note : 1. The description of the commands is referred to the system L3030 L3030 + LINE INTERFACE module. DIGITAL INTERFACE ELECTRICAL CHARACTERISTICS (VDD = + 5V, VSS = ­ 5V, Tamb. = 25oC) (refer to PLCC44 PLCC44 package) Symbol Parameter Test Conditions Min. Typ. Max. Unit 0 0.8 V 2.0 5 V STATIC ELECTRICAL CHARACTERISTICS Vil Input Voltage at Logical "0" Vih Input Voltage at Logical "1" Iil Input Current at Logical "0" Vil = 0V 200 µA Iih Input Current at Logical "1" Vih = 5V 10 µA Vol Output Voltage at Logical "0" Pins 19, 20 Iout = ­ 1mA 0.4 V Voh Output Voltage at Logical "1" Pins 19, 20 Iout = 1mA Tristate Leak. Current Pin 20 NCS = "1" Ilk 14/28 Pins 18, 19, 20, 21, 26 2.4 V 10 µA L3000N L3000N - L3030 L3030 DIGITAL INTERFACE ELECTRICAL CHARACTERISTICS (continued) Symbol Parameter Test Conditions Min. Typ. Max. Unit 600 kHz DYNAMIC ELECTRICAL CHARACTERISTICS fclk Tr, Tf Twh, Twl Clock Frequency 1 Clock Rise and Fall Time 50 ns Clock Impulse Width 750 ns Tis CI to NCS Set up Time 300 ns Tec "0" EIA to DCKL Set up Time 300 ns Tsc DCKL to NCS Delay (+ edge) 300 ns 0 ns Tsd Data in Set up Time Thd Data in Hold Time 800 ns Tcs NCS to DCKL Hold Time 800 ns Tca "0" EIA to DCKL Hold Time 900 ns Tac "1" EIA to DCKL Set up Time 400 ns Tzd Data out to "0" NCS Delay 0 Tce "1" EIA to DCKL Hold Time 900 Tdz Data out to "1" NCS Delay Tdd "0" CI to NCS Hold Time OPERATION DESCRIPTION To set SLIC in operation the following parameters have to be defined : - the DC feeding resistance RFS, defined as the resistance of each side of the traditional feeding system (most common values are 200, 400 or 500 ohm). - the AC impedanceat line terminals, ZML, to which the return loss measurement references. It can be real (typically 600 ohm) or complex. - the equivalent AC impedance of the line Zline, when evaluating the trans hybrid loss (2/4 wire ns 1500 300 ns 500 Data out to DCKL Delay Tsi 600 ns ns ns conversion). It is usually a complex impedance. - the ringing signal frequency Fr (ST SLIC allows frequency ranging from 16 to 66Hz). - the metering pulse frequency Ft (two values are possible : 12kHz or 16kHz). - the value of the two resistors RP1/RP2 in series with the line terminals ; main purpose of the a.m. resistors is to allow primary protection to fire. ST suggest the minimum value of 50 ohm for each side. On this assumptions, the following component list is defined. 15/28 L3000N L3000N - L3030 L3030 EXTERNAL COMPONENT LIST FOR THE LINE INTERFACE Component Pin Ref. Involved Parameter or Function Value L3000N L3000N 10 RREF 24.9k ± 1% 1,15 RP 30 to 100 Line Series Resistor Battery Voltage Rejection Bias Resistance 7 CDVB 47µF ­ 20V 3 CVB+ 0.1µF ­ 100V (1) Positive Battery Filter 8 CVB­ 0.1µF ­ 100V (2) Negative Battery Filter 8 D1 BAT 49X 4-3 CVSS 0.1µF ­ 15V Negative Supply Voltage Filter 5-3 CVDD 0.1µF ­ 15V Positive Supply Voltage Filter 7-8 RR 16K (range: 10 to 50K) Capacitor Multiplier Gain (8) 15-17 RDC 2 x (RFS ­ RP1) CAC1 (3) 1 6.28 x 250 x (ZAC + RDC) Protective Shottky Diode L3030 L3030 (PLCC44 PLCC44) 7-15 14-15 CAC2 CAC1 8-9 8-9 ZAC CCOMP ZML ­ (RP1 + RP2) 1/(6.28 x 150000 x (RPC) 9-14 RPC DC Feeding Resistor (RDC > 270) AC Path decoupling RP1 + RP2 24.9K 1% K x Zline (note 4) 2-3 RREF 36-3 ZB 36-41 ZL CINT Rp insertion loss compensation K x RPC in Series with K x ZAC // (CCOMP/K) 32-3 2 Wire AC impedance AC loop compensation Bias Resistance (note 6) Line Impedance Balancing Network SLIC Impedance Balancing Network (note 5) Ring trip detection time constant 15-16 Ccon 0.15µF (note 7) 35 TTx FILT. ZTTX = 1k 1% in speech band ZTTX 0 at TTX freq. (note 9) Interface Time Constant Teletax filter. 34 RGTTX 10k 1% Teletax filter. Notes : 1. In case line cards wit h less than 7 subscri bers are implemented C VB­ capaci tor shoul d be equal to 680nF/N w here N is the number of subscr iber per card. 2. Thi s shottky diode or equival ent i s necessary to avoid t o damage to the device during hot insert ion or i n al l those cases when a pr oper power up sequence cannot be guaranteed. In case the shot tky diode is not implemented the power sequence should guarant ee that VB+ i s always the last supply applied at power on and the fir st removed at power of f. In case an other shott ky diode type is adopted it must f ulfil l the f oll owi ng charact eristi cs: VF < 450mV @ IF = n 15mA, Tamb = 25°C VF < 350mV @ IF = n 15mA, Tamb = 50°C (T jL3 00 0 = 90°C) VF < 245mV @ IF = n 15mA, Tamb = 85°C (T jL3 00 0 = 120°C) Where n is t he number of l ine shar ing the same diode. 3. If the internal capacity multipl ier stage is not used, pin 7 must be connected with pin 14 w it hout mount ing RR and CA C2. In this case CAC1 = 1/ (6.28 x 30 x RDC ). 4. T he structure of thi s networ k shal l copy the l ine impedance, i n case mul tiplied by a f actor K = 1.10 5. K as fixed at note 4. 6. CI NT can have t he fol lowi ng val ues : Fr. (Hz) 16/18 18/21 21/26 26/31 31/38 38/46 46/57 57/66 CINT (nF) 560 470 390 330 270 220 180 150 7. Ccon is necessary to work "wi thout on/off hook detecti on-errors" duri ng TT X-pul ses. 8. RR i s used by a capaci tor mul tipli er cir cui t t o synthetize an higher AC/DC spl it ting capacitor starting fr om CAC1 and CAC 2. S upposi ng CA C1 = CAC2 = CAC the synthet ized capacitor value wi ll be equal 9. If T eletax is not used the TTX FILT . can be replaced by a 1k resi stor. 16/28 R R + ZML ZML CA C. L3000N L3000N - L3030 L3030 Figure 10 : Typical Application Schematic Diagram. Figure 11 : Typical Application Schematic Diagram without Capacitor Multiplier. 17/28 L3000N L3000N - L3030 L3030 ELECTRICAL CHARACTERISTICS (refer to the test circuits of the Figure 12, VDD = + 5V, VSS = 5V, VB+ = + 72V, VB­ = ­ 48V, Tamb = + 25oC, TTX FILT = 1k) Symbol Parameter Test Conditions Min. Typ. Max. Unit 30.0 28.2 40.0 38.5 V V 5 8.5 mA 5 8.5 mA .75 V 2 mA 35.0 28.8 17.5 V V V + 15% mA 8 mA STAND-BY Vls Output Voltage at L3000N L3000N Terminals Iline = 0mA Iline = 5mA Ilcc Short Circuit Current DATA IN (note 1) 000X00X1 000X00X1 Iot On/off-hook Detection Threshold Vls Symmetry to Ground Iline = 0mA STAND BY DENIAL Ilcc Short Circuit Current DATA IN 000X00X0 000X00X0 DC OPERATION - NORMAL BATTERY (VTTX = 2VRMS, low level) Vlo Output Voltage at L3000N L3000N Terminals Ilim = 70mA Data in 1000X010 1000X010 Ilim Current Programmed Through the Digital Inter. Io On-hook Detection Threshold If Off-hook Detection Threshold 12 Ilgk Longitudinal Line Current with GK Detect 10 Iline = 0mA Iline = 20mA Iline = 50mA 31.0 24.0 2.5 ­ 10% Ilim mA 17 26 mA 95.6 81 V V 10 DC OPERATION - BOOST BATTERY Vlo Output Voltage at L3000N L3000N Terminals Iline = 0mA Iline = 20mA 86 68.6 AC OPERATION Ztx Sending Output Impedance 4 Wire Side Zrx Receiving Input Impedance 4 Wire Side THD Signal Distorsion at 2W and 4W Terminals 100 k 0.5 % R1 2W Return Loss f = 300 to 3400Hz 22 dB Thl Trans Hybrid Loss f = 300 to 3400Hz 24 dB Gs Sending Gain Vso = 0dBm f = 1020Hz Norm. Polarity dB ­ 0.25 + 0.25 Gsf Sending Gain Flatness versus Frequency f = 300 to 3400Hz Respect to 1020Hz ­ 0.1 + 0.1 dB Gsl Sending Gain Linearity fr = 1020Hz, Vsoref = ­10dBm Vso = + 4 /­ 40dBm ­ 0.1 + 0.1 dB Gr Receiving Gain Vri = 0dBm f = 1020Hz Norm. Polarity Grf Receiving Gain Flatness f = 300 to 3400Hz Respect to 1020 dB ­ 0.25 ­ 0.1 0 + 0.25 + 0.1 Notes : 1. The data into the digital interf ace of L3030 L3030 are send i n seri al mode. The f ormat of data i s the fol lowi ng : a) DATA IN : the bit at left side is BIT 0 of t he writi ng wor d, whil e the bit at the ri ght side is BI T 7. b) DATA OUT : the bit at the left side i s BIT0 of the reading word, whil e t he bi t at the ri ght is BI T4. When appear a symbol X, the value of the bit don't care. 18/28 dB L3000N L3000N - L3030 L3030 ELECTRICAL CHARACTERISTICS (continued) Symbol Parameter Test Conditions Min. fr = 1020Hz, Vriref = ­ 10dBm Vri = + 4 /­ 40dBm Typ. ­ 0.1 Max. Unit + 0.1 dB AC OPERATION (continued) Grl Receiving Gain Linearity Np4W Psophometric Noise at 4W-Tx Terminals ­ 75 ­ 70 dBmp Np2W Psophometric Noise at Line Terminals ­ 75 ­ 70 dBmp SVRR Supply Voltage Rejection Ratio Relative to VB­ f = 3400Hz ­ 30 dB SVRR Relative to VDD ­ 26 dB Relative to VSS f = 3400Hz Vs = 100mVrms ­ 30 SVRR ­ 32 ­ 30 dB Ltc Longitudinal to Transversal Conversion Tlc Transversal to Longitudinal Conversion Td Propagation Time Tdd Propag. Time Distortion Vttx Line Voltage of Teletaxe Signal VTTXin = 950mVrms THD Teletaxe Signal Harmonic Dist. ttx Filt = 0 @ 16kHz Note 4 Teletaxe Amplif. Input Impedance Pin 33 of L3030 L3030 Zitt f = 300 to 3400Hz Iline = 30mA, ZML = 600 49 (1) 60 48 dB 51 dB 40 Note 2 Note 3 µs 2.3 5.5 V V 5 1.7 4.5 µs 25 Both Direction % 100 k AC OPERATION BOOST BATTERY Gs Gr Sending Gain Receiving Gain Np4W Relative to Vdd SVRR Vri = 0dBm f = 1020Hz Norm. Polarity ­ 0.27 + 0.08 + 0.43 dB ­ 73 ­ 68 dBmp ­ 73 ­ 68 dB ­ 23 dB ­ 23 dB 27 25 V V Psophometric Noise at line Terminals SVRR ­ 0.66 ­ 0.16 + 0.34 Psophometric Noise at 4W-Tx Terminals Np2W Vso = 0dBm f = 1020Hz Norm. Polarity Relative to Vss f = 3400Hz Vs = 100mVrms dB RINGING PHASE Vlr Vacr If Superimposed DC Voltage Rloop > 100k Rloop = 1k Ringing Signal at Line Termin. Rloop = 1k/1µF 19 17 23 21 56 Vrms DC Off-hook Det. Threshold 1.5 3.5 Ilim Current Limit. 85 130 mA Vrs Ringing Simmetry 2 Vrms 5 % THDr Notes : 1. 2. 3. 4. Ringing Signal Distortion VAC = 0.285VRMS 285VRMS fRING = 30Hz mA Up to 52dB usi ng selected L3000N L3000N . The confi gurati on of data sent to device change, every 100mS, from - 1100X010 1100X010 - to - 1000X010 1000X010 The confi gurati on of data sent to device change, every 100mS, from - 1101X010 1101X010 - to - 1001X010 1001X010 Error gener ated by tt x fil t 0 ohm, on the output teletax ampli tude is err % = 100 x (1 + A) x B/C where A = 10 Kohm/ RGT TX[Kohm], B = TTXF I LT[ Kohm], C = (TT XFILT [Kohm] + 1 Kohm), for example 10 ohm means err% = 2%. 19/28 L3000N L3000N - L3030 L3030 ELECTRICAL CHARACTERISTICS (continued) Symbol Parameter Test Conditions Min. Typ. Max. Unit 600 mV 125 (2T) ms 125 (2T) ms 188 (3T) ms RINGING PHASE Zir Ringing Amplif. Input Impedance Vrr Residual of Ringing Signal at TX Output Trt Ring Trip Detection Time Toh Off-hook Status Delay after the Ringing Stop Trs Cut off of Ringing Pin 41 of L3030 L3030 fring = 16Hz T = 1/fring 100 k (1T) Ring Trip not Confirmed SUPPLY CURRENT IDD Positive Supply Current CS = 1 Stand-by Conversation (NB/BB) Ringing 16.0 26.0 16.5 20.0 31.0 21.0 mA mA mA ISS Negative Supply Current CS = 1 Stand-by Conversation (NB/BB) Ringing 9 19 9 12 23 12 mA mA mA IBAT­ Negative Battery Supply Current Line Current = 0mA Stand-by Conversation NB Conversation BB Ringing 2 5 6.6 14 2.5 6.5 8.0 17 mA mA mA mA IBAT+ Positive Battery Supply Current Line Current = 0mA Stand by Conversation NB Conversation BB Ringing 10 10 8 12 15 15 10 13.5 µA µA mA mA NB = Normal B attery BB = B oosted Batter y Figure 12 : Slic Test Circuit Schematic. 20/28 18 19 20 21 22 16 8 10 9 14 13 11 12 17 DX0 DX1 TSX0 TSX1 Fsx BCLK FSR DR0 DR1 CS CCLK CO CI MCLK VSS IL0 VRING= 285mVrms VFRO IL1 26 2 28 100nF IL2 IL3 IL4 IL5 MR 25 7 6 24 23 15 CTL (*) RDC ZB CINT CAC1 RPC ZAC CCOMP ZA RDC RC CM ZAC ACF CZS RX ZB CRTS EIA 17 15 14 9 8 7 41 36 32 NCS 33 19 40 DIO 20 21 AGND DCLK L3030 L3030 TX CI 3 26 TO/FROM CARD CONTROLLER 18 TTXIN (*) The analog multiplexer can be avoided if the VRING = 285mVRMS is provided by the CODEC. TS5070 TS5070 GND VCC +5V 100nF 100nF -5V 16 27 28 31 13 42 34 35 5 4 2 VDD C2 IL VIN VBIM REF RH AGND VDD D94TL126 D94TL126 IT IT 13 11 12 14 6 7 VB+ VB+ 3 2 1 8 15 L3000N L3000N 4 10 9 5 BGND C1 CCON RGTTX TTX FILTER CVDD VSS CVSS CDVB C1 C2 IL VOUT VBIM RGTTX TTXF VDD VSS REF RL BGND 20 D1 CVB- RING 20 MNT TIP VB- CVB+ VB- VB- 1 1 4 2 4 L3121 L3121 3 30 22nF BGND 30 22nF L3121 L3121 2 3 VB+ L3000N L3000N - L3030 L3030 Figure 13: Typical application schematic with 2nd generation COMBO. 21/28 22/28 FSX FSR BCLKR/ BCLK MCLKR/ MCLKX TSX DR DX VSS +5V ETC5057 ETC5057 R4 VFXI+ R2 R1 VFRO GSX VFXI- (*) C CTL (FROM CARD CONTR.) VRING= 285mVrms (*) R3 RDC ZB CINT CAC1 RPC ZAC CCOMP ZA RDC RC CM ZAC ACF CZS RX ZB CRTS EIA 17 15 14 9 8 7 41 36 32 NCS 33 19 40 DIO 20 21 AGND DCLK L3030 L3030 TX CI 3 26 TO/FROM CARD CONTROLLER 18 TTXIN (*) Resistors R1 to R4 program IX/RX gains ZA, ZB shold be >>than R2. (*) The analog multiplexer can be avoided if the V RING = 285mVRMS is provided by the CODEC. GNDA V CC 100nF 100nF -5V 16 27 28 31 13 42 34 35 5 4 2 VDD IL VIN VBIM REF RH AGND VDD BGND C2 CCON RGTTX TTX FILTER CVDD VSS CVSS CDVB IT C1 IT D94TL127A D94TL127A C1 C2 IL VOUT VBIM RGTTX TTXF VDD VSS REF RL BGND 13 11 12 14 6 7 VB+ 3 2 1 8 15 L3000N L3000N 10 9 5 4 VB+ 20 D1 CVB- RING 20 MNT TIP VB- CVB+ VB- VB- 1 2 L3121 L3121 4 30 3 22nF 22nF BGND 30 3 1 4 L3121 L3121 2 VB+ L3000N L3000N - L3030 L3030 Figure 14: Typical application schematic with 1st generation COMBO. L3000N L3000N - L3030 L3030 APPENDIX SLIC TEST CIRCUITS Referring to the test circuit reported at the end of each SLIC data sheet here below you can find the proper configuration for each measurement. In particular : A-B : Line terminals C : TX sending output on 4W side D : RX receiving input on 4W side E : TTX teletaxe signal input RGIN : low level ringing signal input. TEST CIRCUITS Figure 1 : Symmetry to Ground. Figure 2 : 2W Return Loss. RL = 20 log 1 WC Figure 3 : Trans-hybrid Loss. THL = 20 log10 |VS| |VR| |ZL - Z| |2 VS| = 20 log |E| |ZL + Z|