KS24C040/041 KS24C040/041/080/081 KS24C040/080 KS24C080/081 KS24C080 1010B - Datasheet Archive

 

ELECTRONICS 4,096 / 8,192-Bit Serial EEPROM Data Sheet OVERVIEW The KS24C040/041/080/081 serial EEPROM has a 4K/8K-bit

 

KS24C040/041 KS24C040/041*/080/081* ELECTRONICS 4,096 / 8,192-Bit Serial EEPROM Data Sheet OVERVIEW The KS24C040/041/080/081 KS24C040/041/080/081 serial EEPROM has a 4K/8K-bit (512/1024-byte) capacity and supports the standard 2 I CTM-bus serial interface. It is fabricated using Samsung's most advanced CMOS process. Important features are a hardware-based write protection circuit for the entire memory area and software-based write protection logic for the lower 128 bytes. Software-based protection is for KS24C040/080 KS24C040/080. Hardware-based write protection is controlled by the state of the write-protect (WP) pin. The software-based method is one-time programmable and permanent. Using page write mode, you can load up to 16 bytes of data into the EEPROM in a single write operation. Another significant feature of the KS24C040/041/080/081 KS24C040/041/080/081 is its support of fast mode and standard mode. FEATURES 2 I C-Bus Interface Operating Characteristics · Two-wire serial interface · Operating voltage: 2.7 V to 5.5 V · Automatic word address increment · Operating current: 3.3 V at 100 kHz Maximum supply current: < 0.1 mA EEPROM · 4K/8K-bit (512/1024-byte) storage area · 16-byte page buffer · Typical 6-millisecond write cycle time with auto-erase function · Hardware-based write protection for the entire EEPROM (using the WP pin) Maximum stand-by current: < 5 µA · Operating temperature range: ­ 25°C to + 70°C · Operating clock frequencies: - 100 kHz at standard mode 400 kHz at fast mode · Electrostatic discharge (ESD) · Software-based write protection for the lower 128-byte EEPROM (KS24C040/080 KS24C040/080 only) · EEPROM programming voltage generated on chip Packages · More than 1,000,000 erase/write cycles · 8-pin DIP and SOP · Greater than 100 years data retention · 8-pin TSSOP is under development - 3,000 V (HBM) - 300 V (MM) KS24C040/041/080/081 KS24C040/041/080/081 SERIAL EEPROM DATA SHEET * Under development SDA Control Logic WP SCL HV Generation Timing Control Start/Stop Logic Slave Address Comparator Word Address Pointer Row Decoder EEPROM Cell Array 512 x 8 Bits 1,024 x 8 Bits A0 A1 A2 Column Decoder Data Register D OUT and ACK Figure 1. KS24C040/041/080/081 KS24C040/041/080/081 Block Diagram 2 March 1998 DATA SHEET KS24C040/041/080/081 KS24C040/041/080/081 SERIAL EEPROM V CC WP SCL SDA KS24C040/041/080/081 KS24C040/041/080/081 A0 NOTE: A1 A2 V SS The KS24C040/041/080/081 KS24C040/041/080/081 is currently available in an 8-pin DIP and SOP package. TSSOP is under development. Figure 2. Pin Assignment Diagram Table 1. KS24C040/041/080/081 KS24C040/041/080/081 Pin Descriptions Name Type Description Circuit Number A0 Input 1 A1, A2 Input The A0 pin is unused by the KS24C040/041/080/081 KS24C040/041/080/081; however, to ensure proper operation it must be connected to the own Vcc or Vss. Floating is not permitted. Input pins for device address. The A1 pin is unused by the KS24C080/081 KS24C080/081. To configure the device address, these pins should be connected to V CC or VSS. 1 Floating is not permitted. VSS ­ SDA I/O SCL Ground pin. ­ 2 Bi-directional data pin for the I C-bus serial data interface. Pin configuration is Schmitt trigger input is open-drain output. An external pull-up resistor must be connected to VCC. Typical values for this pull-up resistor are 4.7 K (100 kHz) and 1 K (400 kHz). 3 Input Schmitt trigger input pin for serial clock input. 2 WP Input Input pin for hardware write protection control. If you tie this pin to VCC, the write function is disabled to protect previously written data in the entire memory; if you tie it to VSS, the write function is enabled. 1 VCC ­ Single power supply. ­ NOTE: See the following page for diagrams of pin circuit types 1, 2 and 3. March 1998 3 KS24C040/041/080/081 KS24C040/041/080/081 SERIAL EEPROM DATA SHEET Vcc SC NOISE FILTER L A0, A1, A2, WP Figure 4. Pin Circuit Type 2 Figure 3. Pin Circuit Type 1 SDA DATA OUT V SS NOISE FILTER Figure 5. Pin Circuit Type 3 4 March 1998 DATA IN DATA SHEET KS24C040/041/080/081 KS24C040/041/080/081 SERIAL EEPROM FUNCTION DESCRIPTION 2 I C-BUS INTERFACE 2 The KS24C040/041/080/081 KS24C040/041/080/081 supports the I C-bus serial interface data transmission protocol. The two-wire bus consists of a serial data line (SDA) and a serial clock line (SCL). The SDA and the SCL lines must be connected to VCC by a pull-up resistor that is located somewhere on the bus. Any device that puts data onto the bus is defined as the "transmitter" and any device that gets data from the bus is the "receiver." The bus is controlled by a master device which generates the serial clock, controls bus access, and generates Start and Stop conditions. Using the A0,A1 and A2 input pins, up to four KS24C040/041 KS24C040/041 or two 2 KS24C080/081 KS24C080/081 device can be connect to the same I C-bus as slave (see Figure 6). Both master and slave can operate as transmitter or receiver, but the master device determines which bus operating mode is active. Vcc Vcc R R SDA SCL Slave 1 Slave 2 KS24C080 KS24C080 Tx/Rx A0 A1 A2 KS24C080 KS24C080 Tx/Rx A0 A1 A2 To Vcc or Vss Bus Master (Transmitter/ Receiver) To Vcc or Vss MCU NOTES 1. The A0 pin does not affect the device address of the KS24C040/041/080/081 KS24C040/041/080/081. 2. The A1 pin does not affect the device address of the KS24C080/081 KS24C080/081. 2 Figure 6. Typical Configuration (16 KBits of Memory on the I C-Bus) March 1998 5 KS24C040/041/080/081 KS24C040/041/080/081 SERIAL EEPROM DATA SHEET 2 I C-BUS PROTOCOLS 2 Here are several rules for I C-bus transfers: - A new data transfer can be initiated only when the bus is currently not busy. - Data is always transferred MSB first. - During a data transfer, the data line (SDA) must remain stable. 2 The I C-bus interface supports the following communication protocols: · Bus not busy: The SDA and SCL lines remain High level when the bus is not active. · Start condition: Start condition is initiated by a High-to-Low transition of the SDA line while SCL remains High level. All bus commands must be preceded by a Start condition. · Stop condition: A Stop condition is initiated by a Low-to-High transition of the SDA line while SCL remains High level. All bus operations must be completed by a Stop condition (see Figure 7). SCL SDA START CONDITION DATA or ACK VALID DATA CHANGE STOP CONDITION Figure 7. Data Transmission Sequence · Data valid: Following a Start condition, the data is valid when the data line remains stable for the duration of the High period of SCL. New data must be put onto the bus while SCL is Low. Bus timing is one clock pulse per data bit. The number of data bytes to be transferred is determined by the master device. The total number of bytes that can be transferred in one operation is theoretically unlimited. · ACK (Acknowledge): An ACK signal indicates that a data transfer was completed successfully. The transmitter (master or slave) releases the bus after transmitting eight bits. During the 9th clock, which the master generates, the receiver pulls the SDA line Low to acknowledge that it successfully received the eight bits of data (see Figure 8). But the slave does not send an ACK if a internal write cycle is still in progress. In data read operations, the slave releases the SDA line after transmitting 8 bits of data and then monitors the line for an ACK signal during the 9th clock period. If an ACK is detected but no Stop condition, the slave will continue to transmit data. If an ACK is not detected, the slave terminates data transmission and waits for a Stop condition to be issued by the master before returning to its stand-by mode. 6 March 1998 DATA SHEET KS24C040/041/080/081 KS24C040/041/080/081 SERIAL EEPROM MASTER SCL LINE Bit 1 Bit 9 DATA FROM TRANSMITTER ACK FROM RECEIVER ACK Figure 8. Acknowledge Response From Receiver · · Slave Address: After the master initiates a Start condition, it must output the address of the device to be accessed. The most significant four bits of the slave address are called the "device identifier". The identifier for the KS24C040/041/080/081 KS24C040/041/080/081 is "1010B 1010B". The next three bits comprise the address of a specific device. The device address is defined by the state of the A0, A1 and A2 pins. Using this addressing scheme, you can cascade up to four KS24C040/041 KS24C040/041 or two KS24C080/081 KS24C080/081 on the bus (see Table 2 below). Unused pins (A0 for KS24C040/041 KS24C040/041, A0 and A1 for KS24C080/081 KS24C080/081) must be connected to VCC or VSS. Floating is not permitted. The b1 is "don't care" for both the KS24C040/041 KS24C040/041 and KS24C080/081 KS24C080/081. The b2 is "don't care" for the KS24C080/081 KS24C080/081. The bits which are "don't care" are used by the master to select which of the blocks of internal memory (1 block = 256 words) are to be accessed. The bits which are "don't care" are in effect the most significant bits of the word address. Read/Write: The final (eighth) bit of the slave address defines the type of operation to be performed. When the R/W bit is "1", a read operation is executed; when it is "0", a write operation is executed. Table 2. Slave Device Addressing Function Device Identifier b7 Read Write Write-protect 1 1 0 b6 0 0 1 b5 1 1 1 b4 0 0 0 R/W Bit Device Address b3 b2 A2 (1) A1 A2 A1 A2 A1 b1 b0 X (2) 1 X (2) 0 X (2) 0 NOTES: 1. The b2 is a "don't care" for the KS24C080/081 KS24C080/081. 2. X = Don't care March 1998 7 KS24C040/041/080/081 KS24C040/041/080/081 SERIAL EEPROM DATA SHEET BYTE WRITE OPERATION In a complete byte write operation, the master transmits the slave address, word address, and one data byte to the KS24C040/041/080/081 KS24C040/041/080/081 slave device(see Figure 9). S T A SLAVE WORD R ADDRESS ADDRESS T DATA A C K A C K S T O P A C K Figure 9. Byte Write Operation Following the Start condition, the master puts the device identifier (4 bits), the device address (3 bits), and an R/W bit set to "0" onto the bus. The addressed KS24C040/041/080/081 KS24C040/041/080/081 generates an ACK and waits for the next byte. The next byte to be transmitted by the master is the word address. This 8-bit address is written into the word address pointer of the KS24C040/041/080/081 KS24C040/041/080/081. When the KS24C040/041/080/081 KS24C040/041/080/081 receives the word address, it responds by issuing an ACK and then waits for the next 8-bit data. When it receives the data byte, the KS24C040/041/080/081 KS24C040/041/080/081 again responds with an ACK. The master terminates the transfer by generating a Stop condition, at which time the KS24C040/041/080/081 KS24C040/041/080/081 begins the internal write cycle. While the internal write cycle is in progress, all KS24C040/041/080/081 KS24C040/041/080/081 inputs are disabled and the KS24C040/041/080/081 KS24C040/041/080/081 does not respond to additional requests from the master. 8 March 1998 DATA SHEET KS24C040/041/080/081 KS24C040/041/080/081 SERIAL EEPROM PAGE WRITE OPERATION The KS24C040/041/080/081 KS24C040/041/080/081 can also perform 16-byte page write operation. A page write operation is initiated in the same way as a byte write operation. However, instead of finishing the write operation after the first data byte is transferred, the master can transmit up to 15 additional bytes. The KS24C040/041/080/081 KS24C040/041/080/081 responds with an ACK each time it receives each complete byte of data (see Figure 10). S T A R T SLAVE ADDRESS WORD ADDRESS n A C K DATA n A C K S T O P DATA ( n + 15) A C K Figure 10. Page Write Operation The KS24C040/041/080/081 KS24C040/041/080/081 automatically increments the word address pointer each time it receives a complete data byte. When one byte has been received, the internal word address pointer increments to the next address and the next data byte can be received. If the master transmits more than 16 bytes before it generates a Stop condition to end the page write operation, the KS24C040/041/080/081 KS24C040/041/080/081 word address pointer value "rolls over" and the previously received data is overwritten. If the master transmits less than 16 bytes and generates a Stop condition, the KS24C040/041/080/081 KS24C040/041/080/081 writes the received data to the corresponding EEPROM address. During a page write operation, all inputs are disabled and there is no response to additional requests from the master until the internal write cycle has been completed. March 1998 9 KS24C040/041/080/081 KS24C040/041/080/081 SERIAL EEPROM DATA SHEET POLLING FOR AN ACK SIGNAL When the master issues a Stop condition to indicate the end of a write operation, the KS24C040/041/080/081 KS24C040/041/080/081 starts an internal write cycle. The master can then immediately begin polling for an ACK from the slave device. To poll for an ACK signal in a write operation, the master issues a Start condition followed by the slave address. As long as the KS24C040/041/080/081 KS24C040/041/080/081 remains busy with an internal write cycle, no ACK is returned. When the KS24C040/041/080/081 KS24C040/041/080/081 completes the write operation, it returns an ACK and the master can then proceed with the next read or write operation (see Figure 11). Send write command Send Stop condition to initiate write cycle Send Start condition W Send slave address with R/ W bit = " ACK = WW ? NO YES Start next operation Figure 11. Master Polling for an ACK Signal from a Slave Device 10 March 1998 DATA SHEET KS24C040/041/080/081 KS24C040/041/080/081 SERIAL EEPROM SOFTWARE-BASED WRITE PROTECTION (KS24C040/080 KS24C040/080 ONLY) You can write-protect the lower 128 bytes of the EEPROM, locations 00H-7FH 00H-7FH, in one operation. To do this, you simply write a value to a one-time, write-only register. After you have accessed this write protection once, all write attempts to access the lower 128-byte area are ignored. In other words, the write protection is permanent. 2 The effect of such a failed attempt is processed in the same way as an invalid I C-bus protocol. To enable write protection, you must execute a write operation to the write protection register. To access the write protection register, you use the device address "0110". The word address and data in this write operation can be any value and the timing and wave form characteristics are identical to a normal byte write operation (see Figure 12). S T A SLAVE R ADDRESS T WORD ADDRESS (ignored) A C K A C K S DATA T (ignored) O P A C K Figure 12. Write Protection Operation HARDWARE-BASED WRITE PROTECTION You can also write-protect the entire memory area of the KS24C040/041/080/081 KS24C040/041/080/081. This method of write protection is controlled by the state of the Write Protect (WP) pin. When the WP pin is connected to VCC, all attempts to write a value to it are ignored. The failed attempt is 2 processed in the same way as an invalid I C-bus protocol. However, by connecting the WP pin to VSS, the write function is allowed for the entire memory. These write protection features effectively change the EEPROM to a ROM in order to prevent data from being overwritten. Whenever the write function is disabled, a slave address and word address is acknowledged on the bus, but data bytes are not acknowledged. March 1998 11 KS24C040/041/080/081 KS24C040/041/080/081 SERIAL EEPROM DATA SHEET CURRENT ADDRESS BYTE READ OPERATIONS The internal word address pointer maintains the address of the last word accessed, incremented by one. Therefore, if the last access (either read or write) was to the address "n", the next read operation would access data at address "n+1". When the KS24C040/041/080/081 KS24C040/041/080/081 receives a slave address with the R/W bit set to "1", it issues an ACK and sends the eight bits of data. The master does not acknowledge the transfer but it does generate a Stop condition. In this way, the KS24C040/041/080/081 KS24C040/041/080/081 effectively stops the transmission (see Figure 13). S T A R T SLAVE ADDRESS A C K DATA S T O P NO ACK Figure 13. Current Address Byte Read Operation RANDOM ADDRESS BYTE READ OPERATIONS Using random read operations, the master can access any memory location at any time. Before it issues the slave address with the R/W bit set to "1", the master must first perform a "dummy" write operation. This operation is performed in the following steps: 1. The master first issues the Start condition, the slave address, and the word address it is to read. (This step sets the internal word address pointer of the KS24C040/041/080/081 KS24C040/041/080/081 to the desired address.) 2. When the master receives an ACK for the word address, it immediately re-issues a Start condition followed by another slave address, and with the R/W bit set to "1". 3. The KS24C040/041/080/081 KS24C040/041/080/081 then sends an ACK and the 8-bit data stored at the desired address. 4. At this point, the master does not acknowledge the transmission, but generates a Stop condition instead. 5. In response, the KS24C040/041/080/081 KS24C040/041/080/081 stops transmitting data and reverts to its stand-by mode (see Figure 14). 12 March 1998 DATA SHEET S T A R T KS24C040/041/080/081 KS24C040/041/080/081 SERIAL EEPROM S T A R T WORD ADDRESS SLAVE ADDRESS A C K SLAVE ADDRESS S T O P DATA (n) A C K A C K NO ACK Figure 14. Random Address Byte Read Operation SEQUENTIAL READ OPERATIONS Sequential read operations can be performed in two ways: as a series of current address reads or as random address reads. The first word is sent in the same way as the previous read mode used on the bus. The next time, however, the master responds with an ACK, indicating that it requires additional data. The KS24C040/041/080/081 KS24C040/041/080/081 continues to output data for each ACK it receives. To stop the sequential read operation, the master does not respond with an ACK, but instead issues a Stop condition. Using this method, data is output sequentially with the data from address "n" followed by the data from "n+1". The word address pointer for read operations increments all word addresses, allowing the entire EEPROM to be read sequentially in a single operation. After the entire EEPROM has been read, the word address pointer "rolls over" and the KS24C040/041/080/081 KS24C040/041/080/081 continues to transmit data for each ACK it receives from the master (see Figure 15). S T A R T SLAVE ADDRESS DATA (n) A C K DATA (n+x) A C K A C K S T O P NO ACK Figure 15. Sequential Read Operation March 1998 13 KS24C040/041/080/081 KS24C040/041/080/081 SERIAL EEPROM DATA SHEET ELECTRICAL DATA Table 3. Absolute Maximum Ratings (TA = 25 °C) Parameter Symbol Conditions Rating Unit Supply voltage VCC ­ - 0.3 to + 7.0 V Input voltage VIN ­ - 0.3 to VCC + 0.3 V Output voltage VO ­ - 0.3 to VCC + 0.3 V Operating temperature TA ­ - 25 to + 70 °C Storage temperature TSTG ­ - 65 to + 150 °C Electrostatic discharge VESD HBM 3000 V MM 300 Table 4. D.C. Electrical Characteristics (TA = - 25 °C to + 70 °C, VCC = 2.7 V to 5.5 V) Parameter Symbol Conditions Min Typ Max Unit ­ ­ 0.3 VCC V 0.7 VCC ­ ­ V VIN = 0 to VCC ­ ­ 10 µA ­ 10 µA Input Low voltage VIL Input High voltage VIH Input leakage current ILI Output leakage current ILO VO = 0 to VCC ­ Output Low voltage VOL IOL = 3 mA, VCC = 2.7 V ­ ­ 0.4 V ICC1 (Write) VCC = 5.5 V, 400 kHz ­ ­ 3 mA ICC2 (Write) VCC = 3.3 V, 100 kHz ­ ­ 1 ICC3 (Read) VCC = 5.5 V, 400 kHz ­ ­ 0.5 ICC4 (Read) VCC = 3.3 V, 100 kHz ­ ­ 0.1 ICC5 VCC =SDA = SCL = 5.5 V, all other inputs = 0 V ­ ­ 10 ICC6 VCC =SDA = SCL = 3.3 V, all other inputs = 0 V ­ ­ 5 Supply current Stand-by current 14 SCL, SDA, A0, A1, A2 March 1998 µA DATA SHEET KS24C040/041/080/081 KS24C040/041/080/081 SERIAL EEPROM Table 4. D.C. Electrical Characteristics (Continued) (TA = - 25 °C to + 70 °C, VCC = 2.7 V to 5.5 V) Parameter Symbol Conditions Min Typ Max Unit Input capacitance CIN 25 °C, 1 MHz, VCC = 5 V, VIN = 0 V, A0, A1, A2, SCL and WP pin ­ ­ 10 pF Input / Output capacitance CI/O 25 °C, 1 MHz, VCC = 5 V VI/O = 0 V, SDA pin ­ ­ 10 Table 5. A.C. Electrical Characteristics (TA = - 25 °C to + 70 °C, VCC = 2.7 V to 5.5 V) Parameter Symbol Conditions VCC = 2.7V to 5.5 V (Standard Mode) VCC = 4.5V to 5.5 V (Fast Mode) Min Max Min Unit Max External clock frequency fCLK ­ 0 100 0 400 kHz Clock High time tHIGH ­ 4 ­ 0.6 ­ µs Clock Low time tLOW ­ 4.7 ­ 1.3 ­ µs Rising time tR SDA, SCL ­ 1 ­ 0.3 µs Falling time tF SDA, SCL ­ 0.3 ­ 0.3 µs Start condition hold time tHD:STA ­ 4 ­ 0.6 ­ µs Start condition setup time tSU:STA ­ 4.7 ­ 0.6 ­ µs Data input hold time tHD:DAT ­ 0 ­ 0 ­ µs Data input setup time tSU:DAT ­ 0.25 ­ 0.1 ­ µs Stop condition setup time tSU:STO ­ 4 ­ 0.6 ­ µs Bus free time tBUF Before new transmission 4.7 ­ 1.3 ­ µs Data output valid from clock low (see NOTE) tAA ­ 0.3 3.5 ­ 0.9 µs Noise spike width tSP ­ ­ 100 ­ 50 ns Write cycle time tWR ­ ­ 10 ­ 10 ms Data retention tDR ­ 100 ­ 100 ­ Years ­ ­ 1,000,000 ­ 1,000,000 ­ Cycles Endurance NOTE: When acting as a transmitter, the KS24C040/041/080/081 KS24C040/041/080/081 must provide an internal minimum delay time to bridge the undefined period (minimum 300 ns) of the falling edge of SCL. This is required to avoid unintended generation of a Start or Stop condition. March 1998 15 KS24C040/041/080/081 KS24C040/041/080/081 SERIAL EEPROM DATA SHEET tHIGH tF tR tLOW SCL tSU:STA tHD:STA tHD:DAT tSU:DAT tSU:STO SDA IN tBUF tAA SDA OUT Figure 14. Timing Diagram for Bus Operations 16 March 1998 DATA SHEET KS24C040/041/080/081 KS24C040/041/080/081 SERIAL EEPROM SCL SDA 8th BIT ACK WORD n tWR STOP CONDITION START CONDITION Figure 15. Write Cycle Timing Diagram March 1998 17 KS24C040/041/080/081 KS24C040/041/080/081 SERIAL EEPROM DATA SHEET MECHANICAL DATA This section contains package dimension data for the Samsung 8-DIP-300 8-DIP-300, 8-SOP-225 8-SOP-225 and 8-TSSOP packages. #5 0-15° 0.25 +0.1 6.40 8-DIP-300 8-DIP-300 W0.05 7.62 W0.2 #8 #4 #1 W 3.40 9.20 0.2 5.08MAX 08MAX W0.2 9.60 MAX 0.46 1.52 W0.3 W0.1 W0.1 3.30 2.54 0.33MIN 33MIN (0.79) : NOTE Dimensions are in millimeters. Figure 20. 8-DIP-300 8-DIP-300 Package Dimensions 18 March 1998 DATA SHEET KS24C040/041/080/081 KS24C040/041/080/081 SERIAL EEPROM W° 0 #4 0.15 W0.2 1.55 4.92 W0.2 5.13 MAX 5.72 +0.10 - 0.05 1.95MAX 95MAX #1 W 6.0 3.95 8-SOP-225 8-SOP-225 0.50 .20 #5 W0.2 W0.3 #8 (0.56) 1.27 0.41 0.05MIN 05MIN 0.10 MAX W0.1 NOTE : Dimensions are in millimeters. Figure 21. 8-SOP-225 8-SOP-225 Package Dimensions March 1998 19 KS24C040/041/080/081 KS24C040/041/080/081 SERIAL EEPROM DATA SHEET W 0 ° #5 #4 0.125 +0.10 - 0.05 0.15 1.20MAX 20MAX 3.10 MAX 0.10 MAX 0.65 0.30 W0.1 NOTES: 1. Dimensions are in millimeters. 2. Package dimensions conform to JEDEC MO-153-AA MO-153-AA. Figure 22. 8-TSSOP-SG Package Dimension 20 March 1998 +0. 25 0.50 3.95 #1 W0.2 8-TSSOP-SG + 0.3 6.25 #8