KMM372E160 KMM372E1600BK KMM372E1600BS KMM372E1680BK KMM372E1680BS

KMM372E160(8)0BK/BS KMM372E160(8)0BK/BS EDO Mode 16M x 72 DRAM DIMM with ECC Using 16Mx4, 4K & 8K Refresh, 5V GENERAL

DRAM MODULE KMM372E160 KMM372E160(8)0BK/BS KMM372E160 KMM372E160(8)0BK/BS EDO Mode 16M x 72 DRAM DIMM with ECC Using 16Mx4, 4K & 8K Refresh, 5V GENERAL DESCRIPTION FEATURES The Samsung KMM372E160 KMM372E160(8)0B is a 16Mx72bits Dynamic RAM high density memory module. The Samsung KMM372E160 KMM372E160(8)0B consists of eighteen CMOS 16Mx4bits DRAMs in SOJ/TSOP-II 400mil packages and two 16 bits driver IC in TSSOP package mounted on a 168-pin glassepoxy substrate. A 0.1 or 0.22uF decoupling capacitor is mounted on the printed circuit board for each DRAM. The KMM372E160 KMM372E160(8)0B is a Dual In-line Memory Module and is intended for mounting into 168 pin edge connector sockets. · Part Identification PERFORMANCE RANGE Speed tRAC tCAC tRC tHPC -5 50ns 18ns 84ns 20ns -6 60ns 20ns 104ns 25ns Part number PKG KMM372E1600BK KMM372E1600BK SOJ KMM372E1600BS KMM372E1600BS TSOP KMM372E1680BK KMM372E1680BK SOJ 4K ROR Ref. 4K/64ms 8K/64ms PIN NAMES Pin Front Pin Front Pin Front Pin Back Pin Back 29 *CAS2 57 30 RAS0 58 31 OE0 59 60 VSS 32 61 A0 33 62 A2 34 63 A4 35 64 A6 36 65 A8 37 66 A10 38 67 A12 39 68 VCC 40 41 RFU 69 42 RFU 70 71 43 VSS 44 OE2 72 45 RAS2 73 46 CAS4 74 47 *CAS6 75 76 W2 48 77 VCC 49 50 RSVD 78 51 RSVD 79 52 DQ18 80 53 DQ19 81 82 VSS 54 55 DQ20 83 56 DQ21 84 VSS DQ36 DQ37 DQ38 DQ39 VCC DQ40 DQ41 DQ42 DQ43 DQ44 VSS DQ45 DQ46 DQ47 DQ48 DQ49 VCC DQ50 DQ51 DQ52 DQ53 VSS RSVD RSVD VCC RFU *CAS1 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 *CAS3 *RAS1 RFU VSS A1 A3 A5 A7 A9 A11 *A13 VCC RFU B0 VSS RFU *RAS3 *CAS5 *CAS7 PDE VCC RSVD RSVD DQ54 DQ55 VSS DQ56 DQ57 VSS DQ0 DQ1 DQ2 DQ3 VCC DQ4 DQ5 DQ6 DQ7 DQ8 VSS DQ9 DQ10 DQ11 DQ12 DQ13 VCC DQ14 DQ15 DQ16 RSVD VSS RSVD RSVD VCC W0 CAS0 CBR Ref. 8K 4K/64ms KMM372E1680BS KMM372E1680BS TSOP · Extended Data Out Mode Operation · CAS-before-RAS Refresh capability · RAS-only and Hidden refresh capability · TTL compatible inputs and outputs · Single 5V±10% power supply · JEDEC standard pinout & Buffered PDpin · Buffered input except RAS and DQ · PCB : Height(1250mil), double sided component PIN CONFIGURATIONS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Ref. DQ22 DQ23 VCC DQ24 RFU RFU RFU RFU DQ25 DQ26 DQ27 VSS DQ28 DQ29 DQ30 DQ31 VCC DQ32 DQ33 DQ34 DQ35 VSS PD1 PD3 PD5 PD7 ID0 VCC 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 Pin Back 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 DQ58 DQ59 VCC DQ60 RFU RFU RFU RFU DQ61 DQ62 DQ63 VSS DQ64 DQ65 DQ66 DQ67 VCC DQ68 DQ69 DQ70 DQ71 VSS PD2 PD4 PD6 PD8 ID1 VCC Pin Names Function A0, B0, A1 - A11 Address Input(4K ref.) A0, B0, A1 - A12 Address Input(8K ref.) DQ0 - DQ71 Data In/Out W0, W2 Read/Write Enable OE0, OE2 Output Enable RAS0, RAS2 Row Address Strobe CAS0, CAS4 Column Address Strobe VCC Power(+5V) VSS Ground NC No Connection PDE Presence Detect Enable PD1 - 8 Presence Detect ID0 - 1 ID bit RSVD Reserved Use RFU Reserved for Future Use Pins marked * are not used in this module. PD & ID Table 50NS 60NS PD1 PD2 PD3 PD4 PD5 PD6 PD7 PD8 1 1 1 1 1 0 0 0 1 1 1 1 1 1 1 0 ID0 NOTE : A12 is used for only KMM372E1680BK/BS KMM372E1680BK/BS (8K Ref.) Pin 0 0 0 ID1 0 PD Note :PD & ID Terminals must each be pulled up through a resistor to V CC at the next higher level assembly. PDs will be either open (NC) or driven to V SS via on-board buffer circuits. PD : 0 for Vol of Drive IC & 1 for N.C ID Note : IDs will be either open (NC) or connected directly to V SS without a buffer. ID : 0 for Vss & 1 for N.C DRAM MODULE KMM372E160 KMM372E160(8)0BK/BS FUNCTIONAL BLOCK DIAGRAM RAS0 CAS0 OE0 W0 A0 A1-A11 A1-A11(A12) RAS2 CAS4 OE2 W2 B0 A1-A11 A1-A11(A12) U0 DQ0 DQ1 DQ2 DQ3 DQ0 DQ1 DQ2 DQ3 U1 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 U2 DQ0 DQ1 DQ2 DQ3 DQ8 DQ9 DQ10 DQ11 U3 DQ0 DQ1 DQ2 DQ3 DQ12 DQ13 DQ14 DQ15 U4 DQ0 DQ1 DQ2 DQ3 DQ16 DQ17 DQ18 DQ19 U5 DQ0 DQ1 DQ2 DQ3 DQ20 DQ21 DQ22 DQ23 U6 DQ0 DQ1 DQ2 DQ3 DQ24 DQ25 DQ26 DQ27 U7 DQ0 DQ1 DQ2 DQ3 DQ28 DQ29 DQ30 DQ31 U8 DQ0 DQ1 DQ2 DQ3 U9 DQ32 DQ33 DQ34 DQ35 0.1 or 0.22uF Capacitor under each DRAM Vss DQ40 DQ41 DQ42 DQ43 DQ0 DQ1 DQ2 DQ3 DQ44 DQ45 DQ46 DQ47 U12 DQ0 DQ1 DQ2 DQ3 DQ48 DQ49 DQ50 DQ51 U13 DQ0 DQ1 DQ2 DQ3 DQ52 DQ53 DQ54 DQ55 U14 DQ0 DQ1 DQ2 DQ3 DQ56 DQ57 DQ58 DQ59 U15 DQ0 DQ1 DQ2 DQ3 DQ60 DQ61 DQ62 DQ63 U16 DQ0 DQ1 DQ2 DQ3 DQ64 DQ65 DQ66 DQ67 U17 To all DRAMs DQ0 DQ1 DQ2 DQ3 U11 Vcc DQ36 DQ37 DQ38 DQ39 U10 NOTE : A12 is used for only KMM372E1680BK/BS KMM372E1680BK/BS(8K Ref.) DQ0 DQ1 DQ2 DQ3 DQ0 DQ1 DQ2 DQ3 DQ68 DQ69 DQ70 DQ71 A0 B0 A1-A11 A1-A11(A12) W0, OE0 W2, OE2 U0-U8 U9-U17 U9-U17 U0-U17 U0-U17 U0-U8 U9-U17 U9-U17 DRAM MODULE KMM372E160 KMM372E160(8)0BK/BS ABSOLUTE MAXIMUM RATINGS * Item Symbol Unit VIN, VOUT VCC Tstg PD IOS Voltage on any pin relative VSS Voltage on VCC supply relative to VSS Storage Temperature Power Dissipation Short Circuit Output Current Rating -1 to +7.0 -1 to +7.0 -55 to +125 18 50 V V °C W mA * Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for intended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS (Voltage referenced to V SS, TA = 0 to 70°C) Item Symbol Typ Max Unit VCC VSS VIH VIL Supply Voltage Ground Input High Voltage Input Low Voltage Min 4.5 0 2.4 5.0 0 - 5.5 0 V V V V -1.0*2 VCC*1 0.8 *1 : VCC+2.0V at pulse width20ns, which is measured at VCC. *2 : -2.0V at pulse width20ns, which is measured at VSS. DC AND OPERATING CHARACTERISTICS (Recommended operating conditions unless otherwise noted) Symbol Speed ICC1 KMM372E1600BK/BS KMM372E1600BK/BS KMM372E1680BK/BS KMM372E1680BK/BS Unit Min Max Min Max -5 -6 - 2160 1980 - 1620 1440 mA mA ICC2 Dont care - 100 - 100 mA ICC3 -5 -6 - 2160 1980 - 1620 1440 mA mA ICC4 -5 -6 - 1980 1800 - 1800 1620 mA mA ICC5 Dont care - 30 - 30 mA ICC6 -5 -6 - 2160 1980 - 1620 1440 mA mA II(L) IO(L) Dont care -10 -5 10 5 -10 -5 10 5 uA uA VOH VOL Dont care 2.4 - 0.4 2.4 - 0.4 V V ICC1* : Operating Current * (RAS, CAS, Address cycling @tRC=min) ICC2 : Standby Current (RAS=CAS=W=VIH) ICC3* : RAS Only Refresh Current * (CAS=VIH, RAS cycling @tRC=min) ICC4* : Extended Data Out Mode Current * (RAS=VIL, CAS cycling : tHPC=min) ICC5 : Standby Current (RAS=CAS=W=Vcc-0.2V) ICC6* : CAS-Before-RAS Refresh Current * (RAS and CAS cycling @tRC=min) I(IL) : Input Leakage Current (Any input 0VINVcc+0.5V, all other pins not under test=0 V) I(OL) : Output Leakage Current(Data Out is disabled, 0VVOUTVcc) VOH : Output High Voltage Level (IOH = -5mA) VOL : Output Low Voltage Level (IOL = 4.2mA) * NOTE : ICC1, ICC3, ICC4 and ICC6 are dependent on output loading and cycle rates. Specified values are obtained with the output open. ICC is specified as an average current. In ICC1 and ICC3, address can be changed maximum once while RAS=VIL. In ICC4, address can be changed maximum once within one EDO mode cycle time, tHPC. DRAM MODULE KMM372E160 KMM372E160(8)0BK/BS CAPACITANCE (TA = 25°C, f = 1MHz) Item Symbol Min Max Unit Input capacitance[A0, B0, A1 - A12] Input capacitance[W0, W2, OE0, OE2] Input capacitance[RAS0, RAS2] Input capacitance[CAS0, CAS4] Input/Output capacitance[DQ0 - 71] CIN1 CIN2 CIN3 CIN4 CDQ - 20 20 73 20 17 pF pF pF pF pF AC CHARACTERISTICS (0°CTA70 CTA70°C, VCC=5.0V±10%. See notes 1,2.) Test condition : Vih/Vil=2.4/0.8V, Voh/Vol=2.0/0.8V, output loading CL=100pF Parameter -5 Symbol Min Random read or write cycle time Read-modify-write cycle time Access time from RAS Access time from CAS Access time from column address CAS to output in Low-Z OE to output in Low-Z Output buffer turn-off delay from CAS Transition time(rise and fall) RAS precharge time RAS pulse width RAS hold time CAS hold time CAS pulse width RAS to CAS delay time RAS to column address delay time CAS to RAS precharge time Row address set-up time Row address hold time Column address set-up time Column address hold time Column address to RAS lead time Read command set-up time Read command hold referenced to CAS Read command hold referenced to RAS Write command set-up time Write command hold time Write command pulse width Write command to RAS lead time Write command to CAS lead time Data set-up time Data hold time Refresh period(4K & 8K) CAS to W delay time RAS to W delay time tRC tRWC tRAC tCAC tAA tCLZ tOLZ tCEZ tT tRP tRAS tRSH tCSH tCAS tRCD tRAD tCRP tASR tRAH tASC tCAH tRAL tRCS tRCH tRRH tWCS tWCH tWP tRWL tCWL tDS tDH tREF tCWD tRWD -6 Max 84 Min Unit 104 133 Note Max ns 155 ns 50 60 ns 18 20 ns 3,4,5,13 30 35 ns 3,10,13 ns 3,13 8 8 8 8 8 18 1 50 30 50 ns 3,13 8 18 ns 6,11,13 1 50 ns 2 40 10K 18 60 ns 10K 20 36 ns ns ns 43 13 13 8 10K 10 10K ns 18 32 18 40 ns 4,13 13 20 13 25 ns 10,13 10 10 ns 13 5 5 ns 13 8 8 ns 13 0 0 ns 8 10 ns 30 35 ns 0 0 ns 0 0 ns 8 -2 -2 ns 8,13 7 13 0 0 ns 10 10 ns 10 10 ns 18 20 ns 8 10 ns -2 -2 ns 9,13 13 15 ns 9,13 64 64 13 ms 36 38 ns 7 73 83 ns 7,13 DRAM MODULE KMM372E160 KMM372E160(8)0BK/BS AC CHARACTERISTICS (0°CTA70 CTA70°C, VCC=5.0V±10%. See notes 1,2.) Parameter Column address to W delay time CAS precharge time to W delay time CAS setup time(CAS-before-RAS refresh) CAS hold time(CAS-before-RAS refresh) RAS to CAS precharge time Access time from CAS precharge Hyper page cycle time Hyper page read-modify-write cycle time CAS precharge time(Hyper page cycle) RAS pulse width (Hyper page cycle) RAS hold time from CAS precharge W to RAS precharge time(C-B-R refresh) W to RAS hold time(C-B-R refresh) OE access time OE to data delay Output buffer turn off delay time from OE OE command hold time Output data hold time(C-B-R refresh) Output buffer turn off delay time from RAS Output buffer turn off delay time from W W to data delay OE to CAS hold time CAS hold time to OE OE precharge time W pulse width (Hyper page cycle) Symbol tAWD tCPWD tCSR tCHR tRPC tCPA tHPC tHPRWC tCP tRASP tRHCP tWRP tWRH tOEA tOED tOEZ tOEH tDOH tREZ tWEZ tWED tOCH tCHO tOEP tWPE -5 Min -6 Max Min Max Unit Note 7 48 53 ns 53 60 ns 10 10 ns 13 8 8 ns 13 3 3 33 ns 40 13 ns 3,13 20 25 ns 12 70 77 ns 12 8 10 ns 50 200K 60 200K ns 35 40 ns 13 15 15 ns 13 8 8 ns 13 18 18 8 20 18 13 8 18 15 10 ns 13 ns 18 13 ns 13 ns ns 13 3 15 10 3 15 ns 6,11 8 18 8 20 ns 6,13 13 20 20 ns 5 5 ns 5 5 ns 5 5 ns 5 5 ns Present Detect Read Cycle PDE to Valid PD bit PDE to PD bit Inactive tPD tPDOFF 10 2 7 10 2 ns 7 ns DRAM MODULE KMM372E160 KMM372E160(8)0BK/BS NOTES 1. An initial pause of 200us is required after power-up followed by any 8 RAS-only or CAS-before-RAS refresh cycles before proper device operation is achieved. 2. Input voltage levels are Vih/Vil. V IH(min) and VIL(max) are reference levels for measuring timing of input signals. Transition times are measured between VIH(min) and VIL(max) and are assumed to be 5ns for all inputs. 3. Measured with a load equivalent to 2 TTL loads and 100pF. 4. Operation within the tRCD(max) limit insures that tRAC(max) can be met. tRCD(max) is specified as a reference point only. If tRCD is greater than the specified tRCD(max) limit, then access time is controlled exclusively by tCAC. 5. Assumes that tRCDtRCD(max). 6. This parameter defines the time at which the output achieves the open circuit condition and is not referenced to VOH or VOL. 7. tWCS, tRWD, tCWD, tAWD and tCPWD are not restrictive operating parameter. They are included in the data sheet as electrical characteristics only. If tWCStWCS(min) the cycle is an early write cycle and the data out pin will remain high impedance for the duration of the cycle. If tRWDtRWD(min), tCWDtCWD(min), tAWDtAWD(min) and tCPWDtCPWD(min). The cycle is a read-modify-write cycle and the data out will contain data read from the selected cell. If neither of the above sets of conditions is satisfied, the condition of data out(at access time) is indeterminate. 8. Either tRCH or tRRH must be satisfied for a read cycle. 9. These parameters are referenced to the CAS leading edge in early write cycles. 10. Operation within the tRAD(max) limit insures that tRAC(max) can be met. tRAD(max) is specified as reference point only. If tRAD is greater than the specified tRAD(max) limit, then access time is controlled by tAA. 11. If RAS goes high before CAS high going, the open circuit condition of the output is achieved by CAS high going. If CAS goes high before RAS high going , the open circuit condition of the output is achieved by RAS going. 12. tASC6ns 13. The timing skew from the DRAM to the DIMM resulted from the addition of buffers. DRAM MODULE KMM372E160 KMM372E160(8)0BK/BS READ CYCLE tRC tRAS RAS VIL - tCSH tCRP CAS tRP VIH - tRCD tCRP tRSH VIH - tCAS VIL - tRAD tASR A VIH VIL - tRAH tRAL tASC tCAH ROW ADDRESS COLUMN ADDRESS tRCH tRCS W tRRH VIH VIL - tWEZ tCEZ tAA OE VIH - tOEZ tOEA VIL - tOLZ tCAC DQ VOH VOL - tRAC OPEN tCLZ tREZ DATA-OUT Dont care Undefined DRAM MODULE KMM372E160 KMM372E160(8)0BK/BS WRITE CYCLE ( EARLY WRITE ) NOTE : DOUT = OPEN tRC tRAS RAS tRP VIH VIL - tCSH tCRP CAS tRSH VIH VIL - VIH VIL - tCRP tCAS tRAD tASR A tRCD tRAH tASC ROW ADDRESS tRAL tCAH COLUMN ADDRESS tCWL tRWL tWCS W OE VIH VIL - VIH VIL - tDS DQ tWCH tWP VIH VIL - tDH DATA-IN Dont care Undefined DRAM MODULE KMM372E160 KMM372E160(8)0BK/BS WRITE CYCLE ( OE CONTROLLED WRITE ) NOTE : DOUT = OPEN tRC tRAS RAS VIL - tCSH tCRP CAS tRP VIH - tRCD tRSH tCAS VIH - tCRP VIL - tRAD tRAL tASR A VIH VIL - tRAH ROW ADDRESS tASC tCAH COLUMN ADDRESS tCWL tRWL W OE tWP VIH VIL - VIH VIL - tOED tDS DQ VIH - tOEH tDH DATA-IN VIL - Dont care Undefined DRAM MODULE KMM372E160 KMM372E160(8)0BK/BS READ - MODIFY - WRITE CYCLE tRWC tRAS RAS VIL - tCRP CAS tRP VIH - tRCD tRSH VIH - tCAS VIL - tASR tRAD tRAH tASC tCAH tCSH A VIH VIL - ROW ADDR COLUMN ADDRESS tAWD tRWL tCWD W tCWL VIH - tWP VIL - tRWD OE tOEA VIH VIL - tOLZ tCLZ tCAC tAA DQ VI/OH VI/OL - tOED tOEZ tRAC VALID DATA-OUT tDS tDH VALID DATA-IN Dont care Undefined DRAM MODULE KMM372E160 KMM372E160(8)0BK/BS HYPER PAGE READ CYCLE tRP tRASP RAS VIH VIL - ¡ó tCSH tCRP CAS VIL - VIL - tHPC tCP tCAS tHPC tCP tCAS tCP tCAS tCAS tRAD tASR A tRCD VIH - VIH - tRHCP tHPC tRAH tASC ROW ADDR tCAH tASC COLUMN ADDRESS tCAH COLUMN ADDRESS tASC tCAH COLUMN ADDR tASC tCAH tREZ COLUMN ADDRESS tRRH tRCS W tRCH VIH - tCPA VIL - tCAC tAA tCPA tCAC tAA OE VIH - tAA tCPA tOCH tOEA tAA tCHO tOEP tOEA VIL - tOEP tCAC tDOH tRAC DQ tCAC tCAC VOH VOL - VALID DATA-OUT tOLZ tCLZ tOEZ tOEA tOEZ tOEZ VALID DATA-OUT VALID DATA-OUT VALID DATA-OUT Dont care Undefined DRAM MODULE KMM372E160 KMM372E160(8)0BK/BS HYPER PAGE WRITE CYCLE ( EARLY WRITE ) NOTE : D OUT = OPEN tRP tRASP RAS VIH - tRHCP VIL - ¡ó tHPC tCRP CAS tRCD tHPC tCP VIH - tCP tCAS VIL - tRSH tCAS tCAS tRAD ¡ó tCSH tASR A VIH VIL - tRAH ROW ADDR. tASC tCAH VIH - tWCH tWCS tWP ¡ó tCAH COLUMN ADDRESS tWCS ¡ó tWCH tWP VIL - tCWL tCWL tRWL VIH - ¡ó VIL - ¡ó tDS DQ tASC ¡ó tWCH tWP tCWL OE tCAH COLUMN ADDRESS COLUMN ADDRESS tWCS W tASC VIH VIL - tDH tDS tDH tDS tDH ¡ó VALID DATA-IN VALID DATA-IN VALID DATA-IN ¡ó Dont care Undefined DRAM MODULE KMM372E160 KMM372E160(8)0BK/BS HYPER PAGE READ-MODIFY-WRITE CYCLE RAS tCSH tHPRWC tRCD tCAS VIL - VIH VIL - tCAS tRAD tRAH ROW ADDR tRAL tCAH tASC tCAH tASC COL. ADDR COL. ADDR tRCS W tCRP tCP VIH - tASR A tRSH VIL - tCRP CAS tRWL tCWL tCWL VIH - tWP VIL - tWP tCWD tCWD tAWD tRWD OE tRP tRASP VIH - VIH - tAWD tCPWD tOEA tOEA VIL - tOED tOED tCAC tAA tDH tOEZ tCAC tAA tDS tDH tOEZ tDS tRAC DQ VI/OH VI/OL - tCLZ tCLZ tOLZ VALID DATA-OUT VALID DATA-IN tOLZ VALID DATA-OUT VALID DATA-IN Dont care Undefined DRAM MODULE KMM372E160 KMM372E160(8)0BK/BS HYPER PAGE READ AND WRITE MIXED CYCLE tRP tRASP RAS VIH - READ(tCAC) READ(tCPA) tHPC tHPC tCP tCP CAS VIH VIL - VIH VIL - tCAS tRAD tASR A tRAH tASC ROW ADDR tCAH COLUMN ADDRESS tRCS W READ(tAA) WRITE VIL - tCAS tRCS tCAH tASC COLUMN ADDRESS tRCH tCAS tCAS tCAH tASC tHPC tCP COL. ADDR tRCH tASC tCAH COL. ADDR tWCH tRCH tWCS VIH VIL - tWPE tCLZ tWED tCPA OE VIH VIL - tOEA tCAC tAA DQ VI/OH VI/OL - tWEZ tDH tWEZ tDS VALID VALID DATA-IN tREZ tAA tRAC VALID DATA-OUT DATA-OUT VALID DATA-OUT Dont care Undefined DRAM MODULE KMM372E160 KMM372E160(8)0BK/BS RAS - ONLY REFRESH CYCLE* NOTE : W, OE, DIN = Dont care DOUT = OPEN tRC RAS VIH - tRP tRAS VIL - tRPC tCRP CAS VIH VIL - tASR A tCRP VIH VIL - tRAH ROW ADDR CAS - BEFORE - RAS REFRESH CYCLE NOTE : OE , A = Dont care tRC tRP RAS VIL - tRPC tCP CAS tRAS VIH - VIH - tRPC tCSR tCHR VIL - tWRP W tRP tWRH VIH VIL - tCEZ DQ VOH VOL - OPEN Dont care Undefined * In RAS-only refresh cycle of 64Mb A-dile & B-die, when CAS signal transits from Low to High, the valid data may be cut off. DRAM MODULE KMM372E160 KMM372E160(8)0BK/BS HIDDEN REFRESH CYCLE ( READ ) tRC RAS tRAS VIH - tRP tRAS VIL - tCRP CAS tRC tRP tRCD tRSH tCHR VIH VIL - tRAD tASR A VIH VIL - tRAH tASC ROW ADDRESS tCAH COLUMN ADDRESS tRCS W tRRH tWRH tWRP VIH VIL - tAA OE VIH - tOEA VIL - tCEZ tOLZ tCAC tREZ tWEZ tCLZ tRAC DQ VOH VOL - OPEN tOEZ DATA-OUT Dont care Undefined DRAM MODULE KMM372E160 KMM372E160(8)0BK/BS HIDDEN REFRESH CYCLE ( WRITE ) NOTE : DOUT = OPEN tRC RAS tRAS VIH - tRP tRAS VIL - tCRP CAS tRC tRP tRCD tRSH tCHR VIH VIL - tRAD tASR A VIH VIL - tRAH tASC ROW ADDRESS tCAH COLUMN ADDRESS tWRH tWRP tWCS W OE VIH VIL - VIH VIL - tDS DQ tWCH tWP VIH VIL - tDH DATA-IN Dont care Undefined DRAM MODULE KMM372E160 KMM372E160(8)0BK/BS CAS-BEFORE-RAS REFRESH COUNTER TEST CYCLE tRP RAS CAS VIH - tRAS VIL VIH - tCPT tCSR tRSH tCHR tCAS VIL - tRAL tASC A VIH - W OE COLUMN ADDRESS VIL - READ CYCLE tWRP tWRH tRRH tAA tRCS tRCH tCAC VIH VIL VIH VIL - tOEA tCLZ VOH - DQ tCAH tOEZ DATA-OUT VOL - WRITE CYCLE W tCEZ tREZ tWRP tRWL tWRH tCWL tWCS VIH - tWCH VIL - tWP OE VIH VIL - tDS DQ tDH VIH DATA-IN VIL - READ-MODIFY-WRITE tWRP W tWRH tAWD tRCS tCWL tCWD VIH - tRWL tWP tCAC VIL - tAA tOEA OE VIH - tOED VIL - tCLZ DQ tOEZ tDH tDS VI/OH VI/OL VALID DATA-OUT VALID DATA-IN NOTE : This timing diagram is applied to all devices besides 64M DRAM based modules. Dont care Undefined tWEZ DRAM MODULE KMM372E160 KMM372E160(8)0BK/BS CAS - BEFORE - RAS SELF REFRESH CYCLE NOTE : OE, A = Dont care tRP RAS VIL - tRPS tRPC tRPC tCP VIH - CAS tRASS VIH - tCHS tCSR VIL - tCEZ VOH - DQ OPEN VOL - VIH - W VIL - tWRP tWRH TEST MODE IN CYCLE NOTE : OE , A = Dont care tRC tRP RAS tRP tRAS VIH VIL - tRPC tRPC tCP CAS tCSR VIH - tWTS W tCHR VIL - tWTH VIH VIL - tCEZ DQ VOH VOL - OPEN Dont care Undefined DRAM MODULE KMM372E160 KMM372E160(8)0BK/BS PACKAGE DIMENSIONS Units : Inches (millimeters) 5.250 (133.350) 0.054 (1.372) 5.014 (127.350) 0.118 (3.000) R 0.079 (R 2.000) B 0.250 (6.350) 0.350 (8.890) C 0.250 (6.350) 1.450 (36.830) .450 (11.430) 0.100Min A .118DIA 118DIA±.004 (3.000DIA 000DIA±.100) 2.150 (54.61) (2.540Min) 0.700 (17.780) 0.118 (3.000) 1.250 (31.75) 0.157±0.004 (4.000±0.100) 4.550 (115.57) ( Front view ) 0.150Max (3.81Max) TSOPII 0.165 Min (4.19 Min) 0.350Max (8.89Max) SOJ 0.050±0.0039 (1.270±0.10) 0.100 Min 0.250 (6.350) 0.250 (6.350) 0.1230±.0050 (3.125±.125) 0.079±.0040 (2.000±.100) Detail A 0.1230±.0050 (3.125±.125) 0.079±.0040 (2.000±.100) Detail B Tolerances : ±.005(.13) unless otherwise specified The used device is 16Mx4 DRAM with EDO mode, SOJ or TSOPII. DRAM Part No. : KMM372E1600BK/BS KMM372E1600BK/BS - KM44C16104BK KM44C16104BK, KM44C16104BS KM44C16104BS. KMM372E1680BK/BS KMM372E1680BK/BS - KM44C16004BK KM44C16004BK, KM44C16004BS KM44C16004BS. (2.540 Min) ( Back view ) 0.039±.002 (1.000±.050) 0.01Max (0.25 Max) 0.050 (1.270) Detail C