KCD-A220-BA 656/BT LUT16 BT656 113K/152K/230K/308K - Datasheet Archive

 

for The CyberDisplay ® 113K LV, 152K LV, 230K LV or WQVGA LV Color Displays Part Number: KCD-A220-BA Ver. 0.1 August 10, 2006

 

A220 Display Driver for The CyberDisplay ® 113K LV, 152K LV, 230K LV or WQVGA LV Color Displays Part Number: KCD-A220-BA KCD-A220-BA Ver. 0.1 August 10, 2006 KOPIN A220 List of Figures Figure 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 Title Block Diagram -Edge Enhancement Filter Generation -Edge Enhancement Process -Piecewise-linear Gamma Correction with Lookup Table -Color Bar Chart -49 FBGA Pin Allocation ­ Bottom View -Video Input and DVALID/HS_IN/VS_IN Timing -3 Wire Interface Signals Timing -DIN and CLK_IN Timing (YCbCr Color Space) -Example Timing for HSdly and HSpos Registers Usage -Example Timing for YCbCr Video Input with Separate Syncs -(Using HSpos register to indicate the starting position of active video) Example Timing for YCbCr Video Input with Separate Syncs -(Using DVALID signal to indicate the starting position of active video) RGB(8,8,8) Color Space DataStream Timing -Example Timing for RGB(8,8,8) Video Input with Separate Syncs -(Using HSpos register to indicate the starting position of active video) Example Timing for RGB(8,8,8) Video Input with Separate Syncs -(Using DVALID signal to indicate the starting position of active video) RGB(8,8,8) Color Space DataStream Timing -Example Timing for RGB(5,6,5) Video Input with Separate Syncs -(Using HSpos register to indicate the starting position of active video) Example Timing for RGB(5,6,5) Video Input with Separate Syncs -(Using DVALID signal to indicate the starting position of active video) 3 Wire Serial Transfer Timing -Application Circuit -49 FBGA Package Information - Page 2 4 4 7 7 15 18 18 19 20 21 22 23 23 24 25 25 26 27 28 29 A220 List of Tables Table 1 2 3 4 5 6 7 8 9 10 Title Digital Video Input Formats -Configuration Register -Pin Description -Absolute Maximum Rating -Recommended Operating Condition -DC Characteristics -Display Charge Pump ­ QP -DAC -AC Timing -3 Wire Serial Data Format - Page 3 8 13 16 16 16 17 17 18 27 A220 General Description The A220 is a highly integrated driver IC that supports KOPIN's low voltage color displays. It is designed to accept BT.656, BT.601 or a similar digital video source, and generate analog RGB for the CyberDisplay® products. It includes three 8-bit DACs, video amplifiers and one charge pump for -5 V power supply voltage to the display. It supports a 3-wire serial interface. Features Driver for the CyberDisplay® 113K LV, 152K LV, 230K LV or WQVGA LV Supports NTSC and PAL systems Digital Video Input Formats · · · · BT.656/BT 656/BT.601 standard digital video Square-pixel variants of BT.656/ BT.601 Any of the above formats with separate HS and VS input instead of embedded sync (SAV/EAV) Formats using RGB(8,8,8) or RGB(5,6,5) color space instead of YCbCr Horizontal and Vertical Scaling Programmable Gamma Correction Programmable Video Enhancement on YCbCr o Contrast, Brightness and Sharpness Control on Y signal o Gain Control on Cb,Cr signal Programmable Gain and Offset Control on RGB signal Programmable Timing Control for CyberDisplay® products 3-Wire Serial Interface RGB 8-bit DACs and Video Amplifiers Charge Pump to provide -5 V Power to CyberDisplay products Independent Power Control for Display Interface Signals Power Saving Function 3.3 V Operating Voltage 49 FBGA -1- A220 Block Diagram Test Pattern Generator Video Enhancement 1 0 VS_IN YDIN CDIN Contrast (Y Gain) MUX HS_IN 8 8 Input Data Register Digital Video Interface Edge Enhence Cb Cb Gain SyncPol Programma ble Delay SepSync HsDly ColorSpace DIsplay Clock Generator Limit Limit Contrast Brightness GainCb GainCr YAPSC YAPTH YAPG ClipPlus ClipMinus Serial Interface Color Space Conversion (YCbCr2RGB) Horizontal Prescaling VSpos HSpos ColorSpace CSCC1 - CSCC5 NTSC_PAL VideoType PreScale Clk 8 Bit DAC Gamma Correction Green Gain/Offset Control Display Interface Video AMP ROUT 8 Bit DAC Video AMP GOUT 8 Bit DAC Red Gain/Offset Control Video AMP BOUT Configuration Registers LUT0 - LUT16 LUT16 DIS_CK0 DIS_CK1 DIS_HS DIS_VS DIS_INV DispType DirScan NTSC_PAL DisType Blue Gain/Offset Control GPR0 Horizontal Dot Scaling Vertical Scale Cr Y-low Y-high Cx-low Cx-high ClkInDly SCLK_3W SDAT_3W LD_3W Line Buffer Y Limit Cr Gain TestPattern DVALID CLK_IN Brightness (Y Offset) Gain R Gain G Gain B Offset R Offset G Offset B DispType L2RScan ClkOutDly DrvWhite DAC_PWD Timing Control QP_ENB Figure 1. Block Diagram -2- Charge Pump 1 (DISPLAY) QP_REF0 QP_CLKA QP_CKB QP_FB5 A220 Function Description Digital Video Interface The Digital Video Interface accepts an 8-bit/16-bit data bus and clock. Additional horizontal and vertical sync inputs are needed in some formats. It converts the 4:2:2 YCbCr format to 4:4:4 format. The supported input formats are: · · · · BT.656/BT 656/BT.601 standard digital video, both 525-line/60Hz and 625-line/50Hz (NTSC or PAL) Square-pixel variants of BT.656/BT 656/BT.601 for both NTSC and PAL Any of above with separate HS and VS inputs instead of embedded sync (SAV/EAV) Formats using RGB(8,8,8) or RGB(5,6,5) color spaces instead of YCbCr Table 1 summarizes the timing and resolution of these input formats. Table1. Digital Video Input Formats Format 16:9 Wide 16:9 Square Standard Square Pixel NTSC/ PAL Clock (MHz) Total Y Samples/Row Active Y Samples/Row NTSC PAL NTSC PAL NTSC PAL NTSC PAL 36.00/18.00 36.00/18.00 32.72/16.36 32.72/16.36 27.00/13.5 27.00/13.5 24.54/12.27 24.56/12.28 1144 1152 1020 1026 858 864 780 786 960 960 856 856 720 720 640 640 Active CbCr or RGB Samples/Row 360 360 320 320 360 360 320 320 Digital Video Enhancement The Digital Video Enhancement block enhances the YCbCr video source by Contrast, Brightness, Sharpness on the Y signal and Gain on the Cb, Cr signals. Enhanced data are limited to BT.656 data range as default (Y : 16 ~ 235, Cb & Cr : 16 ~ 240) Contrast control : 0X to 1.99X Brightness control : -128 to 127 Sharpness control block enhances the Figure's sharpness. The sharpness control block generates horizontal sharpness filter from Y video input. Sharpness filter can be noise sliced, gain controlled and clipped by configuration registers. Cb, Cr Gain : 0X to 1.99X Y_low, Y_high : Y signal low and high limits Cx_low, Cx_high : Cb, Cr signals low and high limits -3- A220 OUT YAPSC = "11" YAPSC = "10" YAPSC = "01" YAPSC = "00" IN - YAPTH + YAPTH * YAPSC: Sharpness Noise Slice Control YAPTH: Sharpness Noise Slice TH Value Figure 2. Edge Enhancement Filter Generation + YAPTH Sharpness Filter - YAPTH After Sharpness Noise Slice Control (Ex. YAPSC = "00") ClipPlus Gain on Sharpness Filter ClipMinus (Ex. YAPG = FFH) Clipped Sharpness Filter Sharpness Enhanced Yout (Sharpness Filter + Yin) Figure 3. Edge Enhancement Process -4- A220 Color Space Conversion Color Space conversion block converts color space from YCbCr to RGB and uses following equations. · · · R = CSCC1 * (Y ­ 16) + CSCC2 * (Cr ­ 128) G = CSCC1 * (Y ­ 16) ­ CSCC3 * (Cr ­ 128) ­ CSCC4 * (Cb ­ 128) B = CSCC1 * (Y ­ 16) + CSCC5 * (Cb ­ 128) The default values of the constants are: CSCC1 = 1.164 CSCC2 = 1.596 CSCC3 = 0.813 CSCC4 = 0.392 CSCC5 = 2.017 -5- A220 Horizontal Prescaling The horizontal prescaling stage makes 640 samples per line of video data, independent of the input format. All scaling is linear interpolated and standard BT.656/BT 656/BT.601 input can select either 11:10 scaling or 9:8 scaling by internal mode register. · · · Standard BT.656/BT 656/BT.601 (both NTSC and PAL): 11:10 scaling or 9:8 scaling. Square Pixel PAL: 6:5 scaling. Square Pixel NTSC: No prescaling. Vertical Scaling Only PAL input data will be vertically 6:5 scaled by linear interpolation. Horizontal Dot Scaling The second phase of horizontal scaling produces output samples matching the display's dot layout. Three fixed ratios are implemented as follows. · · · · CyberDisplay® 230K: 2:3 scaling. CyberDisplay® WQVGA: 2:3 scaling or 1:2 Scaling. CyberDisplay® 113K: 5:9 scaling. CyberDisplay® 152K: 5:9 scaling or 5:12 Scaling. For the CyberDisplay® 113K display, the 61 samples are discarded from 640 prescaled samples before 5:9 horizontal dot scaling. Gamma Correction Gamma correction is performed using piecewise-linear function defined by a 9-entry lookup table (Figure 2). Intermediate values are computed by interpolating between the two nearest LUT entries. In C notation: Gamma_x = LUT[x/16] + x%16*(LUT[x/16+1] ­ LUT[x/16]) / 16; The `/' denotes integer division truncating the remainder. Note that LUT[16] is 9 bit registers ­ combine LUT16m and LUT16 LUT16 registers ­ to support the full 0-255 range without missing codes. The 9 bit registers, LUT[16] can be set to "100H" as maximum value (256) and "1FFH" as minimum value (-1). It can not be set between "101H" to "1FEH." After the gamma correction process, the corrected R, G, B value can be shifted separately by Offset-R, G, B configuration register values. -6- A220 Lut[16] Lut[15] Negative slope Lut[14] Lut[13] Lut[12] Lut[11] Lut[10] Lut[9] Lut[8] Lut[7] Lut[6] Lut[5] Lut[4] Lut[3] Positive slope Lut[2] Lut[1] Lut[0] 0 16 32 64 80 96 112 128 134 134 160 176 192 208 224 240 256 Figure 4. Piecewise-linear Gamma Correction with Lookup Table Test Video Pattern Generator When "TestPatt" register is set to `1', it generates the following color bar chart for display test. Figure 5. Color Bar Chart Serial Interface It supports 3-wire serial interfaces. -7- A220 Configuration Register Description Table 2. Configuration Register Address bit Default Name Description "00" ­ All embedded Sync. "10" ­ Separate V-Sync. "01" ­ Separate H-Sync. "11" ­ All Separate Sync. 7:6 00 SepSync 5:4 00 ColorSpace 3 0 Vid16 16 bit Video Input Select ( "1" ­ 16 bit Video Input) "0X" ­ YCbCr "10" ­ RGB(8,8,8) "11" ­ RGB(5,6,5) 00H 2:1 00 VideoType "00" ­ 13.5MHz Sampling Video (4:3/16:9) "01" ­ 12.27MHz Sampling Video (4:3/16:9, Square) "10" ­ 18MHz Sampling Video (16:9) "11" ­ 16.36MHz Sampling Video (16:9, Square) 0 0 NTSC/PAL "0" ­ NTSC "1" ­ PAL 01H 2 1 0 0 0 0 VSyncPol HSyncPol DvalidPol External Sync. Polarity "0" ­ Active High "1' ­ Active Low 02H 3:0 0H ClkInDly Video clk delay 03H 1:0 01 HSdly HS Input delay adjustment (Separate H-Sync. Mode) 04H 0 0 TestPatt "0" ­ External Video Input Select "1" ­ Internal Video Pattern Gen. Select (Color Bar) 05H 0 0 PreScale Std. NTSC/PAL Video Pre-scaling select "0" ­ 11:10 Scaling "1" ­ 9:8 Scaling 06H 7:0 1EH HSpos Horizontal position (Number of blinking Pixels) (Value range from 0 to 254) 07H 7:0 0DH VSpos0 Vertical position ­ Number of "Field 0" blinking lines (Value range from 0 to 254) 08H 7:0 0DH VSpos1 Vertical position ­ Number of "Field 1" blinking lines (Value range from 0 to 254) 5 0 Disp43 4 1 BlueScr 3 0 T2Bscan 2 0 L2Rscan 10H "0" ­ 152K, WQVGA Display Select "1' ­ 113K, 230K Display Select "0" ­ Normal Video Screen "1" ­ Blue Screen "0" ­ Top to Bottom Scan "1" ­ Bottom to Top Scan "0" ­ Left to Right Scan "1" ­ Right to Left Scan "00" ­ 2:3 scaling for CyberDisplay® 230K, WQVGA 1:0 11 "01" ­ 1:2 scaling for CyberDisplay ®230K, WQVGA DispType "10" ­ 5:9 scaling for CyberDisplay ®113K, 152K "11" ­ 5:12 scaling for CyberDisplay® 113K, 152K -8- A220 Table 2. Configuration Register (Continued) Address bit Default Name 11H 1:0 1 0 10 0 0 DACCC DIG_DWN SYS_DWN DAC Current Control Digital Power Down (except I2C block) All System Power Down (include I2C, Dac, Q-Pump) 6 5 0 0 DAC_TST DAC_PWN DAC Test Mode DAC Power Down 4 0 QP_PWN Q-Pump Power Down 1 1 Reserved Do Not Use 0 0 QP_ENB Q-Pump Enable (Active Low) "0": Enable, "1": Power Down 14H 7:0 80H Contrast Y Contrast value (0X ~ 1.99X) 00H . 7FH 80H 0X . 0.99X 1X 15H 7:0 00H Brightness 16H 1:0 00 YAPSC Sharpness Noise Slice Control "00" ­ x 0 , "01" ­ x ¼ "10" ­ x ½ , "11" ­ x 1 17H 7:0 FFH YAPTH Sharpness Noise Slice TH Value 18H 7:0 80H YAPG Sharpness Filter Gain (0X ~ 1.99X) 00H . 7FH 80H 81H 0X . 0.99X 1X 1.01X 19H 7:0 00H ClipPlus 1AH 7:0 00H ClipMinus 1BH 7:0 80H GainCb Cb Gain (0X ~ 1.99X) 00H . 7FH 0X . 0.99X 80H 1X 81H 1.01X . . FFH 1.99X 1CH 7:0 80H GainCr Cr Gain 0X ~ 1.99X) 00H . 7FH 0X . 0.99X 80H 1X 81H 1.01X . . FFH 1.99X 1DH 7:0 80H Reserved Do Not Use 1 1 Reserved 0 1 GPR0 General Purpose Registers (data out to PAD directly) General Purpose Register can be used as T2Bscan, L2Rscan or sleep control outputs. 12H 13H 1FH Description 81H 1.01X Y Brightness value (-128 ~ 127) 80H . FFH 00H 01H -128 . -1 0 1 . . FFH 1.99X . . 7FH 127 . . FFH 1.99X Sharpness Filter Plus Level Clip : 00H(0) ~ FFH(255) Sharpness Filter Minus Level Clip : 00H(0) ~ FFH(255) -9- A220 Table 2. Configuration Register (Continued) Address Default Name 4 20H bit 0 GainSel 3 0 VegSel Description R, ,G, B Gain range select "0" ­ 0X ~ 1.99X range select "1" ­ 0X ~ 3.99X range select V-sync. Active Edge Select "0" ­ Falling edge select when Active High V-sync. Polarity Mode "1" ­ Rising edge select when Active High V-sync. Polarity Mode Drive-to-White Select 2 0 DrvWhite 1:0 01 DacDly Dac Delay (No of Dac clocks) 22H 7:0 10H Y_low Y Signal Low Limit 23H 7:0 EBH Y_high Y Signal High Limit 24H 7:0 10H Cx_low Cb, Cr Signal Low Limit 25H 7:0 F0H Cx_high Cb, Cr Signal High Limit Color Space Conversion Coefficient 1 ­ 1.164 (1.164*256=297.984 -> 12AH) Color Space Conversion Coefficient 2 ­ 1.596 (1.596*256=408.576 -> 198H) Color Space Conversion Coefficient 3 ­ 0.813 (0.813*256=208.128 -> 0D0H) Color Space Conversion Coefficient 4 ­ 0.392 (0.392*256=100.352 -> 064H) Color Space Conversion Coefficient 5 ­ 2.017 (2.017*256=516.352 -> 204H) 27,26H 9:0 12AH CSCC1 29,28H 9:0 198H CSCC2 2B,2AH 9:0 0D0H CSCC3 2D,2CH 9:0 064H CSCC4 2F,2EH 9:0 204H CSCC5 3AH 7:0 00H Offset-R R Offset (-128 ~ 127) 3BH 7:0 00H Offset-G G Offset (-128 ~ 127) 3CH 7:0 00H Offset-B B Offset (-128 ~ 127) 3DH 7:0 80H Gain-R R Gain (0X ~ 1.99X) 3EH 7:0 80H Gain-G G Gain (0X ~ 1.99X) 3FH 7:0 80H Gain-B B Gain (0X ~ 1.99X) 40H 3:0 2H dclkSkip 41H 7:0 1DH WHS DIS_HS Width* 42H 7:0 25H WSP CK0 Start Position* 45,44H 9:0 0EFH DispPixel Number of Display Pixel ­ 1* 47,46H 9:0 005H VidStartP Display Data Start Point (CKx number)* 49,48H 9:0 0EEH VidEndP Display Data End Point (CKx number)* Display Clock Skip Mode* * See attached setting table - 10 - A220 Table 2. Configuration Register (Continued) Address bit Default Name Description 50H 7:0 00H LUT_00 Gamma collection Look-Up Table 0 51H 7:0 13H LUT_01 Gamma collection Look-Up Table 1 52H 7:0 26H LUT_02 Gamma collection Look-Up Table 2 53H 7:0 37H LUT_03 Gamma collection Look-Up Table 3 54H 7:0 49H LUT_04 Gamma collection Look-Up Table 4 55H 7:0 58H LUT_05 Gamma collection Look-Up Table 5 56H 7:0 67H LUT_06 Gamma collection Look-Up Table 6 57H 7:0 73H LUT_07 Gamma collection Look-Up Table 7 58H 7:0 80H LUT_08 Gamma collection Look-Up Table 8 59H 7:0 8CH LUT_09 Gamma collection Look-Up Table 9 5AH 7:0 98H LUT_10 Gamma collection Look-Up Table 10 5BH 7:0 A7H LUT_11 Gamma collection Look-Up Table 11 5CH 7:0 B6H LUT_12 Gamma collection Look-Up Table 12 5DH 7:0 C8H LUT_13 Gamma collection Look-Up Table 13 5EH 7:0 DAH LUT_14 Gamma collection Look-Up Table 14 5FH 7:0 ECH LUT_15 Gamma collection Look-Up Table 15 60H 7:0 FFH LUT_16 Gamma collection Look-Up Table 16 61H 0 0 LUT_16m Gamma collection Look-Up Table 16 MSB - 11 - A220 Table 2. Configuration Register (Continued) *Display Setting Table Sampling Rate LCD 113K 152K 13.5MHz 230K Screen Ratio VidOutMod dclkSkip (10H) (40H) wHS (41H) wSP (42H) DispPixel (45,44H) VidStartP (47,46H) VidEndP (49,48H) 4:3 22 1 14 1A 0B5 005 0B4 16:9 03 2 1D 25 0EF 005 0EE 4:3 02 2 1D 25 0EF 022 0D1 4:3 20 9 27 30 147 005 145 113K 152K 12.27MHz 230K WQVGA 16:9 01 B 3B 47 1B7 007 1B3 4:3 WQVGA 00 B 3B 47 1B7 03D 17D 4:3 22 2 2E 3D 0B5 005 0B4 16:9 03 3 1E 29 0EF 005 0EE 0D1 4:3 02 3 1E 29 0EF 022 4:3 20 0 23 30 147 005 145 16:9 01 0 33 43 1B7 007 1B3 4:3 18MHz 16.36MHz 00 0 33 43 1B7 03D 17D 16:9 03 1 1D 25 0EF 005 0EE WQVGA 16:9 01 B 3B 47 1B7 007 1B3 152K 16:9 03 2 42 56 0EF 005 0EE WQVGA 16:9 01 0 33 43 1B7 007 1B3 152K - 12 - A220 Pin Description Table 3. Pin Description Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Ball No. C3 C2 B1 D2 C1 D3 D1 E1 F1 E3 G2 G3 G4 G5 E2 F2 G1 F3 F4 E4 F5 F6 G6 G7 E5 E6 F7 D6 Pin Name I/O SCLK_3W SDAT_3W LD_3W ResetB VSS VDD CDIN0 CDIN1 CDIN2 CDIN3 CDIN4 CDIN5 CDIN6 CDIN7 YDIN0 YDIN1 YDIN2 YDIN3 YDIN4 YDIN5 YDIN6 YDIN7 DVALID VDD_IO CLK_IN VSS HS_IN VS_IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN Signal Type Digital Digital Digital Digital GND Power Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Power Digital GND Digital Digital 29 E7 QP_CLKB OUT Analog 30 D5 QP_CLKA OUT Analog 31 D7 QP_FB5 IN Analog 32 C6 QP_REF0 OUT 33 34 C7 B6 VSSA_QP VDDA_QP - Description Serial Clock Input for 3 Wire Interface Serial Data Input for 3 Wire Interface Data Load Input for 3 Wire Interface System Reset in Low Active Digital GND Digital Power for CORE Chrominance Data Bit0 Chrominance Data Bit1 Chrominance Data Bit2 Chrominance Data Bit3 Chrominance Data Bit4 Chrominance Data Bit5 Chrominance Data Bit6 Chrominance Data Bit7 Luminance Data Bit0 / Digital Video Bit0 in BT656 BT656 Luminance Data Bit1 / Digital Video Bit1 in BT656 BT656 Luminance Data Bit2 / Digital Video Bit2 in BT656 BT656 Luminance Data Bit3 / Digital Video Bit3 in BT656 BT656 Luminance Data Bit4 / Digital Video Bit4 in BT656 BT656 Luminance Data Bit5 / Digital Video Bit5 in BT656 BT656 Luminance Data Bit6 / Digital Video Bit6 in BT656 BT656 Luminance Data Bit7 / Digital Video Bit7 in BT656 BT656 Data Valid Input in RGB Format Digital Power for IO Pixel Clock Input Digital GND Horizontal Sync Input Vertical Sync Input Display Charge Pump Control Pulse Output (when QP not used, it should be Opened) Display Charge Pump Control Pulse Output (when QP not used, it should be Opened) Display Charge Pump Voltage Feedback (when QP not used, it should be tied to VSSA_QP) Backlight Charge Pump Reference Voltage Buffer Analog Output (when QP not used, it should be Opened) GND Power Analog GND Analog Power For Display Charge Pump(QP) - 13 - A220 Table 3. Pin Description (Continued) Pin No. 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 Ball Pin Name No. B7 VSSA_DAC A7 VRB C5 VDDA_DAC B5 VRT A6 ROUT B4 GOUT A5 BOUT C4 VDD_DIS A4 DIS_CK0 B3 DIS_CK1 A3 DIS_HS B2 DIS_VS A2 DIS_INV A1 GPR0 D4 TESTMODE I/O IN IN OUT OUT OUT OUT OUT OUT OUT OUT OUT IN Signal Type GND Analog Power Analog Analog Analog Analog Power Digital Digital Digital Digital Digital Digital Digital Description Analog GND Bottom Reference Voltage for DAC 5V Analog Power for DAC Top Reference Voltage for DAC and Video Amp RED Signal Output GREEN Signal Output Blue Signal Output Power for Display Interface IO Pixel Clock Output to Display Pixel Clock Output to Display Horizontal Sync Output to Display Vertical Sync Output to Display White Level Adjustment General Purpose Register0 Output TEST Mode Select - 14 - A220 Pin Allocation 7 6 5 4 3 2 1 A VRB ROUT BOUT DIS_CK0 DIS_HS DIS_INV GPR0 A B VSSA_DAC VDDA_QP VRT GOUT DIS_CK1 DIS_VS LD_3W B C VSSA_QP QP_REF0 VDDA_DAC VDD_DIS SCLK_3W SDAT_3W VSS C D QP_FB5 VS_IN QP_CLKA TESTMODE VDD ResetB CDIN0 D E QP_CLKB VSS CLK_IN YDIN5 CDIN3 YDIN0 CDIN1 E F HS_IN YDIN7 YDIN6 YDIN4 YDIN3 YDIN1 CDIN2 F G VDD_IO DVALID CDIN7 CDIN6 CDIN5 CDIN4 YDIN2 G 7 6 5 4 3 2 1 Figure 6. 49 FBGA Pin Allocation ­ Bottom View - 15 - A220 Absolute Maximum Ratings (Table 4) SYMBOL VDD, VDD_IO,VDDA_QP VDDA_DAC, VDD_DIS VIND VINA Tstorage DESCRIPTION Supply Voltage Supply Voltage Digital Input Pin Voltage Analog Input Pin Voltage Storage Temperature MIN -0.5 -0.5 VSSD-0.3 VSSA-0.3 -40 MAX 4.0 6.0 VDD+0.3 VDDA+0.3 125 UNIT V V V V °C Recommended Operating Conditions (Table 5) PARAMETER Power Supply Voltage Power Supply Voltage Power Supply Voltage Logic input level Operating temperature range CONDITIONS VDD, VDD_IO,VDDA_QP VDD_DIS VDDA_DAC MIN 3.0 3.0 4.5 0 -20 TYP 3.3 3.3 5.0 - MAX 3.6 3.6 5.5 VDD 70 UNIT V V V V °C Electrical Characteristics (All parameters are specified at Ta=25°C, All Power =3.3V, unless otherwise noted.) DC Characteristics (Table 6) PARAMETER Supply current 1 (IDD1) (VDD, VDD_IO,VDDA_QP, VDD_DIS) Supply Current 2 (IDD2) (VDDA_DAC) Total Power Dissipation Power Down current Total Power Dissipation Total Power Dissipation (Power Down) Input Capacitance CONDITIONS TYP MAX UNIT VDD,VDD_IO,VDDA_QP, VDD_DIS = 3.3V 30 37 VDDA_DAC = 5.0V 18 21 SYS_PWN = High - 16 - MIN 150 5 150 16 8.67 20 mW mW mW pF A220 Display Charge Pump - QP (Table 7) Parameter Input voltage Output voltage Output current Ripple voltage Quiescent current Shutdown Current Line regulation Load regulation Conditions MIN TYP IOUT5mA, 2.5VVIN3.6V 3.0 -4.8 -5 1 60 70 IOUT=1mA IOUT=0mA, VIN=2.5V to 3.6V SYS_PWN=H and/or QP1_ENB=H 2.5VVIN3.6V 0mAILOAD1mA 40 40 MAX UNIT 3.6 -5.2 5 120 1 50 50 V V mA mV µA µA mV mV DAC (Table 8) Parameter Conditions MIN TYP Resolution Differential Linearity Error Integral Linearity Error Offset Error (1) Gain Error (2) Maximum Output Voltage 0V to (VRT-VRB)*255/256 LSB Size Channel Variation among ROUT, GOUT, BOUT MAX UNIT ±0.5 ±1 VRT=3.3V, VRB=0V D[7:0]=all low VRT=3.3V, VRB=0V D[7:0]=all high VRT=3.3V, VRB=0V D[7:0]=all high VLSB=VOUT(MAX)/255 Bits LSB LSB 5 15 mV 2 3.2 8 ±1 ±2 % 3.3 V 3.287 12.77 0.2 Note: (1) Offset Error = VOUT(D[7:0]=Low) ­VRB (2) Gain Error = VOUT(D[7:0]=high) ­{(VRT-VRB) x 255/256 + VRB} - 17 - mV 0.5 % A220 AC Timing (Table 9) Parameter Symbol Video Data Control Signals tS (HS_IN,DVALID,VS_IN) stup & tH hold tDS SDAT_3W setup & hold tDH MIN TYP ns 150 ns 150 tHW 210 tLW 210 150 150 tCLK Clock Period Clock Duty 24.54 40 ns ns 29.5 60 t CLK CLK_IN YDIN[7:0] CDIN[7:0] tS tH tH DVALID tH tH HS_IN VS_IN tH Figure 7. Video Input and DVALID/HS_IN Timing SDAT_3W D14 D13 UNIT 10 tLH setup & hold MAX 0 tLS SCLK_3W high & low width LD_3W Conditions D12 D4 D3 D2 D1 D0 t DS t DH SCLK_3W t HW t LW t LH LD_3W t LS - 18 - MHz % A220 Figure 8. 3 Wire Interface Signals Timing - 19 - A220 Application Information YCbCr DataStream Using Embedded Sync When embedded sync is used, it just needs the data and a clock with AC timing. The AC timing of the data and clock is in Figure 7, and HS_IN and DVALID signals should be tied to low. If there are difficulties satisfying the AC timing, it can be adjusted using the "ClkInDly" register. Basically, it delays the CLK_IN signal internally. There are 16 different delay steps. DIN[7:0] Cb0 Y0 Cr0 Y1 Cb1 Y2 Cr1 Y3 Cb2 Y4 CLK_IN Figure 9. DIN and CLK_IN Timing (YCbCr Color Space) Using Separate Sync One of the control signals (HS_IN or DVALID) has to be provided. The control signals have lots of flexibility in positioning relative to data input since there is a "HSdly" register to adjust the start of a valid position of input data, and the "HSpos" register to control the horizontal position of the images. It also has flexibility in the polarity, active high or active low. The "VSyncPol", "HSyncPol" and "DvalidPol" registers can be used to accept input polarity of control signals. When the DVALID signal is used, the HS_IN signal is not important as long as it has an active period within the DVALID low period, or it should be tied to low. The default polarity of the DVALID signal is active high. The falling edge of the DVALID signal is not important as long as it is kept high during the actual valid data period. It can be extended up to the blanking period. When the HS_IN signal is used, the DVALID signal has to be tied to high. The default polarity of HS_IN is active high. The rising edge of the HS_IN signal is not important. When using external sync., it is recommended to use one of the signals of HS_IN or DVALID, not both of them. Both of them can be used as long as the HS_IN period (high) is within the low period of the DVALID signal. - 20 - A220 Min. 10 clock cycle HS_IN or DVALID HSdly = "01" (default) Cb0 Y1 Cb1 Y2 Cr1 Y3 Cb2 Y4 Cr2 Y5 Cb3 Y6 Y0 Cr0 Y1 Cb1 Y2 Cr1 Y3 Cb2 Y4 Cr2 Y5 Cb3 Y6 Cr2 Y0 Cr0 Y1 Cb1 Y2 Cr1 Y3 Cb2 Y4 Cr2 Y5 Cb3 Cb0 Cb0 Cr0 Cb0 HSdly = "00" Y0 Y0 Cr0 Y1 Cb1 Y2 Cr1 Y3 Cb2 Y4 Cr2 Y5 DIN[7:0] HSdly = "10" HSdly = "11" HSpos = 00H (default) Internal R,G,B[7:0] (After Color Space Conversion) Pixel 0 Pixel 3 Pixel n Pixel n+1 Pixel 1 Pixel 2 Pixel n-1 Pixel n Pixel 0 Pixel 1 Pixel n-2 Pixel n-1 Pixel 0 HSpos = 02H Pixel 2 Pixel 0 HSpos = 01H Pixel 1 Pixel 1 HSpos = n Figure 10. Example Timing for HSdly and HSpos Registers Usage - 21 - A220 NTSC timing PAL timing D[7:0] 0 0 80 1 1 10 . . . 124 124 80 125 125 10 126 126 80 127 127 10 . . . 242 262 80 243 263 244 264 245 265 246 266 247 267 248 268 249 269 10 Cb 0 Y 0 Cr 0 Y 1 Cb 1 Y 2 . . 1678 1679 1680 1681 1682 1683 1684 1685 1698 1699 1700 1701 1702 1703 1704 1705 . . . Cr 358 . Y 717 Cb 359 Y 718 Cr 359 Y 719 80 10 1712 1713 1714 1715 1724 1725 1726 1727 80 10 80 HS_IN DVALID (not used, "1") HSpos X 2 720 X 2 Blanking Pixels Active Pixels Blanking Pixels VS_IN (NTSC) 1-3 4 | 6 7 - 265 266 | 269 270 - 525 VS_IN (PAL) 1 | 3 4 - 312 313 | 315 316 - 625 Figure 11. Example Timing for YCbCr Video Input with Separate Syncs (Using HSpos register to indicate the starting position of active video) - 22 - 10 A220 NTSC timing PAL timing D[7:0] 0 1 . 124 125 126 127 . 242 243 244 245 246 247 248 249 . 1678 1679 1680 1681 1682 1683 1684 1685 . 1712 1713 1714 1715 0 1 . 124 125 126 127 . 262 263 264 265 266 267 268 269 . 1698 1699 1700 1701 1702 1703 1704 1705 . 1724 1725 1726 1727 10 Cb 0 Y 0 Cr 0 Y 1 Cb 1 Y 2 . Cr 358 . 80 10 . 80 10 80 10 . 80 Y 717 Cb 359 Y 718 Cr 359 Y 719 80 10 80 10 80 HS_IN DVALID Blanking Pixels Active Pixels Blanking Pixels VS_IN (NTSC) 1-3 4 | 6 7 - 265 266 | 269 270 - 525 VS_IN (PAL) 1 | 3 4 - 312 313 | 315 316 - 625 Figure 12. Example Timing for YCbCr Video Input with Separate Syncs (Using DVALID signal to indicate the starting position of active video) - 23 - 10 A220 RGB(8,8,8) DataStream R0 DIN[7:0] G0 B0 X R1 G1 B1 X R2 G2 CLK_IN Figure 13. RGB(8,8,8) Color Space DataStream Timing NTSC timing PAL timing D[7:0] 0 1 . 124 125 126 127 . 242 243 244 245 246 247 248 249 . 1678 1679 1680 1681 1682 1683 1684 1685 . 1712 1713 1714 1715 0 1 . 124 125 126 127 . 262 263 264 265 266 267 268 269 . 1698 1699 1700 1701 1702 1703 1704 1705 . 1724 1725 1726 1727 10 R 0 G 0 B 0 X R 1 G 1 . B 358 . 80 10 . 80 10 80 10 . 80 X R 359 G 359 B 359 X 80 10 80 10 80 10 HS_IN VALID (not used, "1") HSpos X 2 720 X 2 Blanking Pixels Active Pixels Blanking Pixels VS_IN (NTSC) 1-3 4 | 6 7 - 265 266 | 269 270 - 525 VS_IN (PAL) 1 | 3 4 - 312 313 | 315 316 - 625 Figure 14. Example Timing for RGB(8,8,8) Video Input with Separate Syncs (Using HSpos register to indicate the starting position of active video) - 24 - A220 NTSC timing PAL timing D[7:0] 0 1 . 124 125 126 127 . 242 243 244 245 246 247 248 249 . 1678 1679 1680 1681 1682 1683 1684 1685 . 1712 1713 1714 1715 0 1 . 124 125 126 127 . 262 263 264 265 266 267 268 269 . 1698 1699 1700 1701 1702 1703 1704 1705 . 1724 1725 1726 1727 10 R 0 G 0 B 0 X R 1 G 1 . B 358 . 80 10 . 80 10 80 10 . 80 X R 359 G 359 B 359 X 80 10 80 10 80 HS_IN VALID Blanking Pixels Active Pixels Blanking Pixels VS_IN (NTSC) 1-3 4 | 6 7 - 265 266 | 269 270 - 525 VS_IN (PAL) 1 | 3 4 - 312 313 | 315 316 - 625 Figure 15. Example Timing for RGB(8,8,8) Video Input with Separate Syncs (Using DVALID signal to indicate the starting position of active video) - 25 - 10 A220 RGB(5,6,5) DataStream R0[7:3] G0[7:5] DIN[7:0] G0[4:2] B0[7:3] R1[7:3] G1[7:5] G1[4:2] B1[7:3] R2[7:3] G2[7:5] CLK_IN Figure 16. RGB(5,6,5) Color Space DataStream Timing NTSC timing PAL timing D[7:0] 0 1 . 124 125 126 127 . 242 243 244 245 246 247 248 249 . 1678 1679 1680 1681 1682 1683 1684 1685 . 1712 1713 1714 1715 0 1 . 124 125 126 127 . 262 263 264 265 266 267 268 269 . 1698 1699 1700 1701 1702 1703 1704 1705 . 1724 1725 1726 1727 80 10 . 80 10 80 10 . 80 10 R0(7:3) G0(7:5) G0(4:2) B0(7:3) R1(7:3) G1(7:5) . G358(4:2) B358(7:3) R359(7:3) G359(7:5) G359(4:2) B359(7:3) 80 10 . 80 10 80 HS_IN VALID (not used, "1") HSpos X 2 720 X 2 Blanking Pixels Active Pixels Blanking Pixels VS_IN (NTSC) 1-3 4 | 6 7 - 265 266 | 269 270 - 525 VS_IN (PAL) 1 | 3 4 - 312 313 | 315 316 - 625 Figure 17. Example Timing for RGB(5,6,5) Video Input with Separate Syncs (Using HSpos register to indicate the starting position of active video) - 26 - 10 A220 NTSC timing PAL timing D[7:0] 0 1 . 124 125 126 127 . 242 243 244 245 246 247 248 249 . 1678 1679 1680 1681 1682 1683 1684 1685 . 1712 1713 1714 1715 0 1 . 124 125 126 127 . 262 263 264 265 266 267 268 269 . 1698 1699 1700 1701 1702 1703 1704 1705 . 1724 1725 1726 1727 80 10 . 80 10 80 10 . 80 10 R0(7:3) G0(7:5) G0(4:2) B0(7:3) R1(7:3) G1(7:5) . G358(4:2) B358(7:3) R359(7:3) G359(7:5) G359(4:2) B359(7:3) 80 10 . 80 10 80 HS_IN VALID Blanking Pixels Active Pixels Blanking Pixels VS_IN (NTSC) 1-3 4 | 6 7 - 265 266 | 269 270 - 525 VS_IN (PAL) 1 | 3 4 - 312 313 | 315 316 - 625 Figure 18. Example Timing for RGB(5,6,5) Video Input with Separate Syncs (Using DVALID signal to indicate the starting position of active video) - 27 - 10 A220 3-Wire Serial Interface It consists of 6 bits address and 8 bits data. When the address and data are provided with the clock during LD_3W signal is low, it stores address and data to the internal shift registers and address decoding is performed. Next, the actual writing operation to the specified register occurs at the rising edge of the LD_3W signal. Table 10. 3 Wire Serial Data Format A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 Address SDAT_3W A6 A5 D3 D2 D1 D0 Data A4 A3 A2 A1 A0 D7 D6 D5 D4 SCLK_3W LD_3W Figure 19. 3 Wire Serial Transfer Timing - 28 - D3 D2 D1 D0 A220 Example of Application D4 SCLK_3W A1 A2 B2 A3 B3 A4 C4 A5 B4 A6 VSSA *(2) C2 B7 B6 VDDA_QP C1 VDDIO D3 CDIN0 D1 CDIN1 VDD QP_REFO R1 (27K) QP_FB5V R2 (180K) 4.7uF 10pF QP_CKA D5 4.7uF QP_CKB E1 E7 F1 D6 E3 F7 G2 E6 G3 E5 4.7uF CDIN3 CDIN4 CDIN5 VS_IN VSS G7 VDD_IO G6 DVALID F6 YDIN7 F5 YDIN6 E4 YDIN5 F4 YDIN4 F3 YDIN3 G1 YDIN2 F2 YDIN1 E2 YDIN0 CDIN7 CDIN6 G5 VDDD SepSync VideoClock Note: *(1) QP_VOUT = 0.4 - 0.8 * (R2/R1) : When QP is not used, disable QP using QP_ENB register (Configuration register 13H) *(2) VRT can be tied to the CyberDisplay power (VDD) and VRB tied to VSS. Figure 20. Application Circuit - 29 - *(1) QP1_VOUT HS_IN CLK_IN G4 VideoIn VDDD D7 CDIN2 VSSD VSSA C6 10K 1uF VSSA VSSA_QP VSS VDDD VDDA_QP C7 VDDD VDD 2.2uF VSSA_DAC VSSA B1 ResetB VSSD 5K A7 D2 System Controller VSSA VRB C3 VDDA _DAC LD_3W 5K 2.2uF C5 B5 VDD_DIS SDAT_3W VDDA_DAC VDDA_DAC *(2) VRT ROUT GOUT BOUT VDD_DIS DIS_CK0 DIS_CK1 DIS_HS DIS_VS DIS_INV VSSD TM 113K/152K/230K/308K 113K/152K/230K/308K CyberDisplay GPR0 TESTMODE Recommended Power Supply for better contrast in the Display VDDD = VDD = VDD_IO = VDDA_QP = 3.0V - 3.3V VDD_DIS = 3.3V VDDA_DAC = 5.0V VSSD A220 Figure 21. 49 FBGA Package Information - 30 -