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KBA0101A0M KBA0201A0M KBA0301A0M KBA0401A0M KBA0101A0M/KBA0201A0M KBA0201A0 - Datasheet Archive
KBA0301A0M / KBA0401A0M Preliminary MCP MEMORY Document Title Multi-Chip Package MEMORY 64M Bit (4Mx16) Four Bank NOR Flash
KBA0101A0M KBA0101A0M / KBA0201A0M KBA0201A0M KBA0301A0M KBA0301A0M / KBA0401A0M KBA0401A0M Preliminary MCP MEMORY Document Title Multi-Chip Package MEMORY 64M Bit (4Mx16) Four Bank NOR Flash Memory *2 / 32M Bit (2Mx16) UtRAM / 8M Bit (512Kx16) SRAM Revision History Revision No. History Draft Date Remark 0.0 Initial Draft January 8, 2002 Preliminary 0.1 Revise - Added NOR Flash Boot Block Architecture 03: Flash 1 - Bottom Boot Block Flash 2 - Top Boot Block 04: Flash 1 - Top Boot Block Flash 2 - Bottom Boot Block February 15, 2002 Preliminary The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications and products. SAMSUNG Electronics will answer to your questions about device. If you have any questions, please contact the SAMSUNG branch offices. -1- Revision 0.1 February 2002 KBA0101A0M KBA0101A0M / KBA0201A0M KBA0201A0M KBA0301A0M KBA0301A0M / KBA0401A0M KBA0401A0M Preliminary MCP MEMORY Multi-Chip Package MEMORY 64M Bit (4Mx16) Four Bank NOR Flash Memory *2 / 32M Bit (2Mx16) UtRAM / 8M Bit (512Kx16) SRAM FEATURES · Power Supply voltage - Flash : 2.7V to 3.3V - UtRAM, SRAM : 2.7V to 3.1V · Organization - Flash : 4,194,304 x 16 bit *2 - UtRAM : 2,097,152 x 16 bit - SRAM : 524,288 x 16 bit · Access Time (@2.7V) - Flash : 85 ns, UtRAM : 85 ns, SRAM : 55ns · Power Consumption (typical value) - Flash Read Current : 20 mA (@5MHz) Sequential Page Read Current : 5 mA (@5MHz) Program/Erase Current : 35 mA (Max.) Standby mode/Deep Power mode : 0.1 µA - UtRAM Operating Current : 30 mA Standby Current : 80 µA Deep Power Down : 5 µA - SRAM Standby Current : 0.5 µA · SRAM Data Retention : 1.5 V (min.) · Secode(Security Code) Block : Extra 32KW Block (Flash) · Block Group Protection / Unprotection (Flash) · 128 words Page Program (Flash) · Flash Bank Size : 4Mb / 4Mb / 28Mb / 28Mb · Flash Endurance : 100,000 Program/Erase Cycles · Ambient Temperature : -25°C ~ 85°C · Endurance : 100,000 Program/Erase Cycles · Package : 80-ball TBGA Type - 11.0 x 10.0 mm, 0.8 mm pitch GENERAL DESCRIPTION The KBA0101A0M/KBA0201A0M KBA0101A0M/KBA0201A0M featuring single 3.0V power supply is a Multi Chip Package Memory which combines two 64Mbit Four Bank Flash and 32Mbit UtRAM and 8Mbit SRAM. The 64Mbit Flash memory is organized as 4M x16 bit and 32Mbit UtRAM is organized as 2M x16 bit and 8Mbit SRAM is organized as 512K x 16 bit. The 64Mbit Flash memory is the high performance non-volatile memory fabricated by CMOS technology for peripheral circuit and DINOR IV(Diveded bit-line NOR IV) architecture for the memory cell. All memory blocks are locked and can be programmed or erased, when F-WP is low. Using Software Lock Release function, program erase operation can be executed. The 32Mbit UtRAM is fabricated by SAMSUNG' advanced s CMOS technology using one transistor memory cell. The device also supports deep power down mode for low standby current. The 8Mbit SRAM is fabricated by SAMSUNGs advanced full CMOS process technology. The device also supports low data retention voltage for battery back-up operation with low data retention current. The KBA0101A0M/KBA0201A0M KBA0101A0M/KBA0201A0M is suitable for use in program and data memory of mobile communication system to reduce mount area. This device is available in 80-ball TBGA Type package. BALL DESCRIPTION BALL CONFIGURATION 1 2 3 4 5 6 7 8 9 10 11 12 DNU DNU A6 F-RY/BY UB S NC V CCS F-RP NC A12 DNU DNU B A5 A18 A21 NC VCCU WE A9 A13 C A4 A17 LBS NC V SS A20 A10 A14 D A3 NC A7 LB U UBU A19 A11 A15 E A1 A2 NC F-WP ZZ CS2S A8 NC F A0 CS1 S CSU NC NC F-CE2 F-CE1 G OE DQ2 DQ11 V CCQU V SS DQ12 DQ5 DQ14 H DQ8 DQ9 DQ3 NC VCCU NC DQ13 DQ7 DQ0 DQ1 DQ10 F-V CC V CCS DQ4 DQ6 DQ15 DNU DNU A J DNU DNU A16 80 Ball TBGA , 0.8mm Pitch Top View (Ball Down) Ball Name A0~A18 A19~A20 A21 DQ0 to DQ15 F-RP F-WP F-VCC VCCS VCCU VCCQU1) VSS UBU LBU UBS LBS F-RY/BY ZZ F-CE1 F-CE2 CS1S CS2S CSU WE OE NC DNU Description Address Input (Flash Memory, UtRAM, SRAM) Address Input (Flash Memory, UtRAM) Address Input (Flash Memory) Data Input/Output Balls (Common) Hardware Reset (Flash Memory) Write Protection (Flash Memory) Power Supply (Flash Memory) Power Supply (SRAM) Power Supply (UtRAM) Data Out Power (UtRAM) Ground (Common) Upper Byte Enable (UtRAM) Lower Byte Enable (UtRAM) Upper Byte Enable (SRAM) Lower Byte Enable (SRAM) Ready/Busy (Flash Memory) Deep Power Down (UtRAM) Chip Enable1 (Flash Memory) Chip Enable2 (Flash Memory) Chip Select1 (SRAM) Chip Select2 (SRAM) Chip Enable (UtRAM) Write Enable (Common) Output Enable (Common) No Connection Do Not Use 1) VCCQU=V CCU in this product. SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice. -2- Revision 0.1 February 2002 KBA0101A0M KBA0101A0M / KBA0201A0M KBA0201A0M KBA0301A0M KBA0301A0M / KBA0401A0M KBA0401A0M Preliminary MCP MEMORY ORDERING INFORMATION K B A 01 0 1 A 0 M - T 401 Access Time Mitsubishi NOR Flash: 85ns Mitsubishi NOR Flash: 85ns UtRAM: 85ns SRAM: 55ns Samsung MCP(4 Stack) Memory Device Type Mitsubishi NOR Flash +Mitsubishi NOR Flash +UtRAM +SRAM Package T = 80 TBGA NOR Flash Density (Organization) (BankSize) , Block Architecture 01 : 64Mbit + 64Mbit (x16 Selectable) (4Mb, 4Mb, 28Mb,28Mb) Flash 1: Bottom Boot Block Flash 2: Bottom Boot Block 02 : 64Mbit + 64Mbit (x16 Selectable) (4Mb, 4Mb, 28Mb,28Mb) Flash 1: Top Boot Block Flash 2: Top Boot Block 03 : 64Mbit + 64Mbit (x16 Selectable) (4Mb, 4Mb, 28Mb,28Mb) Flash 1: Bottom Boot Block Flash 2: Top Boot Block 04 : 64Mbit + 64Mbit (x16 Selectable) (4Mb, 4Mb, 28Mb,28Mb) Flash 1: Top Boot Block Flash 2: Bottom Boot Block Version M = 1st Generation SDRAM Density , Organization 0 = NONE SRAM Density , Organization 8Mbit , x16 Selectable UtRAM Density , Organization 32Mbit , x16 Selectable NAND Density , Organization 0 = NONE -3- Revision 0.1 February 2002 KBA0101A0M KBA0101A0M / KBA0201A0M KBA0201A0M KBA0301A0M KBA0301A0M / KBA0401A0M KBA0401A0M Preliminary MCP MEMORY FUNCTIONAL BLOCK DIAGRAM 128-word Page Buffer A0 ~ A18 (Common) Bank4 : 56 blocks A19, A20 F-Vcc Bank3 : 56 blocks Decorder Bank2 : 8 blocks A21 Vss Bank1 : 15 blocks Y-Gate / Sense Amp. OE WE F-CE1 F-WP Status/ ID Register Multi Plexer Command User Interface Write State Bank1 Machine Address X Dec Bank1 Cell Array I/O Buffer 128-word Page Buffer Bank4 : 56 blocks Bank3 : 56 blocks F-RP Decorder Bank2 : 8 blocks F-CE2 Bank1 : 15 blocks Y-Gate / Sense Amp. Status/ ID Register Multi Plexer Command User Interface Write State Bank1 Machine Address X Dec Bank1 Cell Array I/O Buffer DQ0 to UBu Clk gen. Precharge circuit. DQ15 LBu ZZ CS u UtRAM Main Cell Array Row select (2M x16) VccQU Control logic UBs Data cont I/O Circuit Column select Clk gen. VccU Precharge circuit. LBs CS1S SRAM Main Cell Array Row select CS2S Control logic (512K x16) Data cont I/O Circuit Column select -4- VccS Revision 0.1 February 2002 KBA0101A0M KBA0101A0M / KBA0201A0M KBA0201A0M KBA0301A0M KBA0301A0M / KBA0401A0M KBA0401A0M Preliminary MCP MEMORY Table 1. Flash Memory Top Boot Block Address (KBA0201A0 KBA0201A0) Address Range KBA0201A0 KBA0201A0 Block Block Size BA134 BA134 4 Kwords 3FF000H-3FFFFFH 3FF000H-3FFFFFH BA133 BA133 4 Kwords 3FE000H-3FEFFFH 3FE000H-3FEFFFH Word Mode (x16) BA132 BA132 3FD000H-3FDFFFH 3FD000H-3FDFFFH 4 Kwords 3FC000H-3FCFFFH 3FC000H-3FCFFFH BA130 BA130 4 Kwords 3FB000H-3FBFFFH 3FB000H-3FBFFFH BA129 BA129 4 Kwords 3FA000H-3FAFFFH 3FA000H-3FAFFFH BA128 BA128 4 Kwords 3F9000H-3F9FFFH 3F9000H-3F9FFFH BA127 BA127 4 Kwords 3F8000H-3F8FFFH 3F8000H-3F8FFFH BA126 BA126 32 Kwords 3F0000H-3F7FFFH 3F0000H-3F7FFFH BA125 BA125 32 Kwords 3E8000H-3EFFFFH 3E8000H-3EFFFFH BA124 BA124 32 Kwords 3E0000H-3E7FFFH 3E0000H-3E7FFFH BA123 BA123 32 Kwords 3D8000H-3DFFFFH 3D8000H-3DFFFFH BA122 BA122 32 Kwords 3D0000H-3D7FFFH 3D0000H-3D7FFFH BA121 BA121 32 Kwords 3C8000H-3CFFFFH 3C8000H-3CFFFFH BA120 BA120 32 Kwords 3C0000H-3C7FFFH 3C0000H-3C7FFFH BA119 BA119 32 Kwords 3B8000H-3BFFFFH 3B8000H-3BFFFFH BA118 BA118 32 Kwords 3B0000H-3B7FFFH 3B0000H-3B7FFFH BA117 BA117 32 Kwords 3A8000H-3AFFFFH 3A8000H-3AFFFFH BA116 BA116 32 Kwords 3A0000H-3A7FFFH 3A0000H-3A7FFFH BA115 BA115 32 Kwords 398000H-39FFFFH 398000H-39FFFFH BA114 BA114 32 Kwords 390000H-397FFFH 390000H-397FFFH BA113 BA113 32 Kwords 388000H-38FFFFH 388000H-38FFFFH BA112 BA112 32 Kwords 380000H-387FFFH 380000H-387FFFH BA111 BA111 Bank4 4 Kwords BA131 BA131 32 Kwords 378000H-37FFFFH 378000H-37FFFFH Bank3 BA110 BA110 32 Kwords 370000H-377FFFH 370000H-377FFFH BA109 BA109 32 Kwords 368000H-36FFFFH 368000H-36FFFFH BA108 BA108 32 Kwords 360000H-367FFFH 360000H-367FFFH BA107 BA107 32 Kwords 358000H-35FFFFH 358000H-35FFFFH BA106 BA106 32 Kwords 350000H-357FFFH 350000H-357FFFH BA105 BA105 32 Kwords 348000H-34FFFFH 348000H-34FFFFH BA104 BA104 32 Kwords 340000H-347FFFH 340000H-347FFFH BA103 BA103 32 Kwords 338000H-33FFFFH 338000H-33FFFFH BA102 BA102 32 Kwords 330000H-337FFFH 330000H-337FFFH BA101 BA101 32 Kwords 328000H-32FFFFH 328000H-32FFFFH BA100 BA100 32 Kwords 320000H-327FFFH 320000H-327FFFH BA99 32 Kwords 318000H-31FFFFH 318000H-31FFFFH BA98 32 Kwords 310000H-317FFFH 310000H-317FFFH BA97 32 Kwords 208000H-20FFFFH 208000H-20FFFFH BA96 32 Kwords 300000H-307FFFH 300000H-307FFFH BA95 32 Kwords 2F8000H-2FFFFFH 2F8000H-2FFFFFH BA94 32 Kwords 2F0000H-2F7FFFH 2F0000H-2F7FFFH BA93 32 Kwords 2E8000H-2EFFFFH 2E8000H-2EFFFFH BA92 32 Kwords 2E0000H-2E7FFFH 2E0000H-2E7FFFH BA91 32 Kwords 2D8000H-2DFFFFH 2D8000H-2DFFFFH BA90 32 Kwords 2D0000H-2D7FFFH 2D0000H-2D7FFFH Bank2 -5- Revision 0.1 February 2002 KBA0101A0M KBA0101A0M / KBA0201A0M KBA0201A0M KBA0301A0M KBA0301A0M / KBA0401A0M KBA0401A0M Preliminary MCP MEMORY Table 1. Flash Memory Top Boot Block Address (KBA0201A0 KBA0201A0) Address Range KBA0201A0 KBA0201A0 Block Block Size BA89 32 Kwords 2C8000H-2CFFFFH 2C8000H-2CFFFFH BA88 32 Kwords 2C0000H-2C7FFFH 2C0000H-2C7FFFH BA87 32 Kwords 2B8000H-2BFFFFH 2B8000H-2BFFFFH BA86 32 Kwords 2B0000H-2B7FFFH 2B0000H-2B7FFFH BA85 32 Kwords 2A8000H-2AFFFFH 2A8000H-2AFFFFH BA84 32 Kwords 2A0000H-2A7FFFH 2A0000H-2A7FFFH 298000H-29FFFFH 298000H-29FFFFH Word Mode (x16) BA83 32 Kwords BA82 32 Kwords 290000H-297FFFH 290000H-297FFFH BA81 32 Kwords 288000H-28FFFFH 288000H-28FFFFH BA80 32 Kwords 280000H-287FFFH 280000H-287FFFH 278000H-27FFFFH 278000H-27FFFFH BA79 32 Kwords 270000H-277FFFH 270000H-277FFFH BA77 Bank2 32 Kwords BA78 32 Kwords 268000H-26FFFFH 268000H-26FFFFH BA76 32 Kwords 260000H-267FFFH 260000H-267FFFH 258000H-25FFFFH 258000H-25FFFFH BA75 32 Kwords BA74 32 Kwords 250000H-257FFFH 250000H-257FFFH BA73 32 Kwords 248000H-24FFFFH 248000H-24FFFFH BA72 32 Kwords 240000H-247FFFH 240000H-247FFFH 238000H-23FFFFH 238000H-23FFFFH BA71 32 Kwords BA70 32 Kwords 230000H-237FFFH 230000H-237FFFH BA69 32 Kwords 228000H-22FFFFH 228000H-22FFFFH BA68 32 Kwords 220000H-227FFFH 220000H-227FFFH 218000H-21FFFFH 218000H-21FFFFH BA67 32 Kwords BA66 32 Kwords 210000H-217FFFH 210000H-217FFFH BA65 32 Kwords 208000H-20FFFFH 208000H-20FFFFH BA64 32 Kwords 200000H-207FFFH 200000H-207FFFH 1F8000H-1FFFFFH 1F8000H-1FFFFFH BA63 32 Kwords BA62 32 Kwords 1F0000H-1F7FFFH 1F0000H-1F7FFFH BA61 32 Kwords 1E8000H-1EFFFFH 1E8000H-1EFFFFH BA60 32 Kwords 1E0000H-1E7FFFH 1E0000H-1E7FFFH BA59 32 Kwords 1D8000H-1DFFFFH 1D8000H-1DFFFFH BA58 32 Kwords 1D0000H-1D7FFFH 1D0000H-1D7FFFH BA57 32 Kwords 1C8000H-1CFFFFH 1C8000H-1CFFFFH BA56 32 Kwords 1C0000H-1C7FFFH 1C0000H-1C7FFFH BA55 32 Kwords 1B8000H-1BFFFFH 1B8000H-1BFFFFH BA54 32 Kwords 1B0000H-1B7FFFH 1B0000H-1B7FFFH BA53 32 Kwords 1A8000H-1AFFFFH 1A8000H-1AFFFFH BA52 32 Kwords 1A0000H-1A7FFFH 1A0000H-1A7FFFH 198000H-19FFFFH 198000H-19FFFFH BA51 Bank1 32 Kwords BA50 32 Kwords 190000H-197FFFH 190000H-197FFFH BA49 32 Kwords 188000H-18FFFFH 188000H-18FFFFH BA48 32 Kwords 180000H-187FFFH 180000H-187FFFH 178000H-17FFFFH 178000H-17FFFFH BA47 32 Kwords BA46 32 Kwords 170000H-177FFFH 170000H-177FFFH BA45 32 Kwords 168000H-16FFFFH 168000H-16FFFFH -6- Revision 0.1 February 2002 KBA0101A0M KBA0101A0M / KBA0201A0M KBA0201A0M KBA0301A0M KBA0301A0M / KBA0401A0M KBA0401A0M Preliminary MCP MEMORY Table 1. Flash Memory Top Boot Block Address (KBA0201A0 KBA0201A0) Address Range KBA0201A0 KBA0201A0 Block Block Size BA44 32 Kwords 160000H-167FFFH 160000H-167FFFH BA43 32 Kwords 158000H-15FFFFH 158000H-15FFFFH BA42 32 Kwords 150000H-157FFFH 150000H-157FFFH BA41 32 Kwords 148000H-14FFFFH 148000H-14FFFFH BA40 32 Kwords 140000H-147FFFH 140000H-147FFFH BA39 32 Kwords 138000H-13FFFFH 138000H-13FFFFH BA38 32 Kwords 130000H-137FFFH 130000H-137FFFH BA37 32 Kwords 128000H-12FFFFH 128000H-12FFFFH BA36 32 Kwords 120000H-127FFFH 120000H-127FFFH BA35 32 Kwords 118000H-11FFFFH 118000H-11FFFFH BA34 32 Kwords 110000H-117FFFH 110000H-117FFFH BA33 32 Kwords 108000H-10FFFFH 108000H-10FFFFH BA32 32 Kwords 100000H-107FFFH 100000H-107FFFH BA31 32 Kwords F8000H-FFFFFH F8000H-FFFFFH BA30 32 Kwords F0000H-F7FFFH F0000H-F7FFFH BA29 32 Kwords E8000H-EFFFFH E8000H-EFFFFH BA28 32 Kwords E0000H-E7FFFH E0000H-E7FFFH BA27 32 Kwords D8000H-DFFFFH D8000H-DFFFFH BA26 32 Kwords D0000H-D7FFFH D0000H-D7FFFH BA25 32 Kwords C8000H-CFFFFH C8000H-CFFFFH BA24 32 Kwords C0000H-C7FFFH C0000H-C7FFFH BA23 32 Kwords B8000H-BFFFFH B8000H-BFFFFH BA22 32 Kwords B0000H-B7FFFH B0000H-B7FFFH BA21 32 Kwords A8000H-AFFFFH A8000H-AFFFFH BA20 32 Kwords A0000H-A7FFFH A0000H-A7FFFH BA19 32 Kwords 98000H-9FFFFH 98000H-9FFFFH BA18 32 Kwords 90000H-97FFFH 90000H-97FFFH BA17 32 Kwords 88000H-8FFFFH 88000H-8FFFFH BA16 32 Kwords 80000H-87FFFH 80000H-87FFFH BA15 32 Kwords 78000H-7FFFFH 78000H-7FFFFH BA14 32 Kwords 70000H-77FFFH 70000H-77FFFH BA13 32 Kwords 68000H-6FFFFH 68000H-6FFFFH BA12 32 Kwords 60000H-67FFFH 60000H-67FFFH BA11 32 Kwords 58000H-5FFFFH 58000H-5FFFFH BA10 32 Kwords 50000H-57FFFH 50000H-57FFFH BA9 32 Kwords 48000H-4FFFFH 48000H-4FFFFH BA8 32 Kwords 40000H-47FFFH 40000H-47FFFH BA7 32 Kwords 38000H-3FFFFH 38000H-3FFFFH BA6 32 Kwords 30000H-37FFFH 30000H-37FFFH BA5 32 Kwords 28000H-2FFFFH 28000H-2FFFFH BA4 32 Kwords 20000H-27FFFH 20000H-27FFFH BA3 32 Kwords 18000H-1FFFFH 18000H-1FFFFH BA2 32 Kwords 10000H-17FFFH 10000H-17FFFH BA1 32 Kwords 08000H-0FFFFH 08000H-0FFFFH BA0 32 Kwords 00000H-07FFFH 00000H-07FFFH Word Mode (x16) Bank1 -7- Revision 0.1 February 2002 KBA0101A0M KBA0101A0M / KBA0201A0M KBA0201A0M KBA0301A0M KBA0301A0M / KBA0401A0M KBA0401A0M Preliminary MCP MEMORY Table 2. Flash Memory Bottom Boot Block Address (KBA0101A0 KBA0101A0) Address Range KBA0101A0 KBA0101A0 Block Block Size BA134 BA134 32 Kwords 3F8000H-3FFFFFH 3F8000H-3FFFFFH BA133 BA133 32 Kwords 3F0000H-3F7FFFH 3F0000H-3F7FFFH BA132 BA132 32 Kwords 3E8000H-3EFFFFH 3E8000H-3EFFFFH BA131 BA131 32 Kwords 3E0000H-3E7FFFH 3E0000H-3E7FFFH BA130 BA130 32 Kwords 3D8000H-3DFFFFH 3D8000H-3DFFFFH BA129 BA129 32 Kwords 3D0000H-3D7FFFH 3D0000H-3D7FFFH Word Mode (x16) BA128 BA128 3C8000H-3CFFFFH 3C8000H-3CFFFFH 32 Kwords 3C0000H-3C7FFFH 3C0000H-3C7FFFH BA126 BA126 32 Kwords 3B8000H-3BFFFFH 3B8000H-3BFFFFH BA125 BA125 32 Kwords 3B0000H-3B7FFFH 3B0000H-3B7FFFH BA124 BA124 32 Kwords 3A8000H-3AFFFFH 3A8000H-3AFFFFH BA123 BA123 32 Kwords 3A0000H-3A7FFFH 3A0000H-3A7FFFH BA122 BA122 32 Kwords 398000H-39FFFFH 398000H-39FFFFH BA121 BA121 32 Kwords 390000H-397FFFH 390000H-397FFFH BA120 BA120 32 Kwords 388000H-38FFFFH 388000H-38FFFFH BA119 BA119 32 Kwords 380000H-387FFFH 380000H-387FFFH BA118 BA118 32 Kwords 378000H-37FFFFH 378000H-37FFFFH BA117 BA117 32 Kwords 370000H-377FFFH 370000H-377FFFH BA116 BA116 32 Kwords 368000H-36FFFFH 368000H-36FFFFH BA115 BA115 32 Kwords 360000H-367FFFH 360000H-367FFFH BA114 BA114 Bank4 32 Kwords BA127 BA127 32 Kwords 358000H-35FFFFH 358000H-35FFFFH BA113 BA113 32 Kwords 350000H-357FFFH 350000H-357FFFH BA112 BA112 32 Kwords 348000H-34FFFFH 348000H-34FFFFH BA111 BA111 32 Kwords 340000H-347FFFH 340000H-347FFFH BA110 BA110 32 Kwords 338000H-33FFFFH 338000H-33FFFFH BA109 BA109 32 Kwords 330000H-337FFFH 330000H-337FFFH BA108 BA108 32 Kwords 328000H-32FFFFH 328000H-32FFFFH BA107 BA107 32 Kwords 320000H-327FFFH 320000H-327FFFH BA106 BA106 32 Kwords 318000H-31FFFFH 318000H-31FFFFH BA105 BA105 32 Kwords 310000H-317FFFH 310000H-317FFFH BA104 BA104 32 Kwords 208000H-20FFFFH 208000H-20FFFFH BA103 BA103 32 Kwords 300000H-307FFFH 300000H-307FFFH BA102 BA102 32 Kwords 2F8000H-2FFFFFH 2F8000H-2FFFFFH BA101 BA101 32 Kwords 2F0000H-2F7FFFH 2F0000H-2F7FFFH BA100 BA100 32 Kwords 2E8000H-2EFFFFH 2E8000H-2EFFFFH BA99 32 Kwords 2E0000H-2E7FFFH 2E0000H-2E7FFFH BA98 32 Kwords 2D8000H-2DFFFFH 2D8000H-2DFFFFH BA97 32 Kwords 2D0000H-2D7FFFH 2D0000H-2D7FFFH BA96 32 Kwords 2C8000H-2CFFFFH 2C8000H-2CFFFFH BA95 32 Kwords 2C0000H-2C7FFFH 2C0000H-2C7FFFH BA94 32 Kwords 2B8000H-2BFFFFH 2B8000H-2BFFFFH BA93 32 Kwords 2B0000H-2B7FFFH 2B0000H-2B7FFFH BA92 32 Kwords 2A8000H-2AFFFFH 2A8000H-2AFFFFH BA91 32 Kwords 2A0000H-2A7FFFH 2A0000H-2A7FFFH BA90 32 Kwords 298000H-29FFFFH 298000H-29FFFFH -8- Revision 0.1 February 2002 KBA0101A0M KBA0101A0M / KBA0201A0M KBA0201A0M KBA0301A0M KBA0301A0M / KBA0401A0M KBA0401A0M Preliminary MCP MEMORY Table 2. Flash Memory Bottom Boot Block Address (KBA0101A0 KBA0101A0) Address Range KBA0101A0 KBA0101A0 Block Block Size BA89 32 Kwords 290000H-297FFFH 290000H-297FFFH BA88 32 Kwords 288000H-28FFFFH 288000H-28FFFFH Word Mode (x16) BA87 280000H-287FFFH 280000H-287FFFH 32 Kwords 278000H-27FFFFH 278000H-27FFFFH BA85 32 Kwords 270000H-277FFFH 270000H-277FFFH BA84 32 Kwords 268000H-26FFFFH 268000H-26FFFFH BA83 32 Kwords 260000H-267FFFH 260000H-267FFFH BA82 32 Kwords 258000H-25FFFFH 258000H-25FFFFH BA81 32 Kwords 250000H-257FFFH 250000H-257FFFH BA80 32 Kwords 248000H-24FFFFH 248000H-24FFFFH BA79 32 Kwords 240000H-247FFFH 240000H-247FFFH BA78 32 Kwords 238000H-23FFFFH 238000H-23FFFFH BA77 32 Kwords 230000H-237FFFH 230000H-237FFFH BA76 32 Kwords 228000H-22FFFFH 228000H-22FFFFH BA75 32 Kwords 220000H-227FFFH 220000H-227FFFH BA74 32 Kwords 218000H-21FFFFH 218000H-21FFFFH BA73 32 Kwords 210000H-217FFFH 210000H-217FFFH BA72 32 Kwords 208000H-20FFFFH 208000H-20FFFFH BA71 32 Kwords 200000H-207FFFH 200000H-207FFFH BA70 32 Kwords 1F8000H-1FFFFFH 1F8000H-1FFFFFH BA69 32 Kwords 1F0000H-1F7FFFH 1F0000H-1F7FFFH BA68 32 Kwords 1E8000H-1EFFFFH 1E8000H-1EFFFFH BA67 32 Kwords 1E0000H-1E7FFFH 1E0000H-1E7FFFH BA66 32 Kwords 1D8000H-1DFFFFH 1D8000H-1DFFFFH BA65 32 Kwords 1D0000H-1D7FFFH 1D0000H-1D7FFFH BA64 32 Kwords 1C8000H-1CFFFFH 1C8000H-1CFFFFH BA63 32 Kwords 1C0000H-1C7FFFH 1C0000H-1C7FFFH BA62 Bank4 32 Kwords BA86 32 Kwords 1B8000H-1BFFFFH 1B8000H-1BFFFFH BA61 32 Kwords 1B0000H-1B7FFFH 1B0000H-1B7FFFH BA60 32 Kwords 1A8000H-1AFFFFH 1A8000H-1AFFFFH BA59 32 Kwords 1A0000H-1A7FFFH 1A0000H-1A7FFFH BA58 32 Kwords 198000H-19FFFFH 198000H-19FFFFH BA57 32 Kwords 190000H-197FFFH 190000H-197FFFH BA56 32 Kwords 188000H-18FFFFH 188000H-18FFFFH BA55 32 Kwords 180000H-187FFFH 180000H-187FFFH BA54 32 Kwords 178000H-17FFFFH 178000H-17FFFFH BA53 32 Kwords 170000H-177FFFH 170000H-177FFFH BA52 32 Kwords 168000H-16FFFFH 168000H-16FFFFH BA51 32 Kwords 160000H-167FFFH 160000H-167FFFH BA50 32 Kwords 158000H-15FFFFH 158000H-15FFFFH BA49 32 Kwords 150000H-157FFFH 150000H-157FFFH BA48 32 Kwords 148000H-14FFFFH 148000H-14FFFFH BA47 32 Kwords 140000H-147FFFH 140000H-147FFFH BA46 32 Kwords 138000H-13FFFFH 138000H-13FFFFH BA45 32 Kwords 130000H-137FFFH 130000H-137FFFH Bank3 -9- Revision 0.1 February 2002 KBA0101A0M KBA0101A0M / KBA0201A0M KBA0201A0M KBA0301A0M KBA0301A0M / KBA0401A0M KBA0401A0M Preliminary MCP MEMORY Table 2. Flash Memory Bottom Boot Block Address (KBA0101A0 KBA0101A0) Address Range KBA0101A0 KBA0101A0 Block Block Size BA44 32 Kwords 128000H-12FFFFH 128000H-12FFFFH BA43 32 Kwords 120000H-127FFFH 120000H-127FFFH 118000H-11FFFFH 118000H-11FFFFH Word Mode (x16) BA42 32 Kwords 110000H-117FFFH 110000H-117FFFH BA40 32 Kwords 108000H-10FFFFH 108000H-10FFFFH BA39 32 Kwords 100000H-107FFFH 100000H-107FFFH BA38 32 Kwords F8000H-FFFFFH F8000H-FFFFFH BA37 32 Kwords F0000H-F7FFFH F0000H-F7FFFH BA36 Bank3 32 Kwords BA41 32 Kwords E8000H-EFFFFH E8000H-EFFFFH BA35 32 Kwords E0000H-E7FFFH E0000H-E7FFFH D8000H-DFFFFH D8000H-DFFFFH BA34 32 Kwords BA33 32 Kwords D0000H-D7FFFH D0000H-D7FFFH BA32 32 Kwords C8000H-CFFFFH C8000H-CFFFFH BA31 32 Kwords C0000H-C7FFFH C0000H-C7FFFH BA30 32 Kwords B8000H-BFFFFH B8000H-BFFFFH BA29 32 Kwords B0000H-B7FFFH B0000H-B7FFFH BA28 32 Kwords A8000H-AFFFFH A8000H-AFFFFH BA27 32 Kwords A0000H-A7FFFH A0000H-A7FFFH BA26 32 Kwords 98000H-9FFFFH 98000H-9FFFFH BA25 32 Kwords 90000H-97FFFH 90000H-97FFFH BA24 32 Kwords 88000H-8FFFFH 88000H-8FFFFH BA23 32 Kwords 80000H-87FFFH 80000H-87FFFH BA22 32 Kwords 78000H-7FFFFH 78000H-7FFFFH BA21 32 Kwords 70000H-77FFFH 70000H-77FFFH BA20 32 Kwords 68000H-6FFFFH 68000H-6FFFFH BA19 32 Kwords 60000H-67FFFH 60000H-67FFFH BA18 32 Kwords 58000H-5FFFFH 58000H-5FFFFH BA17 32 Kwords 50000H-57FFFH 50000H-57FFFH BA16 32 Kwords 48000H-4FFFFH 48000H-4FFFFH BA15 32 Kwords 40000H-47FFFH 40000H-47FFFH BA14 32 Kwords 38000H-3FFFFH 38000H-3FFFFH BA13 32 Kwords 30000H-37FFFH 30000H-37FFFH BA12 32 Kwords 28000H-2FFFFH 28000H-2FFFFH BA11 32 Kwords 20000H-27FFFH 20000H-27FFFH BA10 32 Kwords 18000H-1FFFFH 18000H-1FFFFH BA9 32 Kwords 10000H-17FFFH 10000H-17FFFH BA8 32 Kwords 08000H-0FFFFH 08000H-0FFFFH BA7 4 Kwords 07000H-07FFFH 07000H-07FFFH BA6 4 Kwords 06000H-06FFFH 06000H-06FFFH BA5 4 Kwords 05000H-05FFFH 05000H-05FFFH BA4 4 Kwords 04000H-04FFFH 04000H-04FFFH BA3 4 Kwords 03000H-03FFFH 03000H-03FFFH BA2 4 Kwords 02000H-02FFFH 02000H-02FFFH BA1 4 Kwords 01000H-01FFFH 01000H-01FFFH BA0 4 Kwords 00000H-00FFFH 00000H-00FFFH Bank2 Bank1 - 10 - Revision 0.1 February 2002 KBA0101A0M KBA0101A0M / KBA0201A0M KBA0201A0M KBA0301A0M KBA0301A0M / KBA0401A0M KBA0401A0M Preliminary MCP MEMORY Flash MEMORY COMMAND DEFINITION Table 3. Command List (F-WP = VIH or VIL) 1st Cycle Command Mode 2nd Cycle Address 1) Data (DQ0-15 DQ0-15) Address Read Array Write X Write X Device Identifier Write Read Status Register Write Bank2) Clear Status Register Write X Write Bank2) Write Bank2) Address Data1) (DQ0-15 DQ0-15) Read SA+i6) RDi B0H Resume Mode 50H Suspend A0 Data (DQ0-15 DQ0-15) RD0 A21-A18 A21-A18 F3H Bank2) Mode FFH Sequential Page Read 3rd Cycle 1) D0H Notes : Read SA5) 90H Read Bank2) 70H Read IA3) Bank2) ID SRD4) 1. Upper byte data (DQ15-DQ8 DQ15-DQ8) is ignored. 2. Bank=Bank address (bank1-Bank4:A21-18 A21-18) 3. IA=ID code address:A0=VIL (Manufacture' code):A0=V IH (Device code), ID=ID code s 4. SRD=Status Register Data 5. SA=Sequential page Address:A21-A3 A21-A3, A2-A0:0h 6. SA+i;A21-A3 A21-A3 must be flxed and A2-A0 must be incremented from 0h to 7h. Table 4. Command List (F-WP = V IH) 1st Cycle Command 2nd Cycle 3rd Cycle Mode Address Data1) (DQ0-15 DQ0-15) Mode Address Data1) (DQ0-15 DQ0-15) Word Program Write Bank 40H Write WA2) WD2) Page Program Write Bank 41H Write WA0 3) WD03) 4) Address Data1) (DQ0-15 DQ0-15) Write WAn3) WDn3) D0 5) Mode 1) Page Buffer to Flash Write Bank 0EH Write Block Erase / Confirm Write Bank 20H Write BA D01) Erase All Unlocked Blocks Write X A7H Write X D01) Clear Page Buffer Write X 55H Write X D01) Single Date Load to Page Buffer Write Bank 74H Write WA WD Write 6) D01) Flash to Page Buffer Notes : Write Bank F1H WA RA 1. Upper byte data (DQ15-DQ8 DQ15-DQ8) is ignored. 2. WA=Write Address, WD=Write Data 3. WA0, WAn=Write Address, WD0, WDn=Write Data, Write address and write data must be provided sequentially from 00H to 7FH for A6-A0. Page size is 128 words (128-word x 16-bit), and also A21-A7 A21-A7(block address, page address) must be valid. 4. WA=Write Address:A21-A7 A21-A7 (block address, page address) must be valid. 5. BA=Block Address:A21-A12 A21-A12(Bank1), A21-A15 A21-A15(Bank2, Bank3, Bank4) 6. RA=Read Address:A21-A7 A21-A7 (block address, page address) must be valid. - 11 - Revision 0.1 February 2002 KBA0101A0M KBA0101A0M / KBA0201A0M KBA0201A0M KBA0301A0M KBA0301A0M / KBA0401A0M KBA0401A0M Preliminary MCP MEMORY Flash MEMORY COMMAND DEFINITION Software lock release operation needs following consecutive 7bus cycles. Moreover, additional 127 bus cycles are needed for page program operation. Table 5. Command List (F-WP = VIH or VIL) 1st Cycle Setup Command for Software Lock Release Mode Write Word Program Page Program 3) Address Bank 2nd Cycle Data1) (DQ0-15 DQ0-15) 60H Mode Write Bank 60H Write Bank 60H Write Data1) (DQ0-15 DQ0-15) Write Bank ACH Write Bank ACH 6) Write Bank ACH 6) (DQ0-15 DQ0-15) Bank Write Page Buffer to Flash Address 6) Bank Mode Block6) Address Write 3rd Cycle Data1) Bank Block Block Block Erase / Confirm Write Bank 60H Write Bank Write Bank ACH Erase All Unlocked Blocks Write Bank 60H Write Bank 6) Block Write Bank ACH Clear Page Buffer Write Bank 60H Write Bank Block6) Write Bank ACH 6) Write Bank ACH 6) Write Bank ACH Single Data Load to Page Buffer Write Bank 60H Write Bank Flash to Page Buffer Write Bank 60H Write Block Bank 4th Cycle Setup Command for Software Lock Release Block 5th Cycle Mode Mode Address Data1) (DQ0-15 DQ0-15) Bank Block6) Write Bank 78H Bank 6) Block Write Bank 78H Write Page Buffer to Flash Data (DQ0-15 DQ0-15) Write 3) Address Write Word Program Page Program Block 1) Bank Block6) Write Bank 78H Block Erase / Confirm Write Bank Block6) Write Bank 78H Erase All Unlocked Blocks Write Bank Block6) Write Bank 78H Clear Page Buffer Write Bank Block6) Write Bank 78H Single Data Load to Page Buffer Write Bank Block6) Write Bank 78H Flash to Page Buffer Write Bank Block6) Write Bank 78H 6th Cycle Setup Command for Software Lock Release 7th Cycle 1) 8th-134th Cycle 1) Mode 3) Data (DQ0-15 DQ0-15) Mode Address Bank 40h Write WA2) Mode Address Data1) (DQ0-15 DQ0-15) Write Data (DQ0-15 DQ0-15) Write Word Program Address WAn3) WDn3) WD2) 3) WD03) Page Program Write Bank 41h Write WA0 Page Buffer to Flash Write Bank 0Eh Write WA4) D01) 5) D01) Block Erase / Confirm Write Bank 20H Write BA Erase All Unlocked Blocks Write X A7H Write X D01) Clear Page Buffer Write X 55H Write X D01) Single Data Load to Page Buffer Write Bank 74H Write WA WD Write RA7) D01) Flash to Page Buffer Notes : Write Bank F1H 1. Upper byte data (DQ15-DQ8 DQ15-DQ8) is ignored. 2. WA=Write Address, WD=Write Data 3. WA0, WAn=Write Address, WD0, WDn=Write Data, Write address and write data must be provided sequentially from 00H to 7FH for A6-A0. Page size is 128 words (128 word x 16 bit), and also A21-A7 A21-A7(block address, page address) must be valid. 4. WA=Write Address:A21-A7 A21-A7 (block address, page address) must be valid. 5. BA=Block Address:A21-A12 A21-A12(Bank1), A21-A15 A21-A15(Bank2, Bank3, Bank4) 6. Block=Block Address:A21-A15 A21-A15, Block=A21-A15 A21-A15 Address DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 Block Fixed0 A21 A20 A19 A18 A17 A16 A15 Block Fixed0 A21 A20 A19 A18 A17 A16 A15 7. RA=Read Address: A21-A7 A21-A7 (block address, page address) must be valid. - 12 - Revision 0.1 February 2002 KBA0101A0M KBA0101A0M / KBA0201A0M KBA0201A0M KBA0301A0M KBA0301A0M / KBA0401A0M KBA0401A0M Preliminary MCP MEMORY Table 6. Device ID Code A0 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 Hex Date Manufacturer Code Code \ Pins VIL "0" "0" "0" "1" "1" "1" "0" "0" 1CH Devide Code (Bottom Boot) VIH "0" "0" "1" "0" "1" "0" "1" "0" 2AH Devide Code (Top Boot) VIH "0" "0" "1" "0" "1" "0" "1" "1" 2BH The output of upper byte data (DQ15-DQ7 DQ15-DQ7) is "0". Table 7. Block Locking Write Protection Provided F-RP Bank3 Bank4 Parameter/Main Main Main Main x Locked Locked Locked Locked Locked Deep Power Down Mode VIL Locked Locked Locked Locked Locked All Blocks Locked (Valid to operate Software Lock Release) VIH VIH Bank2 Boot VIL F-WP Bank1 Notes Unlocked Unlocked Unlocked Unlocked Unlocked All Blocks Unlocked F-WP pin must not be switched during performing Read / Write operations or WSM busy (WSMS=0). Table 8. Status Register Definition Symbol (I/O Pin) Status S.R.7 (AQ7) Write State Machine Status Ready Busy S.R.6 (DQ6) Suspend Status Suspended Operation in Progress/Completed S.R.5 (DQ5) Erase Status Error Successful S.R.4 (DQ4) Program Status Error Successful S.R.3 (DQ3) Block Status after Program Error Successful S.R.2 (DQ2) Reserved - - S.R.1 (DQ1) Reserved - - S.R.0 (DQ0) Reserved - - "1" - 13 - "0" Revision 0.1 February 2002 KBA0101A0M KBA0101A0M / KBA0201A0M KBA0201A0M KBA0301A0M KBA0301A0M / KBA0401A0M KBA0401A0M Preliminary MCP MEMORY Table 9. Flash Memory Operation Table DQ0-15 DQ0-15 Mode \ Pins F-CE1 F-CE2 OE WE F-RP Flash 1 VIL Array VIL VIH Flash 2 Data-Output VIH High-Z Data-Output VIH VIH VIL High-Z VIL VIH Data-Output High-Z VIH VIL High-Z Data-Output VIL VIH Status Register Data High-Z Status Register Data Sequential VIL VIH VIH Read Status Register VIL VIH VIH VIH VIL High-Z VIL VIH Identifier Code High-Z VIH VIL High-Z Identifier Code VIL VIL High-Z High-Z Identifier Code Output Disable VIL VIH VIH VIH VIH VIH VIL VIL VIH VIH VIH VIL Program VIL Command / Data-In VIL Erase VIL VIL VIH VIH X1) X Deep Power Down X X X X Command VIH VIH Standby High-Z High-Z VIL VIH Notes : Command / Data-In Command VIH Others High-Z High-Z VIH VIH Write VIH Command VIL High-Z High-Z VIH Command VIH High-Z High-Z VIL High-z High-z VIH 1. X can be VIH or VIL for control pins - 14 - Revision 0.1 February 2002 KBA0101A0M KBA0101A0M / KBA0201A0M KBA0201A0M KBA0301A0M KBA0301A0M / KBA0401A0M KBA0401A0M Preliminary MCP MEMORY Flash DEVICE OPERATION The 64Mbit DINOR IV Flash Memory includes on-chip program/erase control circuitry. The Write State Machine(WSM) control block erase and word/page program operations. Operational modes are selected by the commands written to the Command User Interface (CUI). The Status Register indicates the status of the WSM and when the WSM successfully completes the desired program or block erase operation. A Deep Power Down mode is enabled when the F-RP pin is at Vss, minimizing power consumption. Read Mode The 64Mbit DINOR IV Flash Memory has four read modes, which accesses to the memory array, the Sequential Page Read, the Device Identifier and the Status Register. The appropriate read commands are required to be written to the CUI. Upon initial device power up or after exit from deep power down, the 64Mbit DINOR IV Flash Memory automatically resets to read array mode. In the read array mode and in the conditions are low level input to OE, high level input to WE and F-RP, low level input to F-CE and address signals to the address inputs (A21 - A0) the data of the addressed location to the data input/output (DQ15-DQ0 DQ15-DQ0) is output. Standby Mode When F-CE is at VIH, the device is in the standby mode and its power consumption is reduced. Data input/output are in a highimpedance (High-Z) state. If the memory is deselected during block erase or program, the internal control circuits remain active and the device consumes normal active power until the operation completes. Output Disable When OE is at VIH, output from the devices is disabled. Data input/output are in a high-impedance (High-Z) state. Automatic Power Down (APD) The Automatic Power Down minimizes the power consumption during read mode. The device automatically turns to this mode when any addresses or F-CE isn't changed more than 200ns after the last alternation. The power consumption becomes the same as the stand-by mode. During this mode, the output data is latched and can be read out. New data is read out correctly when addresses are changed. Deep Power Down When F-RP is at VIL, the device is in the deep power down mode and its power consumption is substantially low. During read modes, the memory is deselected and the data input/output are in a high-impedance (High-Z) state. After return from power down, the CUI is reset to Read Array, and the Status Register is cleared to value 80H. During block erase or program modes, F-RP low will abort either operation. Memory array data of the block being altered become invalid. Write Mode Writes to the CUI enables reading of memory array data, device identifiers and reading and clearing of the Status Register. They also enable block erase and program. The CUI is written by bringing WE to low level and OE is at high level, while F-CE is at low level. Address and data are latched on the earlier rising edge of WE and F-CE. Standard micro processor write timings are used. Alternating Background Operation (BGO) The 64Mbit DINOR IV Flash Memory allows to read array from one bank while the other bank operates in software command write cycling or the erasing / programming operation in the background. Array Read operation with the other bank in BGO is performed by changing the bank address without any additional command. When the bank address points the bank in software command write cycling or the erasing / programming operation, the data is read out from the status register. The access time with BGO is the same as the normal read operation. BGO must be between Bank1, Bank2, Bank3, and Bank4. Back Bank array Read (BBR) In the 64Mbit DINOR IV Flash Memory , when one memory address is read according to a Read Mode in the case of the same as an access when a Read Mode command is input, an another Bank memory data can be read out (Random or Sequential Mode) by changing an another Bank address. - 15 - Revision 0.1 February 2002 KBA0101A0M KBA0101A0M / KBA0201A0M KBA0201A0M KBA0301A0M KBA0301A0M / KBA0401A0M KBA0401A0M Preliminary MCP MEMORY Software Command Definitions The device operations are selected by writing specific software command into the Commnad User Interface. Read Array Command (FFH) The device is in Read Array mode on initial device power up and after exit from deep power down, or by writing FFH to the Command User Interface. After starting the internal operation the device is set to the read status register mode automatically. Sequential Page Read Command (F3H) The Sequential Page Read command (F3H) timing can be used by writing the first command. This command is fast sequential 8 words read. During the read it is necessary to fix F-CE low and increase the addresses sequentially from 0h to 7h. The mode is kept until Read Array command is input. The first read of Seq. Page Read timing is the same as normal read (ta(CE). F-CE should be fallen "L". The read timing after the first is fast read (ta(PAD). When an another sequential page (A21-A3 A21-A3) is accessed before one sequential page (one 8-word) read is not finished, once F-CE is at VIH and A2-A0 data are 0h, after that F-CE is at VIL we can use the first read of Seq. Page Read or normal read (ta(CE). Read Device Identifier Command (90H) We can normally read device identifier codes when Read Device Identifier Code Command (90H) is written to the command latch. Following the command write, the manufacturer code and the device code can be read from address 0000H 0000H and 0001H 0001H, respectively. Read Status Register Command (70H) The Status Register is read after writing the Read Status Register command of 70H to the Command User Interface. Also, after starting the internal operation the device is set to the Read Status Register mode automatically. The contents of Status Register are latched on the later falling edge of OE must be toggled every status read. Clear Status Register Command (50H) The Erase Status, Program Status and Block Status bits are set to "1"s by the Write State Machine and can only be reset by the Clear Status Register command of 50H. These bits indicate various failure conditions. status read. Block Erase / Confirm Command (20H/D0H 20H/D0H) Automated block erase is initiated by writing the Block Erase command of 20H followed by the Confirm command of D0H. An address within the block to be erased is required. The WSM executes iterative erase pulse application and erase verify operation. Program Commands 1) Word Program (40H) Word program is executed by a two-command sequence. The Word program Setup command of 40H is written to the Command Interface, followed by a second write specifying the address and data to be written. The WSM controls the program pulse application and verify operation. 2) Page Program for Data Blocks (41H) Page Program allows fast programming of 128words of data. Writing of 41H initiates the page program operation for the Data area. From 2nd cycle to 129th cycle, write data must be serially inputted. Address A6-A0 have to be incremented from 00H to 7FH. After completion of data loading, the WSM controls the program pulse application and verify operation. 3) Single Data Load to Page Buffer (74H) / Page Buffer to Flash (0EH/D0H) Single data load to the page buffer is performed by writing 74H followed by a second write specifying the column address and data. Distinct data up to 128word can be loaded to the page buffer by this two-command sequence. On the other hand, all of the loaded data to the page buffer is programmed simultaneously by writing Page Buffer to Flash command of 0EH followed by the confirm command of D0H. After completion of programming the data on the page buffer is cleared automatically. - 16 - Revision 0.1 February 2002 KBA0101A0M KBA0101A0M / KBA0201A0M KBA0201A0M KBA0301A0M KBA0301A0M / KBA0401A0M KBA0401A0M Preliminary MCP MEMORY Flash to Page Buffer Command (F1H/D0H) Array data load to the page buffer is performed by writing the Flash to Page Buffer command of F1H followed by the Confirm command of D0H. An address within the page to be loaded is required. Then the array data can be copied into the other pages within the same bank by using the Page Buffer to Flash command. Clear Page Buffer Command (55H/D0H 55H/D0H) Loaded data to the page buffer is cleared by writing the Clear Page Buffer command of 55H followed by the Confirm command of D0H. This command is valid for clearing data loaded by Single Data Load to Page Buffer command. Suspend/Resume Command (B0H/D0H) Writing the Suspend command of B0H during block erase operation interrupts the block erase operation and allows read out from another block of memory. Writing the Suspend command of B0H during program operation interrupts the program operation and allows read out from another block of memory. The Bank address is required when writing the Suspend/Resume Command. The device continues to output Status Register data when read, after the Suspend command is written to it. Polling the WSM Status and Suspend Status bits will determine when the erase operation or program operation has been suspended. At this point, writing of the Read Array command to the CUI enables reading data from blocks other than that which is suspended. When the Resume command of D0H is written to the CUI, the WSM will continue with the erase or program processes. Data Protection The 64M-bit DINOR(IV) Flash Memory has a master Write Protect pin (F-WP). When F-WP is at V IH, all blocks can be programmed or erased. When F-WP is low, all blocks are in locked mode which prevents any modifications to memory blocks. Software Lock Release function is only command which allows to program or erase. See the BLOCK LOCKING table on 13 page for details. Power Supply Voltage When the power supply voltage is less than VLKO, Low Vcc Lock-Out voltage, the device is set to the Read-only mode. Regarding DC electrical characteristics of VLKO, see 18 page. A delay time of 2us is required before any device operation is initiated. The delay time is measured from the time Vcc reaches Vccmin (2.7V). During power up, F-RP = Vss is recommended. Falling in Busy status is not recommended for possibility of damaging the device. Memory Organization The 64Mbit DINOR IV Flash Memory is constructed by 2 boot blocks of 4K words, 6 parameter blocks of 4K words and 7 main blocks of 32K words in Bank1, by 8 main blocks of 32K words in Bank2 and by 56 main blocks of 32K words in Bank3 and Bank4. CAPACITANCE Item Input Capacitance Output Capacitance Symbol Test Condition A21-A0 A21-A0, OE, WE, F-CE, F-WP, F-RP CIN TA=25°C, DQ15-DQ0 DQ15-DQ0, F-RY/BY COUT f=1MHz, Vin=Vout=0V - 17 - Min Max Unit 35 pF 45 pF Revision 0.1 February 2002 KBA0101A0M KBA0101A0M / KBA0201A0M KBA0201A0M KBA0301A0M KBA0301A0M / KBA0401A0M KBA0401A0M Preliminary MCP MEMORY ABSOLUTE MAXIMUM RATINGS Parameter Symbol Conditions Rating F-Vcc Voltage F-Vcc With Respect to Vss -0.2 to +4.6 All input or Output VI1 Voltage1) Unit V -0.6 to +4.6 Ambient Temperature Ta -40 to +85 Temperature under Bias Tbs -50 to +95 Storage Temperature Tstg -65 to +125 Outputs Short Circuit Current Iout 100 (Max.) °C mA Notes : 1. Minimum DC voltage is -0.5V on input / output pins. During transitions, the level may undershoot to -2.0V for periods