KB-16 405A3 405B3 405D4 SA-12E SA-27E 200WC1 300TC1 266WC2 390TC2 405GP - Datasheet Archive

 

Reusable processor cores for high performance system-on-a-chip applications Highlights Compatible with the scalable and flexible

 

PowerPC® 405 Embedded Cores Reusable processor cores for high performance system-on-a-chip applications Highlights Compatible with the scalable and flexible PowerPC instruction set architecture to facilitate code reuse Optimized for high performance, low cost, and low power consumption system-on-a-chip (SOC) designs Supports product differentiation via inclusion of custom logic and/ or low cost JTAG and Trace FIFO ports enable robust debug capabilities, even in complex SOC designs Available in the IBM Blue LogicTM core library for integration with peripheral and applicationspecific macro cores to develop SOC solutions Supported by over 75 third-party vendors in IBM's PowerPC Embedded ToolsTM Program Full-function simulation models are available to support SWIFT compliant VHDL and Verilog simulation environments PowerPC 405 CPU · Compatible with PowerPC User Instruction Set Architecture · Five-stage pipeline · 32-bit x 32 general purpose registers · Hardware multiply and divide · Branch prediction Cache Controllers · Separate I- and D- cache units · Fill-first, data forwarding · Non-blocking flush operations · Programmable loads and store Inst. OCM I-Cache I-Cache Array Controller Instruction Cache Unit Timers · 64-bit time-base · Programmable interval timer · Fixed interval timer · Watchdog timer Debug Support · 4 Instruction Address, 2 Data Address, and 2 Data Value breakpoints · Real-time non-invasive trace · Exclusive traceback capability Memory Management Unit · Variable page sizes (1 KB-16 KB-16 MB) · 64-entry fully-associative TLB PLB Master I/O Interfaces · Processor Local Bus (PLB) · Auxiliary Processing Unit (APU) · On-Chip Memory (OCM) · JTAG MMU Instruction Shadow TLB (4 Entry) Cache Units Data Shadow TLB (8 Entry) Fetch and 3-Element Fetch Decode Queue Logic D-Cache D-Cache Array Controller PLB Master Data OCM PowerPC 405xx Core block diagram Timers (FIT, PIT, Watchdog) Timers & Debug Unified TLB (64 Entry) Data Cache Unit 405 CPU Execute Unit (EXU) 32 x 32 GPR ALU MAC APU/FPU Debug Logic (4 IAC, 2 DAC, 2 DVC) JTAG Instruction Trace Specifications 405A3 405A3 405B3 405B3 405D4 405D4 Technology .25µm (.18µm Leff) CMOS SA-12E SA-12E .25µm (.18µm Leff) CMOS SA-12E SA-12E .18µm (.11µm L eff) CMOS SA-27E SA-27E CPU Core Size (est.) 2mm2 2mm2 1.4mm2 Frequency (MHz) 0 to 200WC1 200WC1 0 to 300TC1 300TC1 0 to 200WC1 200WC1 0 to 300TC1 300TC1 0 to 266WC2 266WC2 0 to 390TC2 390TC2 Performance (Dhrystone 2.1 MIPS) 282 @ 200MHz 423 @ 300MHz 282 @ 200MHz 423 @ 300MHz 375 @ 266MHz 550 @ 390MHz Power Dissipation (estimated, typical) 1.0W @200MHz 650mW @200MHz 500mW @266MHz Voltage 2.5V +/- 5% 2.5V +/- 5% 1.8V +/- 5% I- Cache D-Cache 32K 32K 16K 8K 16K 16K MMU Yes Yes Yes Timers Yes Yes Yes JTAG Yes Yes Yes Trace FIFO Yes Yes Yes WC1 Worst case conditions (2.3V, 85° C, slow silicon) WC2 TC1 Worst case conditions (1.65V, 85° C, slow silicon) Typical conditions (2.5V, 55° C, nominal silicon) TC2 PowerPC 405 Core Integration Through the IBM CoreConnect TM bus architecture, PowerPC 405 cores integrate on-chip with and other reusable peripheral and application-specific cores, such as the controllers and CodePack TM code decompression shown in the example below. High speed, high bandwidth peripherals, like the 405 core, directly attach to the processor local bus (PLB). Less performance-critical cores attach to the on-chip peripheral bus (OPB). Typical conditions (1.8V 55° C, nominal silicon) , The PowerPC 405 cores and the CoreConnect bus are available through the Blue Logic core library to help reduce time to market of SOC designs. For more information on IBM Microelectronics core offerings, view the Blue Logic core library at www.chips.ibm.com/products/asics/ or contact your local IBM Microelectronics sales office. All Rights Reserved Printed in the United States of America 5-00 The following are trademarks of International Business Machines Corporation in the United States, or other countries, or both: IBM IBM Logo Blue Logic CodePack PowerPC CoreConnect PowerPC Logo PowerPC Embedded Tools Other company product and service names may , be trademarks or service marks of others. All information contained in this document is subject to change without notice. The products described in this document are NOT intended for use in implantation or other life support applications where malfunction may result in injury or death to persons.The information contained in this document does not affect or change IBM's product specifications or warranties. Nothing in this document shall operate as an express or implied license or indemnity under the intellectual property rights of IBM or third parties. All information contained in this document was obtained in specific environments, and is presented as an illustration. The results obtained in other operating environments may vary . THE INFORMATION CONTAINED IN THIS DOCUMENT IS PROVIDED ON AN "AS IS" BASIS. In no event will IBM be liable for damages arising directly or indirectly from any use of the information contained in this document. IBM Microelectronics Division 1580 Route 52, Bldg. 504 Hopewell Junction, NY 12533-6351 The IBM home page can be found at ibm.com. The IBM Microelectronics Division home page can be found at www.chips.ibm.com. External External Peripheral Bus Master Controller Controller SDRAM Controller © Copyright International Business Machines Corporation 1999, 2000 PCI Interface IIC TM Arbiter Processor Local Bus (PLB) 64-Bit OPB Bridge 16K I-Cache 8K D-Cache MMU Trace Timers PowerPC 405B3 405B3 Core Interrupt Controller DMA Controller MAL 32-Bit SRAM Control 405 CPU JTAG 4KB SRAM On-Chip Peripheral Bus (OPB) IBM CodePack UART UART GPIO 10/100 Ethernet MAC Arbiter IBM PowerPC 405GP 405GP embedded processor showing integration of 405B3 405B3 core *07GK21026901 07GK21026901* GK21-0269-01 GK21-0269-01