KAC-9647 AN450 KAC9647 - Datasheet Archive

 

DEVICE PERFORMANCE SPECIFICATION KODAK KAC-9647 CMOS IMAGE SENSOR 648 (H) X 488 (V) VGA 68 fps Color CIS September 2004 Revision

 

IMAGE SENSOR SOLUTIONS DEVICE PERFORMANCE SPECIFICATION KODAK KAC-9647 KAC-9647 CMOS IMAGE SENSOR 648 (H) X 488 (V) VGA 68 fps Color CIS September 2004 Revision 1.92 www.kodak.com/go/imagers 585-722-4385 1 Email:imagers@kodak.com Revision 1.92, Sept 2004 IMAGE SENSOR SOLUTIONS General Description Applications The KAC-9647 KAC-9647 is a high performance, low power, 1/4" VGA CMOS Active Pixel Sensor capable of capturing color, still or motion images and converting them to a digital data stream. · · · · Great image quality is achieved by integrating a high performance analog signal processor comprising of a high speed 10 bit A/D convertor, fixed pattern noise elimination circuits and separate color gain amplifiers. The offset and black level can be automatically adjusted on chip using a full loop black level compensation circuit. Dual Mode Camera Digital Still Camera Security Camera Machine Vision Key Specifications Optical Format 1/4" 6.0µm x 6.0µm 8 & 10 Bit Digital Frame Rate 68 frames per second Dynamic Range 57 dB Electronic Shutter Rolling Reset FPN 0.2% PRNU 1.7% Sensitivity 2.5 volts/lux*s Fill Factor 49% Color Mosaic Bayer pattern 32 LCC Single Supply 3.0V +/-10% Power Consumption 130mW Operating Temp · I2C compatible serial control interface · Power on reset & power down mode Total: 2.93mm x 4.03mm Active: 2.93mm x 3.89mm Package · Master and slave mode operation · Progressive scan read out with horizontal and vertical flip · Programmable Exposure: - Master clock divider - Inter row delay - Inter frame delay - Partial frame integration · Four channels of digitally programmable analog gain · Full automatic servo loop for black level & offset adjustment on each gain channel · Horizontal & vertical sub-sampling (2:1 & 4:2) · Windowing · Programmable pixel clock, inter-frame and inter-line delays Effective Image Area Video Outputs Features Total: 488 x 672 Active: 488(V) x 648(H) Pixel Size Furthermore, a programmable smart timing and control circuit allowing the user maximum flexibility in adjusting integration time, active window size, gain, frame rate. Various control, timing and power modes are also provided. Array Format -10oC to 50oC System Block Diagram Digital Imaging Processing Storage Display Interface Optics Sensor www.kodak.com/go/imagers 585-722-4385 DVP Email:imagers@kodak.com KAC-9647 KAC-9647 Color CMOS Image Sensor VGA 68 FPS KAC-9647 KAC-9647 Color CMOS Image Sensor VGA 68 FPS Overall Chip Block Diagram sclk sda I2C Compatible Serial I/F Register Bank pwd mclk Power Control POR clk gen Row Address Decoder snapshot Master Sensor Controller extsync ch0 +/- ch1 +/- ch2 +/- MUX 10 bit A/D ch3 Digital Video Framer Horizontal Register +/- Column CDS resetb Black Level Compensation APS Array sadr d[9:0] pclk hsync vsync Figure 1. Chip Block Diagram sclk sda scanmode vdd_od1 vss_od1 vdd_pix resetb atest Connection Diagram 19 18 17 16 15 14 13 12 vcp2 20 11 vss_ana vcp1 21 10 vdd_ana hsync 22 9 vref_p 8 vref_n KAC-9647 KAC-9647 vsync 23 pclk 24 7 vss_adc mclk 25 6 vdd_adc vss_dig 26 5 d9 vdd_dig 27 4 d8 28 29 30 31 32 1 2 3 d1 d2 d3 d4 d5 d6 d7 32 PIN LCC d0 KAC-9647 KAC-9647 IMAGE SENSOR SOLUTIONS Figure 2. Chip Pin Diagram www.kodak.com/go/imagers 585-722-4385 3 Email:imagers@kodak.com IMAGE SENSOR SOLUTIONS KAC-9647 KAC-9647 Typical Application Circuit System Control 0.1µF sda 18 sclk 6 vdd_adc 19 resetb 3.0V 13 mclk 25 Serial Control Bus 7 vss_adc vdd_ana 10 3.0V 0.1µF 16 15 vss_ana 0.1µF 11 vdd_od1 vss_od1 vdd_dig KAC-9647 KAC-9647 3.0V 3.0V vss_dig 14 vdd_pix 27 3.0V 0.1µF 26 0.1µF vcp1 21 56pF 9 vref_p vcp2 20 10µF 46k 1% 0.1µF 8 vref_n 10µF 22 23 24 28 29 30 31 32 1 2 3 12 NC scanmode 17 d8 d9 d7 d6 d5 d4 d3 d2 d1 d0 pclk vsync hsync atest 4 5 Digital Video Bus Figure 3. Typical Application Diagram Scan Read Out Direction vertical scan (0,0) (0,0) digital out (0,0) horizontal scan lens pin 1 CMOS Image Sensor Figure 4. Scan directions and position of origin in imaging system www.kodak.com/go/imagers 585-722-4385 4 Email:imagers@kodak.com KAC-9647 KAC-9647 IMAGE SENSOR SOLUTIONS Pin Descriptions Pin Name I/O Typ Description 1 d5 O D Digital output. Bit 5 of the digital video output bus. This output can be tri-stated 2 d6 O D Digital output. Bit 6 of the digital video output bus. This output can be tri-stated 3 d7 O D Digital output. Bit 7 of the digital video output bus. This output can be tri-stated 4 d8 O D Digital output. Bit 8 of the digital video output bus. This output can be tri-stated 5 d9 O D Digital output. Bit 9 of the digital video output bus. This output can be tri-stated 6 vdd_adc I P 3.0 volt supply for the 10 bit A/D converter. 7 vss_adc I P 0 volt supply for the 10 bit A/D converter. 8 vref_n I A A/D reference resistor ladder low voltage. This is the bottom of the ADC reference ladder and is normally bypassed with a 10 µF capacitor. 9 vref_p I A A/D reference resistor ladder high voltage. This is the top of the ADC reference ladder and is normally bypassed with a 10 µF capacitor. 10 vdd_ana I P 3.0 volt supply for analog circuits. 11 vss_ana I P 0 volt supply for analog circuits. 12 atest O A Analog test pin. This pin is used for production testing and should not be connected. 13 resetb I D Digital input with pull up resistor. When forced to a logic 0 the sensor is reset to its default power up state. 14 vdd_pix I P 3.0 volt supply for the pixel array. This pin should be connected to the 3.0v analog supply and bypassed to ground with a 10uF capacitor. 15 vss_od1 I P 0 volt supply for the digital IO buffers 16 vdd_od1 I P 3.0 volt supply for the digital IO buffers. 17 scanmode I D Digital production test pin. This pin should be tied to ground 18 sda IO D I2C compatible serial interface data bus. 19 sclk I D I2C compatible serial interface clock. 20 vcp2 O A Analog output, reset charge pump 2 output, connect to vss_ana via a 0.1µf capacitor. Voltage on this pin should be 5 volt. 21 vcp1 O A Analog output, reset charge pump 1 output, connect to vss_ana via a 56pf capacitor. Voltage on this pin should be 3.6 volt. D Digital Bidirectional. This is a dual mode pin. When the sensor's digital video port is configured to be a master, this pin is an output and is the horizontal synchronization pulse. When the sensor's digital video port is configured to be a slave, (the default), this pin is an input and is the row trigger. D Digital Bidirectional. This is a dual mode pin. When the sensor's digital video port is configured to be a master, this pin is an output and is the vertical synchronization pulse. When the sensor's digital video port is configured to be a slave, (the default), this pin is an input and is the frame trigger. 22 23 hsync vsync IO IO www.kodak.com/go/imagers 585-722-4385 5 Email:imagers@kodak.com IMAGE SENSOR SOLUTIONS KAC-9647 KAC-9647 Pin Descriptions (continued) Pin Name I/O Typ Description 24 pclk O D Digital output. The pixel clock. 25 mclk I D Digital input. The sensor's master clock input. 26 vss_dig I P 0 volt power supply for the digital circuits. 27 vdd_dig I P 3.0 volt power supply for the digital circuits. 29 d1 O D Digital output. Bit 1 of the digital video output bus. This output can be tri-stated. 30 d2 O D Digital output. Bit 2 of the digital video output bus. This output can be tri-stated 31 d3 O D Digital output. Bit 3 of the digital video output bus. This output can be tri-stated 32 d4 O D Digital output. Bit 4 of the digital video output bus.This output can be tri-stated Legend: (I=Input), (O=Output), (IO=Bi-directional), (P=Power), (D=Digital), (A=Analog). www.kodak.com/go/imagers 585-722-4385 6 Email:imagers@kodak.com KAC-9647 KAC-9647 IMAGE SENSOR SOLUTIONS Absolute Maximum Ratings (Notes 1 & 2) Operating Ratings (Notes 1 & 2) Any Positive Supply Voltage Voltage On Any Input or Output Pin Input Current at any pin (Note 3) Package Input Current (Note 3 Package Dissipation at TA = 25°C ESD Susceptibility (Note 5) Human Body Model Machine Model Peak Soldering Temperature (Note 6) Storage Temperature Operating Temperature Range All VDD Supply Voltages 4.2V -0.3V to 4.2V ±35mA ±50mA see Note 4 -10°CT+50°C +2.7V to +3.3V 2000V 200V 235°C -40°C to 125°C DC and logic level specifications The following specifications apply for all VDD pins= +3.0V. Boldface limits apply for TA = TMIN to TMAX: all other limits TA = 25oC. Symbol Parameter Conditions Min note 9 Typical note 8 Max note 9 Units sclk, sda Digital Input/Output Characteristics VIH Logical "1" Input Voltage 0.7*vdd_od vdd_od+0.5 V VIL Logical "0" Input Voltage -0.5 0.3*vdd_od V VOL Logical "0" Output Voltage vdd_od = +2.7V, Iout=3.0mA 0.4 V Vhys Hysteresis (SCLK pin only) vdd_od > +2.0V Ileak Input Leakage Current Vin=vdd_od 0.05*vdd_od V µA 1 mclk, resetb, hsync, vsync Digital Input Characteristics VIH Logical "1" Input Voltage vdd_dig = +3.3V 2.0 V VIL Logical "0" Input Voltage vdd_dig = +2.7V IIH Logical "1" Input Current VIH = vdd_dig 1 nA IIL Logical "0" Input Current VIL = vss_dig -1 nA 0.8 V d0 - d9, pclk, hsync, vsync Digital Output Characteristics VOH Logical "1" Output Voltage vdd_od=2.7V, Iout=-1.6mA VOL Logical "0" Output Voltage vdd_od=2.7V, Iout =-1.6mA IOZ TRI-STATE Output Current VOUT = vss_od VOUT = vdd_od IOS 2.2 Output Short Circuit Current V 0.5 V -0.1 0.1 µA µA +/-17 mA @27MHz @12MHz 670 60 50 µA mA mA @27MHz @12MHz 0 28 13 µA mA mA Power Supply Characteristics IA Analog Supply Current Power down mode Operational mode ID Digital Supply Current Power down mode Operational mode Power Dissipation Specifications The following specifications apply for all VDD pins= +3.0V. Boldface limits apply for TA = TMIN to TMAX: all other limits TA = 25oC. Symbol Parameter Pdwn Power Down PWR Average Power Dissipation Conditions www.kodak.com/go/imagers 585-722-4385 Min note 9 Typical note 8 Max note 9 Units 2.0 264 189 @27 MHz @12MHz 7 mW mW mW Email:imagers@kodak.com IMAGE SENSOR SOLUTIONS The following specifications apply for all VDD pins= +3.0V. Boldface limits apply for TA = TMIN to TMAX: all other limits TA = 25oC Symbol Parameter Min (note 9) Conditions Gain Resolution Typical (note 8) Max (note 9) Units 7 Bits 0.125 dB Maximum Gain 16 dB Minimum Gain 0.0 dB Step Size (Gain / Resolution) AC Electrical Characteristics The following specifications apply for All VDD pins = +3.0V. Boldface limits apply for TA = TMIN to TMAX: all other limits TA = 25oC. Symbol Fmclk Parameter Conditions Input Clock Frequency Min note 9 Typical note 8 Units 27 12 Max note 9 MHz Tch Clock High Time @ CLKmax 16.0 ns Tcl Clock Low Time @ CLKmax 16.0 ns Clock Duty Cycle @ CLKmax 45/55 Trc, Tfc Clock Input Rise and Fall Time Internal System Clock Frequency 12 Treset Reset pulse width 1.0 Note 2: Note 3: Note 4: 55/45 3 Fhclk Note 1: 50/50 min/max ns 27 MHz µs Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions. All voltages are measured with respect to vss_dig = vss_ana = vss_adc = vss_od1 = vss_od2 = 0V, unless otherwise specified. When the voltage at any pin exceeds the power supplies (VIN < [vss_dig or vss_ana or vss_adc or vss_od1 or vss_od2] or VIN > [vdd_dig or vdd_ana or vdd_adc or vdd_od1 or vdd_od2]), the current at that pin should be limited to 25mA. The 50mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 25mA to two. The absolute maximum junction temperature (TJmax) for this device is 150oC. The maximum allowable power dissipation is dictated by TJmax, the junction-to-ambient thermal resistance (JA), and the ambient temperature (TA), and can be calculated using the formula PDMAX = (TJmax - TA)/JA. In the 48-pin LCC, JA is 69oC/W, so PDMAX = 1,811mW at 25oC Note 5: Note 6: Note 7: Note 8: Note 9: and 1,449 mW at the maximum operating ambient temperature of 50oC. Note that the power dissipation of this device under normal operation will typically be about 215 mW. The values for maximum power dissipation listed above will be reached only when the KAC-9647 KAC-9647 is operated in a severe fault condition. Human body model is 100pF capacitor discharged through a 1.5k resistor. Machine model is 220pF discharged through ZERO Ohms. See AN450 AN450, "Surface Mounting Methods and Their Effect on Product Reliability", or the section entitled "Surface Mount" found in any post 1986 National Semiconductor Linear Data Book, for other methods of soldering surface mount devices. The analog inputs are protected as shown below. Input voltage magnitude up to 500mV beyond the supply rails will not damage this device. However, input errors will be generated If the input goes above AV+ and below AGND. Typical figures are at TJ = 25oC, and represent most likely parametric norms Test limits are guaranteed to AOQL (Average Outgoing Quality Level). www.kodak.com/go/imagers 585-722-4385 8 Email:imagers@kodak.com KAC-9647 KAC-9647 Video Amplifier Specifications KAC-9647 KAC-9647 IMAGE SENSOR SOLUTIONS CMOS Active Pixel Array Specifications Parameter Value Units Number of pixels (row, column) Total Active 488 x 672 488 x 648 pixels pixels Array size (x,y Dimensions) Total Active 2.93 x 4.03 2.93 x 3.89 mm mm Pixel Pitch 6.0 µ Fill Factor without micro-lens 49 % Image Sensor Specifications The following specifications apply for All VDD pins = +3.3V, TA = 25oC, Illumination Color Temperature = 2850oK, IR cutoff filter at 700nm, mclk = 27MHz, frame rate = 15Hz, unity video gain. Parameter Min note 9 Description Typical note 8 Max note 9 Units Optical Sensitivity1 red green blue 2.50 1.18 0.59 Measured at the input of the A/D Volt/lux.s Dark Signal 0.15 Volt/s Read Noise The RMS temporal noise of the pixel output signal in the dark averaged over all pixels in the array. 1.5 LSBs Dynamic Range The ratio of the saturation pixel output signal and the read noise expressed in dB. 57 dB FPN Fixed Pattern Noise: the RMS spatial noise in the dark excluding the effect of read noise. 0.2 % PRNU red green blue 1 The pixel output signal due to dark current. Photo Response Non Uniformity: the RMS variation of pixel sensitivities as a percentage of the average optical sensitivity. 0.5 1.7 2.5 % 1024 The optical sensitivity at the A/D output, in units of LSBs/lux.s, can be calculated using: - Optical Sensitivity vrefp-vrefn www.kodak.com/go/imagers 585-722-4385 9 Email:imagers@kodak.com IMAGE SENSOR SOLUTIONS KAC-9647 KAC-9647 Sensor Response Curves 500 450 red Sensitivity [VW-1m2s-1] 400 green 350 300 blue 250 200 150 100 50 0 400 500 600 700 800 900 WaveLength [nm] Figure 5. Spectral Response Curve www.kodak.com/go/imagers 585-722-4385 10 Email:imagers@kodak.com Functional Description After color gain adjustment the analog value of each pixel is converted to a 10 bit digital data as shown in figure 8. 648 columns, 488 rows color (Bayer pattern) active pixels 24 columns black pixels ch0 +/- Digital pixel values 1.1 Light Capture and Conversion The KAC-9647 KAC-9647 contains a CMOS active pixel array consisting of 488 rows by 648 columns. 24 columns of optically shielded (black) pixels are provided to the right of the array as shown in Figure 6. Only the middle 8 black columns are used for black level compensation. The black pixels are physically located at the end of each row but are read out first. ch1 +/- MUX +/- 10 Bit A/D ch2 +/- ch3 I2C Compatible Serial I/F OVERVIEW Analog pixel values 1.0 MUX Auto Black Level Compensation Target & Rate Registers Manual Offset Registers Figure 8. Analog Signal Conditioning & Conversion to Digital Figure 6. CMOS APS region of the KAC-9647 KAC-9647 The color filters are Bayer pattern coded starting at row 0 and column 0. The color coding is green, red, green, red until the column 647 of row 0, then blue, green, blue, green until column 647 of row 1 and so on (see Figure ). The black level of each color together with the full analog signal path offset is automatically compensated as shown in figure 8. This can be manually overridden. do[9:0] a b c d e f g h i j pclk Digital Framer At the beginning of a given integration time the on-board timing and control circuit will reset every pixel in the array one row at a time as shown in Figure 7. Note that all pixels in the same row are simultaneously reset, but not all pixels in the array. Line Address KAC-9647 KAC-9647 IMAGE SENSOR SOLUTIONS hsync vsync k l m n o p q r 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Figure 9. Digital Pixel Processing. Finally the pixel data is framed and output on the digital video bus as shown in figure 9. 1.2 Program and Control Interfaces The programming, control and status monitoring of the KAC9647 KAC9647 is achieved through a two wire I2C compatible serial bus. A device address pin is provided allowing two different device addresses to be selected for the serial interface as shown in Figure 10. Analog Data Out CDS/Shift Register Figure 7. CMOS APS Row and Column addressing scheme Register Bank At the end of the integration time, the timing and control circuit will address each row and simultaneously transfer the integrated value of the pixel to a correlated double sampling circuit and then to a shift register as shown in Figure 7. I2C Compatible Serial I/F sda sclk Figure 10. Control Interface to the KAC-9647 KAC-9647. Once the correlated double sampled signals have been loaded into the shift register, the timing and control circuit will shift them out one pixel at a time. The analog pixel signals are then separated and fed into four channels analog gain channels as shown in figure 8. Each gain channel can be digitally programmed allowing signal level of each color in the Bayer pattern to be seperately adjusted. www.kodak.com/go/imagers 585-722-4385 11 Email:imagers@kodak.com IMAGE SENSOR SOLUTIONS 2.0 DOUBLE BUFFERED REGISTERS 4.0 All programmable registers that effect the frame rate and integration timing are double buffered; such that the new values only take effect at the start of the new frame. When writing to all split double buffered registers, e.g. ITIMEH and ITIMEL, the following procedure must be followed: - to change both the MSB and LSB, first write to the MSB register and then write to the LSB register, - to change only the MSB, first write to the MSB register and then write the unchanged value of the LSB to the LSB register, - to only change the LSB write to the LSB register. ARRAY READOUT The pixels in the array are read out in progressive scan. In progressive scan, every pixel in every row in the defined "Active Window" is consecutively read out, one pixel at a time. The first 8 pixels of every row are black unless masked out by setting the BlkPixelEn bit of the DVBUSCONFIG2 register to a logic 0. The scan direction can be programmed as follows: WINDOWING Four coordinates (start row address, start column address, end row address & end column address) need to be programmed to define the size and location of the "Active Window" to be read out (see Figure 11). column column end address start address WColEnd[10:2] WColStart[10:2] Active Window row end address WEndRow[10:2] 1 0 1 Reverse Horizontal Scan Direction 1 0 Reverse Vertical and Horizontal Scan Direction 0 0 4.1 Default Scan Direction The default scan direction is to consecutively read out, one pixel at a time, starting with the left most pixel in the top most row. Hence, for the example shown in Figure 12, the read out order will be a0,b0,.,r0 then a1,b1,.,r1 and so on until pixel r20 is read out. See figure 12. 4.3 Reverse Horizontal Scan Direction The horizontal scan direction can be reversed by setting the "HScanDir" bit in the HSCAN register to a logic 0, while setting the "VScanDir" bit in the VSCAN register to a logic 1. In this case for the example shown in Figure 12, the read out order will be r0,q0,.,a0 then r1,q1,.,a1 and so on until pixel a10 is read out. Active Pixel Array Figure 11. Windowing Notes: · By default the "Active Window" is set to 320 columns by 240 rows. To program a VGA window aligned to the optical center to the pixel array the following codes need to be written to the 4.4 Reversing The Horizontal & Vertical Scan Direction The horizontal scan direction can be reversed by setting both the "HScanDir" bit in the HSCAN and the "VScanDir" bit in the VSCAN register to a logic 0. In this case for the example shown in Figure 12, the read out order will be r10,q10,.,a10 then r9,q9,.,a9 and so on until pixel a0 is read out. windowing registers via the I2C interface WROWS 1 4.2 Reverse Vertical Scan Direction The vertical scan direction can be reversed by setting the "VScanDir" bit in the VSCAN register to a logic 0, while setting the HScanDir bit in the HSCAN register to a logic 1. In this case for the example shown in Figure 12, the read out order will be a10,b10,.,r10 then a9,b9,.,r9 and so on until pixel r0 is read out. row start address WStartRow[10:2] 19h HScanDir Default Scan Direction The integrated timing and control circuit allows any size window in any position within the active region of the array to be read out with a 4x4 pixel resolution. The window read out is called the "Active Window". VScanDir Reverse Vertical Scan Direction 3.0 Scan Direction 00h 1Ah WROWE 3Bh 1Bh WROWLSB 23h 1Ch WCOLS 00h 1Dh WCOLE 50h 1Eh WCOLLSB 23h Row/Vertical · The "Active Window" registers are double buffered. · The black pixels are read out at the beginning of each row even when not contained in the active window. The black pixel read out can be masked by setting the BlKPixelEn bit in the DVBUSCONFIG2 register to a logic 0. 0 1 2 3 4 5 6 7 8 9 10 Column/Horizontal a b c d e f g h i j k l mn o p q r Figure 12. Progressive Scan Read Out Mode www.kodak.com/go/imagers 585-722-4385 12 Email:imagers@kodak.com KAC-9647 KAC-9647 Functional Description (continued) Functional Description (continued) 5.0 SUB-SAMPLING MODES 5.1 2:1 Sub-Sampling The timing and control circuit can be programmed to sub-sample pixels in the "Active Window" vertically, horizontally or both, with an aspect ratio of 2:1 as illustrated in figure 13. Register Bit VIDCONFIG Color VSCAN VSub HSCAN HSub Vertical 0 1 Horizontal 0 0 0 1 Register Bit VIDCONFIG Color 0 1 HSCAN HAvr 0 1 H1 + H2 a Column/Horizontal a b c d e f g h i j k l m n o p q r b c d e f g h i j H1 H2 H1 H2 H1 H2 H1 H2 H1 H2 H1 H2 H1 H2 H1 H2 H1 H2 H1 H2 H1 H2 H1 H2 H1 H2 H1 H2 2 H1 H2 H1 H2 1 0 1 2 3 4 5 6 7 8 9 Row/Vertical VSCAN VAvr When horizontal 2:1 subsampling with averaging is selected, neighboring pixels in the horizontal direction are combined as shown in figure 14. The value of the combined pixel is given by 1 Both 5.2 2:1 Sub-Sampling with Averaging The timing and control circuit can be programmed to average neighboring pixels in the analog domain before sub-sampling in the horizontal direction only as shown in the table below Horizontal 0 H1 H2 H1 H2 H1 H2 H1 H2 Figure 14. :2:1Horizontal Subsampling with Averaging a) Horizontal Sub-Sampling Row/Vertical Column/Horizontal a b c d e f g h i j k l m n o p q r 0 1 2 3 4 5 6 7 8 9 b) Vertical Sub-Sampling Column/Horizontal a b c d e f g h i j k l Row/Vertical KAC-9647 KAC-9647 IMAGE SENSOR SOLUTIONS l n o p q r 0 1 2 3 4 5 6 7 8 9 c) Horizontal & Vertical Sub-Sampling Not Read Out Green Pixel Red Pixel Blue Pixel Figure 13. Example of 2:1 Sub-sampling Note a: Note b: Note that the pixel read out will depend on the programmed scan order as described in section 4.0. For max FPN performance it is recommended to always switch on the averaging feature when subsampling (see next section). www.kodak.com/go/imagers 585-722-4385 13 Email:imagers@kodak.com IMAGE SENSOR SOLUTIONS 5.3 4:2 Sub-Sampling The timing and control circuit can be programmed to sub-sample pixels in the display window vertically, horizontally or both, with an aspect ratio of 4:2 as illustrated in figure 15 Register Bit VIDCONFIG Color VSCAN VSub HSCAN HSub Vertical 1 1 1 0 1 Both 1 1 Register Bit 0 Horizontal 5.4 4:2 Sub-Sampling with Averaging The timing and control circuit can be programmed to average neighboring pixels of the same color in the analog domain before subsampling. This can be done in the horizontal direction only as shown in the table below: 1 VIDCONFIG Color Horizontal VSCAN VAvr 1 0 HSCAN HAvr 1 When horizontal 2:1 subsampling with averaging is selected, neighboring pixels in the horizontal direction are combined as shown in figure 16. The value of the combined pixel is given by H1 + H2 Row/Vertical Column/Horizontal a b c d e f g h i j k l m n o p q r a 0 1 2 3 4 5 6 7 8 9 b c d e f g h H2 H2 H2 H2 H1 H1 H2 H2 H1 H1 H2 H2 H1 H1 H2 H2 H1 H1 H2 H2 2 H1 H1 H1 H1 1 H1 H1 H2 H2 H1 H1 H2 H2 Figure 16. :4:2Horizontal Subsampling with Averaging Row/Vertical a) Horizontal Sub-sampling Column/Horizontal a b c d e f g h i j k l m n o p q r 0 1 2 3 4 5 6 7 8 9 b) Vertical Sub-sampling Row/Vertical a Column/Horizontal b c d e f g h i j k l mn o p q r 0 1 2 3 4 5 6 7 8 9 c) Horizontal & Vertical Sub-sampling Green Pixel Red Pixel Blue Pixel Not Read Out Figure 15. Example 4:2 Sub-sampling Note a: Note b: Note that the pixel read out will depend on the programmed scan order as described in section 4.0. For max FPN performance it is recommended to always switch on the averaging feature when subsampling (see next section). www.kodak.com/go/imagers 585-722-4385 14 Email:imagers@kodak.com KAC-9647 KAC-9647 Functional Description (continued) Functional Description (continued) 6.0 FRAME RATE & EXPOSURE CONTROL 6.1 Introduction The frame time is defined as the time it takes to reset every pixel in the array, integrate the incident light, convert it to digital data and present it on the digital video port. This is not a concurrent process and is characterized in a series of events each requiring a certain amount of time as shown in Figure 17. Start Frame delay time 6.2 Analog Gain Four channels of gain are provided allowing the gain of each color to be separately adjusted before the analog to digital conversion. The mapping of each gain channel to a pixel in a quadrant is programmable, allowing flexibility in the selection of the Color Filter Array (CFA) pattern. The color mapping is programmed using the CFAMAP register as shown in figure 18. For the example shown in figure 18 pixel "a1" can be routed to color gain channel 0 (ch0) by setting ColorMap0 in the CFAMAP to 00. Pixel "a1" is to be routed to color gain channel 1 (ch1) by setting ColorMap0 in the CFAMAP register should be set to 01. ch0 Row address = 0 ch1 Row delay time MUX ch2 Transfer all pixels to CDS Reset all pixels in row ch3 Row Time KAC-9647 KAC-9647 IMAGE SENSOR SOLUTIONS a ColorMap0 Row address + 1 Last row? ColorMap ColorAmp 00 ch0 01 ch1 10 ch2 11 ch3 ColorMap ColorAmp 00 ch0 01 ch1 10 ch2 11 ch3 Red 1 ColorMap3 ColorMap ColorAmp 00 ch0 01 ch1 10 ch2 11 ch3 ColorMap ColorAmp 00 ch0 01 ch1 10 ch2 11 ch3 Blue 1 1 ColorMap1 Green 1 ColorMap2 Shift all pixels out of row Yes Green 2 No 2 Figure 17. Frame Readout Flow Diagram The following factors effect frame rate, exposure & signal level, the: · · · · · b Pixel Quadrant frequency of Hclk size of the "Active Window" subsampling mode programmed row delay programmed frame delay. Figure 18. Color To Gain Channel Mapping The KAC-9647 KAC-9647 is supplied with a Bayer patterned CFA upon reset the color mapping is set as follows The following factor effects signal level only. Pixel Color This section describes how to program the frame rate and exposure time. ch1 Blue ch2 Green 2 · integration time ch0 Red The following factor effects exposure & signal level: Gain Channel Green 1 · analog gain ch3 Each gain channel can provide up to 16dB of gain programmable in 128 steps of 0.125dB, (see registers PGA0, PGA1, PGA2 & PGA3). www.kodak.com/go/imagers 585-722-4385 15 Email:imagers@kodak.com IMAGE SENSOR SOLUTIONS Max. Gain = 16.0 dB PGA Gain (dB) 15 10 5 0 0 16 32 48 64 80 96 112 128 PGA Gain Code Figure 19. Gain Plot 6.3 Clock Generation The KAC-9647 KAC-9647 contains a clock generation module (figure 20) that will create three clocks as follows: Hclk, the horizontal clock. This is an internal system clock and can be programmed to be the input clock (mclk) or mclk divided by 2,4 or 6. All exposure times are in multiples of this clock. ÷ HclkGen Hclk data ready mode PixClkMode To set the frequency of this clock the HclkGen bits in the VCLKGEN register should be programed. pclk mclk mux PixClkPol the pixel clock. This is the external pixel clock that appears at the digital video port. By default pclk is free running and it's frequency is always equal to Hclk (see figure 20). pclk pclk can be programmed to the following modes: · Data Ready Mode, where pclk clock will go active every time a valid pixel appears on the data out bus by setting the PixClkMode bit of the DVBUSCONFIG1 to a logic 1. · Reverse Polarity Mode, where the polarity of pclk is negated by programming the PixClkPol bit in the DVBUSCONFIG2 register. www.kodak.com/go/imagers 585-722-4385 Figure 20. Clock Generation Module 16 Email:imagers@kodak.com KAC-9647 KAC-9647 KAC-9647 KAC-9647 Functional Description (continued) KAC-9647 KAC-9647 IMAGE SENSOR SOLUTIONS Functional Description (continued) 6.4 Full Frame Integration Full frame integration is when each pixel in the array integrates light incident on it for the duration of a frame (see Figure 21). The number of pixels processed per row is given by: Npix = WEndCol - WStartCol + 1 Where: WStartRow is the "Active Window" row end address as programmed in registers WROWS and WROWLSB. MVfactor is 1 when vertical subsampling is disabled and 0.5 when vertical subsampling is enabled. The number of Hclk clocks required to process a full frame is given by: FNHclk = [Nrows + Fdelay] * RNHclk WEndCol is the "Active Window" column start address as programmed in registers WCOLE and WCOLLSB. Where: WStartCol is the "Active Window" column end address as programmed in registers WCOLS and WCOLLSB. The number of Hclk clock cycles required to process & shift out one row of pixels is given by: RNHclk = Ropcycle + RItime + (Npix*MHfactor) + Rdelay Where: Ropcycle is a fixed integer value of 137 representing the Row Operation Cycle Time in multiples of Hclk clock cycles. It is the time required to carry out all fixed row operations outlined in Figure 17. RItime When partial frame integration is enabled, (PrtFrmEn bit in the ITIMECONFIG register is set to a logic 1), RItime is a fixed integer of 37. When Partial frame integration is disabled, (PrtFrmEn bit in the ITIMECONFIG register is set to a logic 0), RItime is a fixed integer of 0. Is the number of pixels processed in a row. Npix MHfactor Is 1 when horizontal subsampling is disabled and 0.5 when horizontal subsampling is enabled. Rdelay a programmable value between 0 & 8191 representing the Row Delay Time in multiples of Hclk. This parameter allows the Row Operation Cycle time to be extended. The Rdelay value is programmed in the RDELAYH and RDELAYL registers. The number of rows in the active window is given by: Nrows = (WEndRow - WStartRow + 1) * MVfactor Nrows Fdelay is the number of rows in the "Active Window". a programmable value between 0 & 32766 representing the Inter Frame Delay in multiples of RNHclk. This parameter allows the frame time to be extended. (See the Frame Delay High and Frame Delay Low registers). The Fdelay value is programmed in the FDELAYH and FDELAYL registers. The frame rate is given by: Hclk Frame Rate = FN Hclk 6.5 Partial Frame Integration In some cases it is desirable to reduce the time during which the pixels in the array are allowed to integrate incident light without changing the frame rate. This is known as Partial Frame Integration and can be achieved by resetting pixels in a given row ahead of the row being selected for readout as shown in Figure 21. The number of Hclk clocks required to process a partial frame is given by: FPHclk = RNHclk * Itime Where: RNHclk Itime is the number of Hclk clock cycles required to process & shift out one row of pixels. a programmable value between 0 & 32767 representing the number of rows ahead of the current row to be reset. This value must not be larger than the number of active rows. The Itime value is programmed in the ITIMEH and ITIMEL registers. Note: Where: . Upon system reset the partial frame integration is automatically enabled. It can be disabled by setting the PrtFrmEn bit in the WEndRow ITIMECONFIG register to a logic 0 or by programming 0. is the "Active Window" row start address as programmed in registers WROWE and WROWLSB. Full Integration Time Partial Integration Time Row n Frame Delay Row 0 Row 1 Row 2 Row x Programmable Row Delay Row x+ Row n Frame Delay Row 0 Row CDS, Reset Row x & Shift Full Frame integration Programmable Row Delay Row CDS, Reset Row x+ & Shift Partial Frame Integration Figure 21. Partial and Full Frame Integration www.kodak.com/go/imagers 585-722-4385 17 Email:imagers@kodak.com IMAGE SENSOR SOLUTIONS 7.0 BLACK LEVEL & OFFSET ADJUSTMENT 8.0 The KAC-9647 KAC-9647 allows for both fine and coarse black level adjustment. Coarse adjustment is made using the PIXELOFFSET register and only needs to be done once at power up. Fine offset adjustment is done on a row basis and can be accomplished either atomically using the on chip black level compensation circuit or manually by disabling the on chip black level compensation circuit. 7.1 Coarse Black Level and Offset Adjustment To ensure maximum performance of the CMOS image sensor, the natural offset of the pixel array needs to be minimized. Coarse adjustment is made using the PIXELOFFSET register and only needs to be done once at power up. This procedure is explained in detail in KAC-9647 KAC-9647 Application Note 4. 7.2 Manual Black Level and Offset Adjustment Each offset channel can provide up to 255 levels of black level and offset adjustment. To manually adjust the black level and offset the BlkLevEn bit in the BLKLEVCONFIG register should be set to a logic 1. Eight bit offset values can then be programmed to registers OFFSET0, OFFSET1, OFFSET2 & OFFSET3. 7.3 Auto Black Level and Offset Adjustment Automatic black level and offset adjustment mode is enabled by setting the BlkLevEn bit in the BLKLEVCONFIG register to a logic 0. BlkRate 8 bit DAC SYSTEM MANAGMENT 8.1 System Reset Upon power up an on-chip power on reset block will ensure that the sensor is initialized to its reset state. After power up the sensor can be reset by asserting a logic 0 on the resetb pin or by writing to the SenReset bin in the PWD&RESET register. Furthermore, all state machines contained in the sensors integrated timing and control block can be reset by writing to the RstzSoft bit in the OPCTRL register. 8.2 Power Up and Down The KAC-9647 KAC-9647 is equipped with an on-board power management system allowing the analog and digital circuitry to be switched off (power down) and on (power up) at any time. The sensor can be put into power down mode by asserting a logic one on the pdwn pin or by writing to the PwDn bit in the PWD&RST register. To power up the sensor a logic zero can be asserted on the pdwn pin or by writing to the PwDn bit in the PWD&RST register. To ensure proper sensor operation the reference ladders must be intitialized upon power up of the sensor. To switch on the sensor's reference resistors, the following sequence of codes should be written to the sensor via the I2C compatible interface at power up. This must be done for the sensor to operate properly after reset or when the sensor is powered up. BlkTraget Comp cmpl Level Calc Address (Hex) + CHx ADC 10 Output Data 01 POWCTRL all CHx Pixels Data (Hex) INITREG2 Black Pixel Acquisition 81 Figure 22: Digital Black Level & Offset Adjustment Loop Figure 22 illustrates the automatic black level and offset compensation circuit contained within the sensor. For every row, the digitized values of the middle 8 black pixels are acquired and fed to the compensation level calculator circuit. This circuit is a digital first order exponential averaging filter. It calculates the compensation level (cmpl) that is required to ensure that for pixels that are optically black, the black level at the output of the ADC is equal to the desired black level. The desired black level (ClkTarget) can be programmed in the BLKTARGET register. The black level control loop not only controls the black level of the pixels in the sensor array, but also controls the offset of the PGAs and A/D in the system. Because there are four channels, which can be operating at different gains and with different offsets, four different compensation levels are calculated, one for each channel. The convergence rate of the cancellation loop can be set by programming the BlkRate parameter located in the BLKLEVCONFIG register. Small values of the BlkRate parameter ensure a fast convergence. High values of the BlkRate parameter reduce the noise in the calculated compensation level. The optimal setting of the BlkRate parameter is the result of a compromise between convergence speed after power up and image quality. www.kodak.com/go/imagers 585-722-4385 18 Email:imagers@kodak.com KAC-9647 KAC-9647 Functional Description (continued) IMAGE SENSOR SOLUTIONS Functional Description 9.0 SERIAL BUS The serial bus interface consists of the sda (serial data) and sclk (serial clock) pins. The KAC-9647 KAC-9647 can operate only as a slave. 9.4 Data Valid The master must ensure that data is stable during the logic 1 state of the sclk pin. All transitions on the sda pin can onlyoccur when the logic level on the sclk pin is "0" as shown in Figure 25 The sclk pin is an input, it only controls the serial interface, all other clock functions within KAC-9647 KAC-9647 use the master clock pin, mclk. Mclk must be running at least 4 times faster than sclk to write to the serial bus. 9.1 Start/Stop Conditions The serial bus will recognize a logic 1 to logic 0 transition on the sda pin while the sclk pin is at logic 1 as the start condition. A logic 0 to logic 1 transition on the sda pin while the sclk pin is at logic 1 is interrupted as the stop condition as shown in Figure 23. sda sclk S P stop condition start condition Figure 23. Start/Stop Conditions 9.2 Device Address The Device Address can be changed by writing to the I2cDevAddr parameter in the I2CMODE Register. 9.3 Acknowledgment The KAC-9647 KAC-9647 will hold the value of the sda pin to a logic 0 during the logic 1 state of the Acknowledge clock pulse on sclk as shown in Figure 24. sda from master MSB ACK sda from sensor sclk S ACK 1 7 2 8 START 9 Clock pulse for ACK Figure 24. Acknowledge sda sclk data line stable; data valid data line stable; data valid change of data allowed Figure 25. Data Validity 9.5 Byte Format Every byte consists of 8 bits. Each byte transferred on the bus must be followed by an Acknowledge. The most significant bit of the byte is should always be transmitted first. See Figure 26. 9.6 Write Operation A write operation is initiated by the master with a Start Condition followed by the sensor's Device Address and Write bit. When the master receives an Acknowledge from the sensor it can transmit an 8-bit internal register address. The sensor will respond with a second Acknowledge signaling the master to transmit 8 write data bits. A third Acknowledge is issued by the sensor when the data has been successfully received. The write operation is completed when the master asserts a Stop Condition or a second Start Condition. See Figure 27. 9.7 Read Operation A read operation is initiated by the master with a Start Condition followed by the sensor's Device Address and Write bit. When the master receives an Acknowledge from the sensor it can transmit the internal Register Address byte. The sensor will respond with a second Acknowledge. The master must then issue a new Start Condition followed by the sensor's Device Address and read bit. The sensor will respond with an Acknowledged followed by the Read Data byte. The read operation is completed when the master asserts a Not Acknowledge followed by Stop Condition or a second Start Condition. See Figure 28. 9.8 Advanced Write Mode Several addresses can be written to without the need to re-start by setting the AdvWr bit in the I2CMODE register to a logic 1. MSB sda ack signal from receiver ack signal from receiver byte complete 1 sclk 7 2 1 9 8 ACK clock line held low S 2 8 9 ACK P Figure 26. Serial Bus Byte Format Device Address S W A Register Address A Data Byte A P bold sensor action Figure 27. Serial Bus Write Operation S Device Address W A Register Address A S Device Address R A Data Byte _ A P bold sensor action Figure 28. Serial Bus Read Operation www.kodak.com/go/imagers 585-722-4385 19 Email:imagers@kodak.com KAC-9647 KAC-9647 IMAGE SENSOR SOLUTIONS Functional Description (continued) 10.0 DIGITAL VIDEO PORT Synchronisation Signals in Master Mode The captured image is placed onto a flexible 10-bit digital port as shown in Figure 9. The digital video port consists of a programmable 10-bit digital Data Out Bus (d[9:0]) and three programmable synchronisation signals (hsync, vsync, pclk). In master mode the integrated timing and control block controls the flow of data onto the 12-bit digital port, three synchronisation outputs are provided: By default the synchronisation signals are configured to operate in "slave" mode. They can be programmed to operate in "master" mode. The following sections are a detailed description of the timing and programming modes of digital video port. The 10-bit digital video out bus can be tri-stated by asserting a logic 0 on the oe pin or by writing a logic 1 to the TriState bit in the DVBUSCONFIG3 register. In addition to this, the 10-bit digital video bus can be switch off to a logic 0 by writing a logic 0 to the VBusEn bit of the DVBUSCONFIG2 register (see figure 29). pclk is the pixel clock output pin. hsync is the horizontal synchronisation output signal. vsync is the vertical synchronisation output signal. The vsync, hsync and pclk signals can be tri-stated by asserting a logic 0 on the oe pin or by writing a logic 0 to the TriState bit in the DVBUSCONFIG3 register. In addition to this vsync, hsync and pclk signals can be switch off by writing a logic 0 to the VBusEn bit of the DVBUSCONFIG2 register. (see figure 32) vsync,hsync,pclk vsync,hsync,pclk oe d[9:0] d[9:0] TriState oe VsOveride, HsOveride, PclkOveride TriState Figure 32. hsync,vsync and pclk output circuit diagram Figure 29. Digital Pixel Data Out Bus Circuit Diagram 10.1 Digital Video Data Out Bus (d[9:0]) A programmable barrel shifter is provided to map the output of the internal pixel data framer to the pins of the digital video bus as illustrated in Figure 30. · In free running mode, (the PixClkMode bit of DVBUSCONFIG1 register is set to a logic 0), the pixel clock output pin, pclk, is always running with a fixed period. Pixel data appearing on the digital video bus d[9:0] are synchronized to a specified active edge of the clock as shown in Figure 33. Internal Pixel Framer Output Barrel Shift Register 9 8 7 6 5 4 3 2 1 10.2 Pixel Clock Output Pin (pclk) (Master Mode) The pixel clock output pin, pclk, is provided to act as a synchronisation reference for the pixel data appearing at the digital video out bus pins d[9:0]. This pin can be programmed to operate in two modes: 0 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 pclk Figure 30. Digital Video Bus Switching Modes The Bshift parameter in the DVBUSCONFIG2 register can be used to program the number of bits that the digital pixel data is shifted by. This feature allows a programmable digital gain to be implemented when connecting the sensor to 8 or 10 bit digital video processing systems as illustrated in Figure 31. d9 d9 d8 d8 d7 d7 10 bit d6 d6 Digital d5 d5 d4 Image d4 KACd3 d3 Processor d2 d2 d1 d1 d0 d0 a) KAC-9647 KAC-9647 Connected to a 10 bit Digital Image Processors d7 d9 d6 d8 d7 d5 8 bit d4 d6 Digital d3 d5 Image d4 d2 KACd3 d1 Processor d2 d0 d[9:0] a) pclk active edge negative pclk d[9:0] b) pclk active edge positive (default) invalid pixel data Figure 33. pclk in Free Running Mode · In data ready mode, (the PixClkMode bit of DVBUSCONFIG1 register is set to a logic 1), the pixel clock output pin pclk will produce a pulse with a specified level every time valid pixel data appears on the digital video bus d[9:0] as shown in Figure 34. pclk d[9:0] a) pclk active edge negative pclk d[9:0] b) pclk active edge positive invalid pixel data Figure 34. pclk in Data Ready Mode b) KAC-9647 KAC-9647 Connected to a 8 bit Digital Image Processors Figure 31. Example of connection to 10/8 bit systems www.kodak.com/go/imagers 585-722-4385 20 Email:imagers@kodak.com IMAGE SENSOR SOLUTIONS , By default the pixel clock is a free running active high (pixel data changes on the positive edge of the clock) with a period equal to the internal hclk. See section 6.3 for more pclk programming modes. 10.3 Horizontal Synchronisation Output Pin (hsync) The horizontal synchronisation output pin, hsync, is used as an indicator for row data. The hsync output pin can be programmed to operate in two modes as follows: · Level mode should be used when the pixel clock, pclk, is programmed to operate in free running mode. In level mode the hsync output pin will go to the specified level (high or low) at the start of each row and remain at that level until the last pixel of that row is read out on d[9:0] as shown in Figure 35. The hsync level is always synchronized to the active edge of pclk. The hsync pin is put into level mode by setting the HsyncMode bit of the DVBUSCONFIG1 register to a logic 0. The active level of the hsync pulse is programmed using the HsyncPol bit of the DVBUSCONFIG1 register. 10.4 Vertical/Horizontal Synchronisation Pin (vsync) The vertical synchronisation output pin, vsync, is used as an indicator for pixel data within a frame. The vsync output pin can be programmed to operate in two modes as follows: · Level mode should be used when the pixel clock, pclk, is programmed to operate in free running mode. In level mode the vsync output pin will go to the specified level (high or low) at the start of each frame and remain at that level until the last pixel of that row in the frame is placed on d[9:0] as shown in Figure 37. The hsync level is always synchronized to the active edge of pclk. The vsync pin is put into level mode by setting the VsyncMode bit of the DVBUSCONFIG1 register to a logic 0. The active level of the vsync pulse is programmed using the VsyncPol bit of the DVBUSCONFIG1 register. pclk d[9:0] vsync Frame n+1 Frame n a) vsync programmed to be active high pclk pclk d[9:0] d[9:0] hsync Row n Row n+1 a) hsync programmed to be active high (default) vsync Frame n+1 Frame n b) vsync programmed to be active low invalid pixel data Figure 37. vsync in Level Mode pclk d[9:0] hsync Row n+1 Row n b) hsync programmed to be active low Figure 35. hsync in Level Mode · Pulse mode should be used when the pixel clock, pclk, is programmed to operate in data ready mode. In pulse mode the hsync output pin will produce a pulse at the end of each row. The width of the pulse will be a minimum of four pclk cycles and its polarity can be programmed as shown in Figure 36. The hsync level is always synchronized to the active edge of pclk. The hsync pin is put into pulse mode by setting the HsyncMode bit of the DVBUSCONFIG1 register to a logic 1.The active level of the hsync pulse is programmed using the HsyncPol bit of the DVBUSCONFIG1 register. · Pulse mode should be used when the pixel clock, pclk, is programmed to operate in data ready mode. In pulse mode the vsync output pin will produce a pulse at the end of each frame. The width of the pulse will be a minimum of four hclk cycles and its polarity can be programmed as shown in Figure 38. The vsync level is always synchronized to the active edge of pclk. The hsync pin is put into pulse mode by setting the HsyncMode bit of the DVBUSCONFIG1 register to a logic 1. The active level of the vsync pulse is programmed using the VsyncPol bit of the DVBUSCONFIG1 register. pclk d[9:0] vsync pclk d[9:0] hsync pclk d[9:0] Row n+1 Row n a) hsync programmed to be active high vsync d[9:0] Row n Row n+1 b) hsync programmed to be active low Figure 36. hsync in Pulse Mode By default the first pixel data at the beginning of each row is placed on the digital video bus as soon as hsync is activated. Furthermore, hsync is de-activated upon the placement of the last pixel of the current row on the digital video bus the digital video bus. It is possible to shift the start and end edges of the hsync signal by programming the HsyncStart parameter of the DVBUSCONFIG0 register and the HsyncEnd parameter of the HYSNCADJUST register. www.kodak.com/go/imagers 585-722-4385 Frame n Frame n+ b) vsync programmed to be active low (default) invalid pixel data Figure 38. vsync in pulse mode pclk hsync Frame n+1 Frame n a) vsync programmed to be active high 21 By default the first pixel data at the beginning of each frame is placed on the digital video bus as soon as vsync is activated. Furthermore, vsync is de-activated upon the placement of the last pixel of the current frame on the digital video bus. It is possible to shift the start and end edges of the vsync signal by programming the VsyncStart parameter of the DVBUSCONFIG0 register and the VsyncEnd parameter of the HYSNCADJUST register. Email:imagers@kodak.com KAC-9647 KAC-9647 Functional Description (continued) KAC-9647 KAC-9647 IMAGE SENSOR SOLUTIONS Functional Description (continued) pclk vsync hsync d[9:0] c0 c1 c2 c3 c4 c5 c6 c7 c8 c9 c0 c1 c2 c3 c4 c5 c6 c7 c8 c9 c0 c1 c2 c3 c4 c5 c6 c7 c8 c9 row 2 row1 c0 c1 c2 c3 c4 c5 c6 c7 c8 c9 row 1 row 2 frame 1 frame 2 Programmable hsync to 1st valid pixel delay Programmable inter-frame delay Programmable row delay Figure 39. Example of Digital Video Port Timing in Progressive Scan Mode pclk vsync hysync d[9:0] c0 c2 c4 c6 c8 c0 row 1 c2 c4 c6 c8 c0 row 3 c2 c4 c6 c8 c0 c2 row 1 c4 c6 c8 row 3 frame 1 frame 2 Programmable hsync to 1st valid pixel delay Programmable inter-frame delay Programmable inter-row delay Figure 40. Example of Digital Video Port Timing in 2:1 Sub-sampling Mode pclk vsync hsync d[9:0] c0 c2 c4 c6 c8 c0 row 1 c2 c4 c6 c8 c0 row 2 c2 c4 c6 c8 c0 row 1 frame 1 c2 c4 c5 c8 row 2 frame 2 Programmable hsync to 1st valid pixel delay Programmable inter-frame delay Programmable inter-row delay Figure 41. Example of Digital Video Port Timing in 4:2 Sub-sampling Mode www.kodak.com/go/imagers 585-722-4385 22 Email:imagers@kodak.com IMAGE SENSOR SOLUTIONS 10.5 Synchronisation Signals in Slave Mode By default the sensor's digital video port synchronisation signals are configured to operate in slave mode. In slave mode the integrated timing and control block will only start frame and row processing upon the receipt of triggers from an external source. 10.6 Row Trigger Input Pin (hsync) The row trigger input pin, hsync, is used to trigger the processing of a given row. It must be activated for at least two mclk cycles. The first pixel data will appear at d[9:0] "Xmclk"periods after the falling edge of the row trigger, where Xmclk is given by: Note: Xmclk = 146 + PrtFrmEn*37 - 8*BlkPixelEn 1. Partial frame integration is disabled in slave mode. 2. In order to get all rows out of the device in slave mode VsynPol and HsynPol bits of register 0x53h must be set to 0. Only two synchronization signals are used in slave mode as follows: hsync vsync is the row trigger input signal. is the frame trigger input signal. Figure 42 shows the KAC-9647 KAC-9647's digital video port in slave mode connected to a digital video processor master DVP. d[9:0] RowTrig vsync FrameTrig pclk Pixel Clock mclk MasterClock KAC-9647 KAC-9647 PrtFrmEn is the partial frame integration bit setting in the ITIMECONFIG register. BlkPixelEn is the BlkPixelEn bit setting in the DVBUSCONFIG2 register The polarity of the active level of the row trigger can be programmed using the HsynPol bit of the DVBUSCONFIG1 register. By default it is active high. 10.7 Frame Trigger Input Pin (vsync) The frame trigger input pin, vsync, is used to reset the row address counter and prepare the array for row processing. It must be activated for at least one more mclk cycle than the row trigger and the falling edge must be between 1 and 96 mclk cycles after falling edge of hsync as illustrated in Figure 44. din[9:0] hsync Where: The polarity of the active level of the frame trigger is programmable. By default it is active high. DVP Figure 42. KAC-9647 KAC-9647 in slave mode hsync (row trigger) First Pixel In The Row Last Pixel In The Row d[9:0] Xmclk Number Of Pixel In The Row mclk Figure 43. hsync slave mode timing diagram for centered display window of 640 pixels hsync (row trigger) 96 mclk clock cycles vsync (frame trigger) internal row counter Last Row of Current Frame First Row of Next Frame mclk Minimum Valid Hsync Pulse Width Figure 44. vsync slave mode timing diagram. www.kodak.com/go/imagers 585-722-4385 23 Email:imagers@kodak.com KAC-9647 KAC-9647 Functional Description (continued) KAC-9647 KAC-9647 IMAGE SENSOR SOLUTIONS MEMORY MAP ADDR Register Reset Value 00h DEVID 47h 01h REV Latest Silicon 02h - 04h Description Device ID Register. Revision Register Reserved 05h VCLKGEN 00h Clock Generation Register 06h PWD&RST 00h Power Down & Reset Register 07h I2CMODE AAh I2C compatible Serial Interface Configuration Register OPCTRL 02h Operation Control Register 00h Reserved 10h VIDCONFIG 01h Video Color Configuration Register 11h VSCAN 04h Vertical Scan Configuration Register 08h 09h Reserved 0Ah - 0Fh 12 1 3h Reserved HSCAN 04h 14h 15h Horizontal Scan Configuration Register Reserved ITIMECONFIG 08h 16h-18h Integration Time Configuration Register Reserved 19h WROWS 00h Active Window Row Start Register 1Ah WROWE 16h Active Window Row End Register 1Bh WROWLSB 23h Active Window Row LSB Register 1Ch WCOLS 00h Active Window Column End Register 1Dh WCOLE 28h Active Window Column Start Register 1Eh WCOLE 23h Active Window Column LSB Register 20h FDELAYH 00h Frame Delay High Register 21h FDELAYL 08h Frame Delay Low Register 22h RDELAYH 00h Row Delay High Register 23h RDELAYL 08h Row Delay Low Register 24h ITIMEH 00h Integration Time High Register 25h ITIMEL 00h Integration Time Low Register BLKLEV 07h Black Level Compensation Register 41h BLKTARGET 10h Black Level Target Register 42h PGA0 00h Programmable Gain Amplifier, Channel 0 43h PGA1 00h Programmable Gain Amplifier, Channel 1 44h PGA2 00h Programmable Gain Amplifier, Channel 2 45h PGA3 00h Programmable Gain Amplifier, Channel 3 46h OFFSET0 00h Gain Channel 0 Offset Register 47h OFFSET1 00h Gain Channel 1 Offset Register 48h OFFSET2 00h Gain Channel 2 Offset Register 26h - 3Fh 40h Reserved 49h OFFSET3 00h Gain Channel 3 Offset Register 4Ah CFAMAP 1Bh Gain Color Map Register. 4Bh- 4Fh www.kodak.com/go/imagers 585-722-4385 Reserved 24 Email:imagers@kodak.com IMAGE SENSOR SOLUTIONS KAC-9647 KAC-9647 MEMORY MAP (continued) ADDR Register Reset Value Description 50h VSYNCADUST 08h Vsync Adjust Register 51h HSYNCADUST 08h Hsync Adjust Register 52h DVBUSCONFIG0 00h Digital Video Bus Configuration Register 0 53h DVBUSCONFIG1 0Ch Digtal Video Bus Configuration Register 1 54h DVBUSCONFIG2 F0h Digtal Video Bus Configuration Register 2 55h DVBUSCONFIG3 00h Digtal Video Bus Configuration Register 3 56h - 7Fh 80h Reserved INITREG1 00h Sensor Initialization Register 1 81h - 82h 83h Reserved PIXELOFFSET 1Eh Sensor's Pixel Offset Register 84h 85h Reserved POWCTRL 81h Sensor's Power Down Control Register 86h - 87h 88h Reserved INITREG2 www.kodak.com/go/imagers 585-722-4385 00h Sensor Initialization Register 2 25 Email:imagers@kodak.com KAC-9647 KAC-9647 IMAGE SENSOR SOLUTIONS Register Set The following section describes all available registers in the KAC-9647 KAC-9647 register bank and their function. Register Name Address Mnemonic Type Reset Value Bit 7:0 7:0 DevId I2cDevAddr Use to program the I2C compatible device address. By default, the value is 55 hex. AdvWr Set to a logic 1 to activate the I2C compatible serial interface's advance write option. In advance write mode, several addresses can be written to without the need to restart. Description Set to a logic 0, the default, to operate the interface in mode. The sensor's silicon revision. Clock Generation Register 05 Hex VCLKGEN Read/Write 00 Hex. Bit Symbol Register Name Address Mnemonic Type Reset Value Description Bit Reserved. HclkGen ÷4 11 ÷6 1 Power Down/Reset Register 06 Hex PWD&RST Read/Write 00 Hex. Bit Symbol 7:2 Set to a logic 1 to configure the digital video port's synchronisation's signal to operate in master mode. Set to a logic 0 (the default) to configure the digital video port's synchronisation signals to operate in slave mode. Reserved. Bit Description Reserved. MasterMode ÷2 10 Bit Symbol ÷1(default) 01 2 I2C compatible standard write Operation Control Register 09 Hex OPCTRL Read/Write 02 Hex. 7:3 Use to divide the frequency of the sensors master clock input, mclk, and generate the sensor's internal clock, hclk. 00 0 Description 0 Silicon Revision 01 Hex REV Read Only Latest Silicon Hex SiRev Register Name Address Mnemonic Type Reset Value Bit Symbol The sensor's device ID. 7 2:1 I2C Mode Register 07 Hex I2CMODE Read/Write AA Hex. 7:1 Description Bit Symbol Register Name Address Mnemonic Type Reset Value Bit Bit Bit Symbol Register Name Address Mnemonic Type Reset Value Bit Device ID 00 Hex DEVID Read Only 47 Hex Register Name Address Mnemonic Type Reset Value 0 Description This bit is reserved for factory testing and must be set to a logic 1 at all times. RstzSoft Set this self clearing register to a logic 1 to reset all state machines contained in the integrated smart timing and control circuitry. Reserved. 1 SenReset Set this self clearing bit to a logic 1 to reset the sensor. 0 PwDn Set to a logic 1 to power down the chip. All internal clocks will be turned off in this mode. Set to a logic 0, (the default) to put the chip in power up mode. Refer to section 8.2 for information on the low power down sequence. www.kodak.com/go/imagers 585-722-4385 26 Email:imagers@kodak.com IMAGE SENSOR SOLUTIONS Bit Video Configuration Register 10 Hex VIDCONFIG Read/Write 01 Hex. Bit Symbol 7:1 0 Register Name Address Mnemonic Type Reset Value Description Bit Reserved. Color Bit 2 7:3 2 Set to a logic 1, (the default) to set the sensor's horizontal scan direction to operate from left to right. HSub Set to a logic 1 to enable horizontal sub sampling. Set to a logic 0, (the default), to disable horizontal sub sampling. 0 HAvrg Set to a logic 1 to enable horizontal averaging. Set to a logic 0, (the default) to disable horizontal averaging. Description Reserved. VscanDir Set to a logic 1, (the default), to set the sensor's vertical scan direction to operate from top to bottom. Register Name Address Mnemonic Type Reset Value VSub Bit 3 Reserved. Bit Symbol Description Reserved. PrtFrmEn Set to a logic 1, (the default), to turn on the Partial Frame Integration. Set to a logic 0, to turn off the partial Partial Frame Integration. 2:0 www.kodak.com/go/imagers 585-722-4385 Integration Time Configuration Register 15 Hex ITIMECONFIG Read/Write (Double Buffered) 08 Hex. 7:4 Set to a logic 1 to enable vertical sub sampling. Set to a logic 0, (the default), to disable vertical sub sampling. 0 Reserved. HscanDir 1 Set to a logic 0, to set the sensor's vertical scan direction to operate from bottom to top. 1 Description Set to a logic 0, to set the sensor's horizontal scan direction to operate from right to left. Vertical Scan Register 11 Hex VSCAN Read/Write (Double Buffered) 04 Hex. Bit Symbol Bit Symbol 7:3 Set to a logic 1, (the default), to configure the sensor's smart timing and control circuit to operate in color mode. This bit always be set for color sensor. Set to a logic 0 to configure the sensor's smart timing and control circuit to operate in monochrome mode. Register Name Address Mnemonic Type Reset Value Horizontal Scan Register 13 Hex HSCAN Read/Write (Double Buffered) 04 Hex. 27 Reserved, should always be set to a logic 0. Email:imagers@kodak.com KAC-9647 KAC-9647 Register Set (continued) Register Name Address Mnemonic Type Reset Value KAC-9647 KAC-9647 IMAGE SENSOR SOLUTIONS Register Set (continued) Register Name Address Mnemonic Type Reset Value Bit 7:0 Bit Symbol WStartRow[10:3] Register Name Address Mnemonic Type Reset Value Bit 7:0 4:3 Bit Use to program the display window's start row address' MSBs. The LSBs can be programmed using the DROWLSB register. 7:0 Active Window Row End Register 1A Hex WROWE Read/Write (Double Buffered) 1B Hex. WEndRow[10:3] Description Bit Use to program the scan window's end row address' MSBs. The LSBs can be programmed using the WROWLSB register. 7:0 Bit Symbol Reserved WStartRow[2] WStart Row[1:0] Bit Use to program the display window's start row address LSBs. The MSBs can be programmed using the WROWS register. WEndRow[2] WEnRow[1:0] Bit Symbol WEndCol[10:3] Description Use to program the scan window's end column address' MSBs. The LSBs can be programmed using the WCOLLSB register. Active Window Column LSB Register 1E Hex WCOLLSB Read/Write (Double Buffered) 23 Hex. Bit Symbol Description Reserved WStart Col[1:0] The two LSBs of the windows column start address are fixed to 0Hex. Although these bits can be written to they will have on effect on the LSBs of the window's column start address. WEndCol[2] Use to program the scan window's end column address' LSBs. The MSBs can be programmed using the WCOLE register. 1:0 28 Use to program the display window's start column address' LSBs. The MSBs can be programmed using the WCOLS register. 2 NOTE: The Row and Column start and end registers should be written to at power up to guarantee that the expected window size is set. WStartCol[2] 4:3 The two LSBs of the windows row end address are fixed to 3Hex. Although these bits can be written to they will have on effect on the LSBs of the window's row end address. www.kodak.com/go/imagers 585-722-4385 Use to program the display window's start column address' MSBs. The LSBs can be programmed using the WCOLLSB register. 5 Use to program the scan window's end row address's LSBs. The MSBs can be programmed using the WROWE register 1:0 Description Active Window Column End Register 1D Hex WCOLE Read/Write (Double Buffered) 28 Hex. 7:6 The two LSBs of the windows row start address are fixed to 0Hex. Although these bits can be written to they will have on effect on the LSBs of the window's row start address. 2 WStartCol[10:3] Register Name Address Mnemonic Type Reset Value Description Active Window Column Start Register 1C Hex WCOLS Read/Write (Double Buffered) 00 Hex. Bit Symbol Register Name Address Mnemonic Type Reset Value Active Window Row LSB Register 1B Hex WROWLSB Read/Write (Double Buffered) 23 Hex. 7:6 5 Register Name Address Mnemonic Type Reset Value Description Bit Symbol Register Name Address Mnemonic Type Reset Value Bit Active Window Row Start Register 19 Hex WROWS Read/Write (Double Buffered) 00 Hex. WEndCol[1:0] The two LSBs of the windows column end address are fixed to 3Hex. Although these bits can be written to they will have on effect on the LSBs of the window's column end address. Email:imagers@kodak.com IMAGE SENSOR SOLUTIONS Bit 7:0 Bit Symbol Fdelay[14:7] Register Name Address Mnemonic Type Reset Value Bit Frame Delay High Register 20 Hex FDELAYH Read/Write (Double Buffered) 00 Hex. Register Name Address Mnemonic Type Reset Value Description Bit Use to program the MSBs of the frame delay. Note the max allowed frame delay is 32767. Bit Symbol 7:4 3:0 Description Fdelay[6:0] Bit 7:0 Bit Bit Itime[10:7] Rdelay[12:5] Itime[6:0] Description Register Name Address Mnemonic Type Reset Value Row Delay Low Register 23 Hex RDELAYL Read/Write (Double Buffered) 08 Hex. Bit Symbol Bit Symbol Bit Program to set the integration time of the array. The value programmed in the register is the number of rows ahead of the selected row to be reset. Black Level Configuration Register 40 Hex BLKLEVCONFIG Read/Write 07 Hex. Bit Symbol 7 Description Description Reserved. 6:0 Use to program the MSBs of the row delay. Program to set the integration time of the array. The value programmed in the register is the number of rows ahead of the selected row to be reset. Itime can not be greater then the number of active rows. Integration Time High Register 25 Hex ITIMEL Read/Write (Double Buffered) 00 Hex. 7 Row Delay High Register 22 Hex RDELAYH Read/Write (Double Buffered) 00 Hex. Bit Symbol Register Name Address Mnemonic Type Reset Value Use to program the LSBs of the frame delay. Note the max allowed frame delay is 32767. Description Reserved Register Name Address Mnemonic Type Reset Value Reserved. Register Name Address Mnemonic Type Reset Value Bit Symbol Frame Delay Low Register 21 Hex FDELAYL Read/Write (Double Buffered) 08 Hex. 7 6:0 Integration Time High Register 24 Hex ITIMEH Read/Write (Double Buffered) 00 Hex. Description Reserved. 4:0 3 BlkLevEn Set to a logic 1, (the default) to disable the internal black level compensation circuit. Set to a logic 0 to enable the internal black level compensation circuit. 2:0 7:5 BlkRate Use to adjust the rate at which the auto black level circuit converges to the programmed target, BlkTarget. See section 7.3 for more information. Reserved. Rdelay[4:0] Use to program the LSBs of the row delay. Register Name Address Mnemonic Type Reset Value Bit 7:0 www.kodak.com/go/imagers 585-722-4385 29 Reference Black Level Register 41 Hex BLKTARGET Read/Write 10 Hex. Bit Symbol BlkRef Description Use to program the target black level. See section 7.3 for more information. Email:imagers@kodak.com KAC-9647 KAC-9647 Register Set (continued) Register Name Address Mnemonic Type Reset Value KAC-9647 KAC-9647 IMAGE SENSOR SOLUTIONS Register Set (continued) Register Name Address Mnemonic Type Reset Value Bit Register Name Address Mnemonic Type Reset Value PGA Channel 0 Register 42 Hex PGA0 Read/Write 00 Hex. Bit Symbol 7 Bit Description 7:0 Reserved 6:0 PGA0 Register Name Address Mnemonic Type Reset Value Bit Use to program the analog gain of color channel 0. Max gain is 16dB of gain programmable in 128 steps of 0.125dB. Bit Symbol 7 Bit PGA1 Register Name Address Mnemonic Type Reset Value Bit 7:0 Bit Symbol Bit 7:0 Reserved 6:0 PGA2 Register Name Address Mnemonic Type Reset Value Bit 6:0 Use to program the analog gain of color channel 2. Max gain is 16dB of gain programmable in 128 steps of 0.125dB. Bit 7:0 PGA Channel 3 Register 45 Hex PGA3 Read/Write 00 Hex. Bit Symbol 7 Description Bit Use to program the analog gain of color channel 3. Max gain is 16dB of gain programmable in 128 steps of 0.125dB. Use to manually set the black level for gain channel 0. See section 7.2 for more information. Description Use to manually set the black level for gain channel 1. See section 7.2 for more information. Offset Channel 2 Register 48 Hex OFFFSET2 Read/Write 00 Hex. Bit Symbol Offset2 Description Use to manually set the black level for gain channel 2. See section 7.2 for more information. Offset Channel 3 Register 49 Hex OFFSET3 Read/Write 00 Hex. Bit Symbol Offset3 Register Name Address Mnemonic Type Reset Value Reserved PGA3 Offset1 Register Name Address Mnemonic Type Reset Value Description Description Offset Channel 1 Register 47 Hex OFFSET1 Read/Write 00 Hex. Bit Symbol Register Name Address Mnemonic Type Reset Value Use to program the analog gain of color channel 1. Max gain is 16dB of gain programmable in 128 steps of 0.125dB. PGA Channel 2 Register 44 Hex PGA2 Read/Write 00 Hex. 7 Offset0 Description Reserved 6:0 Bit Symbol Register Name Address Mnemonic Type Reset Value PGA Channel 1 Register 43 Hex PGA1 Read/Write 00 Hex. Offset Channel 0 Register 46 Hex OFFSET0 Read/Write 00 Hex. Description Use to manually set the black level for gain channel 3. See section 7.2 for more information. Gain Color Map Register 4A Hex CFAMAP Read/Write 1B Hex. Bit Symbol Description Use to program the color map for gain channel 0. See section 6.2 for more information. Note: When using monochrome sensor set all bits [7:0] to 0. ColorMap1 Use to program the color map for gain channel 1. See section 6.2 for more information. 3:2 ColorMap2 Use to program the color map for gain channel 2. See section 6.2 for more information. 1:0 30 ColorMap0 5:4 www.kodak.com/go/imagers 585-722-4385 7:6 ColorMap3 Use to program the color map for gain channel 3. See section 6.2 for more information. Email:imagers@kodak.com IMAGE SENSOR SOLUTIONS Register Name Address Mnemonic Type Reset Value Bit Bit Symbol 7:6 4:0 Register Name Address Mnemonic Type Reset Value VSYNC Latency Register 50 Hex VSYCADJUST Read/Write 08 Hex. Description Bit Reserved. VsyncEnd 7:4 Synchronization Adjustment Register 52 Hex DVBUSCONFIG0 Read/Write 00 Hex. Bit Symbol VsyncStart By default, in pulse mode the vsync signal will remain active for four pclk periods after end of frame. In level mode vsync will remain active for the duration of the frame delay time. 01001 to 11111 Register Name Address Mnemonic Type Reset Value Bit +1 pclk clock to +24 pclk clocks 3:0 Bit Symbol HsyncStart By default, in pulse mode the hsync signal will remain active for four pclk periods after end of row. In level mode hsync will remain active for the duration of the row delay time. Use to adjust the time that the hsync signal goes active in multiples of pclk as follows: 0000 to 1111 HSYNC Latency Register 51 Hex HSYNCADJUST Read/Write 08 Hex. 7:4 3:0 no adjustment, the default 0 pclk clocks to -15 pclk clock Reserved 01000 0000 to 1111 no vsync pulse 00001 to 00111 By default, in pulse mode the vsync signal will remain active for four pclk periods after end of frame. In level mode vsync will remain active for the duration of the frame delay time. Use to adjust the time that the vsync signal goes active in multiples of pclk as follows: Use to adjust the time that the vsync signal goes inactive in multiples of pclk as follows: 0000 Description 0 pclk clocks to -15 pclk clock Description Reserved. HsyncEnd By default, in pulse mode the hsync signal will remain active for four pclk periods after end of each row. In level mode hsync will remain active for the duration of the row delay time. Use to adjust the time that the hsync signal goes inactive in multiples of pclk as follows: 0000 no hsync pulse 0001 to 0111 Reserved 01000 no adjustment, the default 1001 to 1111 +1 pclk clock to +8 pclk clocks www.kodak.com/go/imagers 585-722-4385 31 Email:imagers@kodak.com KAC-9647 KAC-9647 Register Set (continued) KAC-9647 KAC-9647 IMAGE SENSOR SOLUTIONS Register Set (continued) Register Name Address Mnemonic Type Reset Value Bit Register Name Address Mnemonic Type Reset Value Polarity Adjustment Register 53 Hex DVBUSCONFIG1 Read/Write 0C Hex. Bit Symbol 7 Bit Description PixClkMode VsyncMode HsyncMode Set to a logic 1 to operate the hsync signal to pulse for a minimum of four pixel clocks at the end of each row. Set to a logic 0, (the default) to force the hsync signal to a level indicating valid data within a row. Set to a logic 0 to tri-state all output signals (data and control) on the digital video port. set to a logic 1, (the default) to enable all signals (data and control) on the digital video port. 6 Set to a logic 1 to operate the vsync pin to "pulse mode". Set to a logic 0, (the default) to operate the vsync signal to "level mode". 4 3:2 1 BlkPixelEn Set to a logic 1, (the default) to read out the middle 8 black pixels at the start of every row. Set to a logic 0 to mask out the black pixel readout. 0 NOTE: In master mode when the black pixels are enabled the active edge of Hsync corresponds to the first black pixel. 5 PixClkPol Reserved VsyncPol HsyncPol Assert to force the vsync signal to generate a logic 1 during a frame readout (Level Mode), or a negative pulse at the end of a frame readout (Pulse Mode). Clear (the default) to force the vsync signal to generate a logic 0 during a frame readout (Level Mode), or a positive pulse at the end of a frame readout (Pulse Mode). NOTE: In slave mode this bit must be set to 0. 4 3:0 Set to a logic 1 to set the active edge of the pixel clock to negative. Set to a logic 1, (the default), to set the active edge of the clock to positive. Reserved Bshift[3:0] Use to program the routing of the MSB output of the internal video A/D to a bit on the digital video bus. 0000 A/D[9:0] -> d[9:0] 0001 A/D[9:0] -> d[8:0],d[9] 0010 A/D [9:0] ->d[7:0],d[9:8] 0011 A/D [9:0] -> d[6:0],d[9:7] 0100 A/D [9:0] -> d[5:0],d[9:6] 0101 A/D[9:0] -> d[4:0],d[9:5] Assert to force the hsync signal to generate a logic 1 during a row readout (Level Mode), or a negative pulse at the end of a row readout (Pulse Mode). Clear (the default) to force the hsync signal to generate a logic 0 during a row readout (Level Mode), or a positive pulse at the end of a readout (Pulse Mode). NOTE: In slave mode this bit must be set to 0. www.kodak.com/go/imagers 585-722-4385 Description OutputEn Set the to a logic 1 to operate pclk to "data ready mode". Set to a logic 0, the default, to set pclk to "free running mode". 5 Bit Symbol 7 Reserved 6 Video Output Adjustment Register 54 Hex DVBUSCONFIG2 Read/Write F0 Hex. 0110 A/D [9:0] -> d[3:0],d[9:4] 0111 A/D [9:0] -> d[2:0],d[9:3] 1000 A/D [9:0] ->d[1:0],d[9:2] 1001 A/D [9:0] -> d[0],d[9:1] 1010 A/D [9:0] -> d[9:0] 32 Email:imagers@kodak.com IMAGE SENSOR SOLUTIONS Register Name Address Mnemonic Type Reset Value Bit Bit Symbol 7:5 4 Register Name Address Mnemonic Type Reset Value Video Output Tristate Adjustment Register 55 Hex DVBUSCONFIG3 Read/Write 00 Hex.Register Set (continued) Description Bit Reserved Tristate 7:0 Power Down Control Register 85 Hex POWCTRL Read/Write 81 Hex. Bit Symbol Patrol Write 82Hex before power down to minimize the sensor's power down current. Digital output tristate. Set this bit to 1 to tristate all digital outputs. (vsync, hsync, pclk, data, external sync). Use can override this setting with independent override bits. 3 VsOverride HsOverride Overrides tri-stating of Hsync port in master timing mode. To enable override, set bit to 1. 1 PclkOverride Write 81Hex after power up from the power down mode to ensure correct operation of the sensor. Overrides tri-stating of Vsync port in master timing mode. To enable override, set bit to 1. 2 Overrides tri-stating of Pclk port in master timing mode. To enable override, set bit to 1. 0 ExtSyncOverride Register Name Address Mnemonic Type Reset Value Bit 7:0 Refer to section 9.2 for more information. Register Name Address Mnemonic Type Reset Value Bit Overrides tri-stating of external sync port in master timing mode. To enable override, set bit to 1. 7:0 PixCal Initialization Register 2 88 Hex INITREG2 Read/Write 00 Hex. Bit Symbol Int2 Description Write 1 Hex to activate the sensor's initialization registers Write 0 Hex to disable the sensor's initialization registers. Initialization Register 1 80 Hex INITREG1 Read/Write 00 Hex. Bit Symbol Description Note this register is used for · the pixel array offset calibration (section 7.2) · power/up and down of the array (section 8.2) Description Write 5 Hex to enable the pixel offset calibration circuits. Notes: This register can only be accessed when the Int2 parameter in the INTREG2 register is set to 01Hex. PixCal should be reset to 00Hex at the end of the pixel offset calibration procedure (see section 7.1 for more details). Register Name Address Mnemonic Type Reset Value Bit 7:0 Pixel Offset Register 83 Hex PIXELOFFSET Read/Write 1E Hex. Bit Symbol PixelOffset Description Use to compensate for the sensors natural pixel offset. See section 7.1 for more details. www.kodak.com/go/imagers 585-722-4385 33 Email:imagers@kodak.com KAC-9647 KAC-9647 Register Set (continued) KAC-9647 KAC-9647 IMAGE SENSOR SOLUTIONS Timing Information 1.0 DIGITAL VIDEO PORT MASTER MODE TIMING LEVEL MODE pclk hsync t2 t1 d[9:0] P0 Pn P1 t3 Figure 45. Row Timing Diagram pclk vsync t6 t5 hsync R1 R0 Rn Rn t1 t2 Figure 46. Frame Timing pclk vsync t6 t5 hsync Fdelayn-1 Fdelay1 R0 Fdelayn R1 R2 Rn t2 t1 Frame (n) Inter Frame Delay Figure 47. Frame Delay Timing (With Inter Frame Delay). Label Descriptions Min Typ Max t0 pclk period 37.04ns 45.45ns 83.33ns t1 hsync inactive1,2 level mode (RNHclk - Npix + HsyncStart - HsyncEnd - 8*BlkPixelEn) * Hclk t2 hsync active1,2 level mode (HsyncEnd - HsyncStart + 8*BlkPixelEn + Npix) * Hclk t3 first valid pixel data after hsync active HsyncStart t5 vsync inactive1,3 level mode (Fdelay*RNHclk) + Ropcycle + Ritime + VsyncStart - VsyncEnd) * Hclk t6 vsync active1,3 level mode (VsyncEnd - VsyncStart + (RNHclk * Nrows) * Hclk * Hclk 1. See section 6.4 for definitions of RNHclk and FNHclk 2. The values of HsyncStart and HsyncEnd are stored in the DVBUSCONFIG0 and HSYNCADJUST registers respectively. 3. The values of VsyncStart and VsyncEnd are stored in the DVBUSCONFIG0 and VSYNCADJUST registers eruptively. www.kodak.com/go/imagers 585-722-4385 34 Email:imagers@kodak.com IMAGE SENSOR SOLUTIONS Timing Information 2.0 DIGITAL VIDEO PORT MASTER MODE TIMING PULSE MODE pclk hsync t1 t2 t3 d[9:0] P639 P0 P39 P1 Figure 48. Row Timing Diagram pclk vsync hsync R479 R0 t5 t6 Figure 49. Frame Timing t2 t1 vsync t5 t6 hsync R479 Fdelayn-2 Fdelayn-1 Fdelayn t2 R0 t1 Inter Frame Delay Rn R1 Frame (n) Figure 50. Frame Delay Timing (With Inter Frame Delay). Label Descriptions Min Typ Max t0 pclk period 37.04ns 45.45ns 83.33ns t1 hsync inactive1,2 pulse mode (RNHclk - 3) * Hclk t2 hsync active1,2 pulse mode 3 * Hclk t3 first valid pixel data after hsync active 145 * Hclk t5 vsync inactive1,3 pulse mode (FNHclk - 3) * Hclk t6 vsync active1,3 pulse mode 3 * Hclk 1. See section 6.4 for definitions of RNHclk and FNHclk 2. The values of HsyncStart and HsyncEnd are stored in the DVBUSCONFIG0 and HSYNCADJUST registers respectively. 3. The values of VsyncStart and VsyncEnd are stored in the DVBUSCONFIG0 and VSYNCADJUST registers eruptively. www.kodak.com/go/imagers 585-722-4385 35 Email:imagers@kodak.com IMAGE SENSOR SOLUTIONS KAC-9647 KAC-9647 Timing Information (continued) 3.0 DIGITAL VIDEO PORT SLAVE MODE TIMING t3 t1 hsync trigger row n trigger row n+1 t2 d[9:0] P640 P1 P640 mclk Row n-1 Row n Figure 51. Slave Mode Row Trigger and Readout Timing t4 hsync vsync trigger first row in frame n+1 trigger last row in frame n t5 trigger frame n + 1 with falling edge of vsync mclk Figure 52. Slave Mode d[9:0], hsync & vsync to pclk Timing d[9:0] t6 mclk t7 pclk Figure 53. Rising Edge of mclk to Valid Pixel Data The following specifications are from simulation. For the minimum value the conditions are all supply pins = +3.0V & CL = 5pF and 0C while the maximum value conditions are all supply pins = 3.6V & CL = 25pF. Label Descriptions Min t1 Pulse width of row trigger 2 * mclk t2 First pixel out after falling edge of row trigger1 Xmclk t3 Minimum time between row triggers2 (Xmclk +Ncol) * mclk t4 Time to falling edge of frame trigger after falling edge of last row trigger in current frame. 1*mclk t5 Pulse width of Frame trigger 3*mclk t6 Time to valid pixel data after rising edge of mclk 14.9ns 39.7ns t7 Time to pclk rising edge after rising edge of mclk 14.5ns 35.0ns www.kodak.com/go/imagers 585-722-4385 36 Typ Max Xmclk Xmclk 96 * mclk Email:imagers@kodak.com KAC-9647 KAC-9647 IMAGE SENSOR SOLUTIONS 1. See section 10.6 for definition of Xmclk Timing Information (continued) mclk vsync t4 t1 hsync t3 t2 Figure 54. Set up and Hold Times for Slave Mode PARAMETER LABEL MIN MAX UNIT Vsync rising edge to Mclk rising (set-up time) t1 -6.0 14.6 ns Hsync rising edge to Mclk rising (set-up time) t2 -7.3 14.2 ns Mclk rising edge to Hsync falling edge (hold time) t3 23.8 45.3 ns Mclk rising edge to Vsync falling edge (hold time) t4 23.4 44.0 ns Figure 55. Set up and Hold times for Slave Mode www.kodak.com/go/imagers 585-722-4385 37 Email:imagers@kodak.com IMAGE SENSOR SOLUTIONS Timing Information (continued) 1.0 SERIAL BUS TIMING Sr Sr P tfDA tfDA sda tSU;STA tHD;DAT tHD;STA tSU;STO tSU;DAT sclk trCL trCL1 trCL = Rp resistor pull-up tHIGH tLOW tLOW trCL1 tHIGH (1) = MCS current source pull-up (1) Rising edge of the first sclk pulse after an acknowledge bit. Figure 1. I2C Compatible Serial Bus Timing. The following specifications apply for all supply pins = +3.3V, CL = 10pF, and sclk = 400KHz unless otherwise noted. Boldface limits apply for TA = TMIN to TMAX: all other limits TA = 25oC (Note 7) PARAMETER SYMBOL MIN MAX UNIT sclk clock frequency fSCLH 0 400 KHz Set-up time (repeated) START condition tSU;STA 0.6 - µS Hold time (repeated) START condition tHD;STA 0.6 - µS LOW period of the sclk clock tLOW 1.3 - µS HIGH period of the sclk clock tHIGH 0.6 - µS Data set-up time tSU;DAT 180 - nS Data hold time tHD;DAT 0 0.9 µS Set-up time for STOP condition tSU;STO 0.6 Capacitive load for and sclk lines Cb www.kodak.com/go/imagers 585-722-4385 38 µS 400 pF Email:imagers@kodak.com IMAGE SENSOR SOLUTIONS Mechanical Information H Optical Center G K Pin 1 F Glass Lid E B D Chip C A Dimension Description min (mm) typ (mm) max (mm) A Distance from top of die to bottom of cavity 0.788 0.820 0.852 B Top of die to top of glass lid 0.690 0.970 1.250 C Top of package to bottom of glass lid 0.250 0.420 0.590 D Max total thickness of package E Thickness of lid F X-Coordinate of optical center (nom) 5.340 G Y-Coordinate of optical center (nom) 6.425 H X-Dimension of Package 10.540 10.670 10.970 K Y-Dimension of Package 10.540 10.670 10.970 Die Rotational Accuracy -2o 0o +2o www.kodak.com/go/imagers 585-722-4385 2.580 0.530 39 0.640 0.750 Email:imagers@kodak.com IMAGE SENSOR SOLUTIONS Package Information * *