K8Q2815UQB 56TSOP K8P2715UQB DA/555H DA/X00H DA/X01H 257EH 2506H 2501H - Datasheet Archive

 

FLASH MEMORY 128Mb B-die Page NOR Specification Dual Die Package (56TSOP) (64Mb x 2) INFORMATION IN THIS DOCUMENT IS PROVIDED IN

 

K8Q2815UQB K8Q2815UQB FLASH MEMORY 128Mb B-die Page NOR Specification Dual Die Package (56TSOP 56TSOP) (64Mb x 2) INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL INFORMATION IN THIS DOCUMENT IS PROVIDED ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND. 1. For updates or additional information about Samsung products, contact your nearest Samsung office. 2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar applications where Product failure couldresult in loss of life or personal or physical harm, or any military or defense application, or any governmental procurement to which special terms or provisions may apply. * Samsung Electronics reserves the right to change products or specification without notice. 1 Revision 1.1 June 2007 K8Q2815UQB K8Q2815UQB FLASH MEMORY Document Title 128M Bit (8M x16) Page Mode / Multi-Bank NOR Flash Memory / 56TSOP 56TSOP - Two 64M Bit NOR with 1 Chip Enable (A22 is virtual Chip Enable of 2nd Chip) Revision History Revision No. History Draft Date Remark 0.0 Initial draft 0.1 Part ID is changed from K8P2715UQB K8P2715UQB to K8Q2815UQB K8Q2815UQB. 0.2 - Group block protect time : 100us -> 120us - Group block unprotect time : 1.2ms -> 3ms In Figure 8. Block Group Protection & Unprotection Algorithms & Block Group Protect & Unprotect Operations timing 0.5 - Page Read Current (Icc6) max. value is changed 15mA to 22mA - Package dimension is added. March 21, 2007 Preliminary 0.6 - "#OE or #CE should be toggled in each toggle bit status read." is added in DQ2 & DQ6 toggle bit. April 23, 2007 Preliminary 1.0 - Specification is finalized. June 08, 2007 1.1 - Fast access time 55ns is deleted. - Absolute maximum ratings All other pins value is changed -0.5 to 2.5 to -0.5 to Vcc + 0.5. June 28, 2007 2 November 14, 2006 Target Information Target January 19, 2007 Information February 08, 2007 Target Information Revision 1.1 June 2007 K8Q2815UQB K8Q2815UQB FLASH MEMORY 128M Bit (8M x16) Page Mode / Multi-Bank NOR Flash Memory / 56TSOP 56TSOP - Two 64M Bit NOR with 1 Chip Enable (A22 is virtual Chip Enable of 2nd Chip) FEATURES · Single Voltage, 2.7V to 3.6V for Read and Write operations · Organization 8M x16 bit (Word mode Only) · Fast Read Access Time : 60ns · Page Mode Operation 8 Words Page access allows fast asychronous read Page Read Access Time : 20ns · Read While Program/Erase Operation · Multiple Bank architectures (8 banks) Bank 0 : 8Mbit (4Kw x 8 and 32Kw x 15) Bank 1 :24Mbit (32Kw x 48) Bank 2 : 24Mbit (32Kw x 48) Bank 3 : 8Mbit (4Kw x 8 and 32Kw x 15) Bank 4 : 8Mbit (4Kw x 8 and 32Kw x 15) Bank 5 :24Mbit (32Kw x 48) Bank 6 : 24Mbit (32Kw x 48) Bank 7 : 8Mbit (4Kw x 8 and 32Kw x 15) · OTP Block : Extra 256 word - 128word for factory and 128word for customer OTP · Power Consumption (typical value) - Active Read Current : 45mA (@10MHz) - Program/Erase Current : 17mA - Read While Program or Read While Erase Current : 35mA - Standby Mode/Auto Sleep Mode : 30uA (15uA for each chip) · Support Single & Quad word accelerate program · WP/ACC input pin - Allows special protection of two outermost boot blocks at VIL, regardless of block protect status (for each chip) - Removes special protection of two outermost boot block at VIH, the two blocks return to normal block protect status (for each chip) - Accelerated Quadword Program time : 1.5us · Erase Suspend/Resume · Program Suspend/Resume · Unlock Bypass Program · Hardware RESET Pin · Command Register Operation · Block Protection / Unprotection · Supports Common Flash Memory Interface · Industrial Temperature : -40°C to 85°C · Endurance : 100,000 Program/Erase Cycles Minimum · Data Retention : 10 years · Vccq options at 1.8V and 3V I/O · Package options - 56 Pin TSOP (20x14mm) only GENERAL DESCRIPTION The K8Q2815UQB K8Q2815UQB featuring single 3.0V power supply, is an 128Mbit NOR-type Flash Memory organized as 8M x16. The memory architecture of the device is designed to divide its memory arrays into 284 blocks with independent hardware protection. This block architecture provides highly flexible erase and program capability. The K8Q2815UQB K8Q2815UQB NOR Flash consists of eight banks. This device is capable of reading data from one bank while programming or erasing in the other banks. The K8Q2815UQB K8Q2815UQB offers fast page access time of 20~30ns with random access time of 60~70ns. The devices fast access times allow high speed microprocessors to operate without wait states. The device performs a program operation in unit of 16 bits (Word) and erases in units of a block. Single or multiple blocks can be erased. The block erase operation is completed within typically 0.7 sec. The device requires 15mA as program/ erase current in the industrial temperature ranges. The K8Q2815UQB K8Q2815UQB NOR Flash Memory is created by using Samsung's advanced CMOS process technology. This device is available in 56 Pin TSOP package. The device is compatible with EPROM applications to require high-density and costeffective non-volatile read/write storage solutions. PIN DESCRIPTION Pin Name A0 - A22 DQ0 - DQ15 Pin Function Address Inputs (A22 : Virtual Chip Enable of 2nd Chip) Data Inputs / Outputs CE Chip Enable OE Output Enable RESET Hardware Reset Pin RY/BY Ready/Busy Output WE WP/ACC Write Enable Hardware Write Protection/Program Acceleration Vcc Power Supply VSS Ground N.C No Connection SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice. 3 Revision 1.1 June 2007 K8Q2815UQB K8Q2815UQB FLASH MEMORY 56TSOP 56TSOP PIN CONFIGURATION NC A22 A15 A14 A13 A12 A11 A10 A9 A8 A19 A20 WE RESET A21 WP/ACC RD/BY A18 A17 A7 A6 A5 A4 A3 A2 A1 NC NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 56-pin TSOP1 Standard Type 14mm x 20mm 4 NC NC A16 NC VSS DQ15 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VCC DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 OE VSS CE A0 NC VCCQ Revision 1.1 June 2007 K8Q2815UQB K8Q2815UQB FLASH MEMORY FUNCTIONAL BLOCK DIAGRAM Bank 0 Address Vcc X Dec Bank 0 Cell Array Y Dec Latch & Control Y Dec Vccq Latch & Control Vss CE OE WE RESET RY/BY I/O Interface & Bank Control Bank 1 Address X Dec Bank 1 Cell Array Bank 7 Address X Dec Bank 7 Cell Array WP/ACC Y Dec Latch & Control A0~A22 Erase Control DQ0~DQ15 Block Inform 5 Program Control High Voltage Gen. Revision 1.1 June 2007 K8Q2815UQB K8Q2815UQB FLASH MEMORY ORDERING INFORMATION K8 Q 28 15 U Q B - P I 4B Access Time 4B = 60ns/25ns 4C = 65ns/25ns 4D = 70ns/30ns Operating Temperature Range C = Commercial Temp. (0 °C to 70 °C) I = Industrial Temp. (-40 °C to 85 °C) E = Extended Temp. (-25 °C to 85 °C) Samsung NOR Flash Memory Device Type Page Mode DDP Package P = 56 Pin TSOP (Lead Free) Density & Bank Architecture 128 Mbits, 8 Banks Organization x16 Version 3rd Generation Block Architecture Q = Top and Bottom Boot Block (for each chip) Operating Voltage Range 2.7V to 3.6V Table 1. PRODUCT LINE-UP Speed Option Speed Item 4B Vcc 4C 4D 2.7V~3.6V Vccq (1) 1.65~1.95V , 2.7~3.6V Max. Address Access Time (ns) 60ns 65ns 70ns Max. CE Access Time (ns) 60ns 65ns 70ns Max. OE Access Time (ns) 25ns 25ns 30ns Max. Page Access Time (ns) 25ns 25ns 30ns Notes : 1. Only 4C or 4D speed options can be provided in case of using 1.65~1.95V Vccq. Table 2. K8Q2815UQB K8Q2815UQB DEVICE BANK DIVISIONS Bank 0, Bank 3,Bank 4, Bank 7 Bank 1, Bank 2, Bank 5, Bank 6 Mbit Block Sizes Mbit Block Sizes 8 Mbit 4 Kw x 8 and 32 Kw x 15 24 Mbit 32 Kw x 48 Table 3. OTP BLOCK (Chip 1, A22='0') Block Address A21~A8 0000h Block Size Address Range Factory-Locked Area 128 words 000000h-00007Fh Customer-Locked Area OTP Area 128 words 000080h-0000FFh After entering OTP block, any issued addresses should be in the range of OTP block address 6 Revision 1.1 June 2007 K8Q2815UQB K8Q2815UQB FLASH MEMORY Table 4. K8Q2815UQB K8Q2815UQB DEVICE BANK DIVISIONS Bank Number of Blocks Block Size 8 4 Kwords 15 32 Kwords 1 48 32 Kwords 2 48 32 Kwords 15 32 Kwords 8 4 Kwords 8 4 Kwords 15 32 Kwords 5 48 32 Kwords 6 48 32 Kwords 15 32 Kwords 8 4 Kwords 0 3 4 7 Notes : 1. K8Q2815UQB K8Q2815UQB is consist of two 64Mb. 2. Boot block is located in Bank 0, Bank 3, Bank 4, Bank 7 7 Revision 1.1 June 2007 K8Q2815UQB K8Q2815UQB FLASH MEMORY PRODUCT INTRODUCTION The K8Q2815UQB K8Q2815UQB is an 128Mbit NOR-type Flash memory. The device features single voltage power supply operating within the range of 2.7V to 3.6V. The device is programmed by using the Channel Hot Electron (CHE) injection mechanism which is used to program EPROMs. The device is erased electrically by using Fowler-Nordheim tunneling mechanism. To provide highly flexible erase and program capability, the device adapts a block memory architecture that divides its memory array into 284 blocks (4 Kw x 32 , 32 Kw x 252). Programming is done in units of 16 bits (Word). All bits of data in one or multiple blocks can be erased simultaneously when the device executes the erase operation. To prevent the device from accidental erasing or over-writing the programmed data, 284 memory blocks can be hardware protected. The device offers fast page access time of 20~30ns with random access time of 60~70ns supporting high speed microprocessors to operate without any wait states. The command set of K8Q2815UQB K8Q2815UQB is fully compatible with standard Flash devices. The device is controlled by chip enable (CE), output enable (OE) and write enable (WE). Device operations are executed by selective command codes. The command codes to be combined with addresses and data are sequentially written to the command registers using microprocessor write timing. The command codes serve as inputs to an internal state machine which controls the program/erase circuitry. Register contents also internally latch addresses and data necessary to execute the program and erase operations. The K8Q2815UQB K8Q2815UQB is implemented with Internal Program/Erase Algorithms to execute the program/erase operations. The Internal Program/Erase Algorithms are invoked by program/erase command sequences. The Internal Program Algorithm automatically programs and verifies data at specified addresses. The Internal Erase Algorithm automatically pre-programs the memory cell which is not programmed and then executes the erase operation. The K8Q2815UQB K8Q2815UQB has means to indicate the status of completion of program/erase operations. The status can be indicated via the RY/BY pin, Data polling of DQ7, or the Toggle bit (DQ6). Once the operations have been completed, the device automatically resets itself to the read mode. Table 5. Operations Table Operation Read CE OE WE WP/ ACC A22 A9 A6 A1 A0 DQ8/ DQ15 DQ0/ DQ7 RES ET L L H L/H L/H A9 A6 A1 A0 DOUT DOUT H Vcc ± 0.2V X X (2) L/H X X X X High-Z High-Z (2) Output Disable L H H L/H L/H X X X X High-Z High-Z H Reset X X X L/H L/H X X X X High-Z High-Z L Write L H L (4) L/H A9 A6 A1 A0 DIN DIN H Stand-by Enable Block Protect (3) L H L L/H L/H X L H L X DIN VID Enable Block Unprotect (3) L H L (4) L/H X H H L X DIN VID Temporary Block Unprotect X X X (4) L/H X X X X X X VID Auto Select Manufacturer ID (5) L L H L/H L VID L L L X L L H L/H L VID L L H X Auto Select Device Code (5) Code(See Table 7) Code(See Table 7) H H Notes : 1. L = VIL (Low), H = VIH (High), VID = 8.5V to 9.5V, DIN = Data in, DOUT = Data out, X = Don't care. 2. WP/ACC and RESET pin are asserted at Vcc±0.2 V or Vss±0.2 V in the Stand-by mode. 3. Addresses must be composed of the Block address (A12 - A22). The Block Protect and Unprotect operations may be implemented via programming equipment too. Refer to the "Block Protection and Unprotection". 4. If WP/ACC=VIL, the two outermost boot blocks is protected. If WP/ACC=VIH, the two outermost boot block protection depends on whether those blocks were last protected or unprotected using the method described in "Block Protection and Unprotection". If WP/ACC=VHH, all blocks will be temporarily unprotected. 5. Manufacturer and device codes may also be accessed via a command register write sequence. Refer to Table 7. Manufacturer and device codes can be read by A22=L only. (Chip1) 6. A22 is working as virtual CE of 2nd chip 1st Chip Enable Condition : CE - "L", A22 - "L" 2nd Chip Enable Condition : CE - "L", A22 - "H" 8 Revision 1.1 June 2007 K8Q2815UQB K8Q2815UQB FLASH MEMORY COMMAND DEFINITIONS The K8Q2815UQB K8Q2815UQB operates by selecting and executing its operational modes. Each operational mode has its own command set. In order to select a certain mode, a proper command with specific address and data sequences must be written into the command register. Writing incorrect information which include address and data or writing an improper command will reset the device to the read mode. The defined valid register command sequences are stated in Table 6. Note that Erase Suspend (B0H) and Erase Resume (30H) commands are valid only while the Block Erase Operation is in progress. Program Suspend (B0H) and Program Resume (30H) commands are valid during Program Operation and Erase Suspend - Program Operation. Only Read Operation is available after Program Suspend Operation. A22 has to be fixed whenever command is issued to the device in order to select one chip of the whole chip. For example, when A22 is Low, 1st chip is selected. And when A22 is High, : 2nd chip is selected. Table 6. Command Sequences Command Sequence Read Reset Cycle Addr Data Addr Data Autoselect Manufacturer ID (1,2) Addr Autoselect Device Code (1,2,3) Addr Autoselect Block Protect Verify (1,2) Addr Autoselect OTP Factory Protect Addr Program Unlock Bypass (14) Data Data Data Data Addr Data Addr Data Unlock Bypass Program (14) Addr Unlock Bypass Block Erase (14) Addr Unlock Bypass Chip Erase (14) Addr Unlock Bypass Reset (14) Unlock Bypass CFI (14) Chip Erase Block Erase Block Erase Suspend (4, 5) Block Erase Resume Program Suspend (6,7) Program Resume CFI Query (8) Data Data Data Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data 1 1 4 4 4 4 4 3 2 2 2 2 1 6 6 1 1 1 1 1 1st Cycle 2nd Cycle 3rd Cycle 4th Cycle 5th Cycle 6th Cycle 555H 2AAH DA/555H DA/555H DA/X00H DA/X00H AAH 55H 90H ECH 555H 2AAH DA/555H DA/555H AAH 55H 90H DA/X01H DA/X01H DA/X0EH DA/X0FH 257EH 257EH 2506H 2506H 555H 2AAH DA/555H DA/555H BA / X02H 2501H 2501H AAH 55H 90H (See Table 7) 555H 2AAH DA/555H DA/555H X03H AAH 55H 90H (See Note 10) 555H 2AAH 555H PA AAH 55H A0H PD 555H 2AAH 555H 20H RA RD (See Note13) F0H AAH 55H XXXH PA A0H PD XXXH BA 80H 30H XXXH XXXH 80H 10H XXXH XXXH 90H 00H XXH 98H 555H 2AAH 555H 555H 2AAH 555H AAH 55H 80H AAH 55H 10H 555H 2AAH 555H 555H 2AAH BA AAH 55H 80H AAH 55H 30H DA B0H DA 30H DA B0H DA 30H 55H 98H 9 Revision 1.1 June 2007 K8Q2815UQB K8Q2815UQB FLASH MEMORY Table 6. Command Sequences (Continued) Command Definitions Cycle Addr Accelerated Program Addr Addr Enter OTP Block Region (15) Addr Exit OTP Block Region (15) Addr OTP Protection bit Program (11,12,15) Addr OTP Protection bit Status (15) PD PA1 PA2 PA3 PA4 PD2 PD3 PD4 555H 2AAH 555H AAH 55H 88H 555H 2AAH 555H XXX AAH 55H 90H 00H 555H 2AAH 555H OW OW OW AAH 55H 60H 68H 48H RD(0) 555H 2AAH 555H OW OW AAH 55H 60H 48H RD(0) 5 Data 6th Cycle PD1 6 Data 5th Cycle A5H 4 Data 4th Cycle XXXH 3 Data 3rd Cycle PA A0H 5 Data 2nd Cycle XXH 2 Data Quadruple word Accelerated Program(9) 1st Cycle Notes : · RA : Read Address, PA : Program Address, RD : Read Data, PD : Program Data · DA : Bank Address (A20- A22), BA : Block Address (A12 - A22), ABP : Address of the block to be protected or unprotected, X = Don't care . · OW = Address (A7:A0) is (00011010), RD(0) = Read Data DQ0 for protection indicator bit ,RD(1) = Read Data DQ1 for PPB Lock status. · DQ8 - DQ15 are don't care in command sequence, except for RD and PD. · A11 - A21 are also don't care, except for the case of special notice. (A22 have to be fixed to '0' or '1') 1. To terminate the Autoselect Mode, it is necessary to write Reset command to the register. 2. The 4th cycle data of Autoselect mode is output data. The 3rd and 4th cycle bank addresses of Autoselect mode must be same. Manufacturer and device codes can be read by A22=L only. (Chip1) 3. Device ID must be read across cycles 4, 5 and 6. K8Q2815UQB K8Q2815UQB (xOEh = 2506h, x0Fh = 2501h), K8Q2815UQB K8Q2815UQB ID is same with 64Mb ID (K8P6415UQB K8P6415UQB) 4. The Read / Program operations at non-erasing blocks and the autoselect mode are allowed in the Erase Suspend mode. 5. The Erase Suspend command is applicable only to the Block Erase operation. 6. The Read Operation is allowed in the Program Suspend mode. 7. The Program Suspend command is applicable to Program and Erase Suspend - Program operation. 8. Command is valid when the device is in read mode or Autoselect mode. CFI information can be read by A22=L only. (Chip1) 9. Quadruple word accelerated program is invoked only at Vpp=Vid, Vpp setup is required prior to this command sequence. PA1,PA2,PA3,PA4 have the same A22~A2 address 10. The data is DQ6=1 for customer locked and DQ7=1 for factory locked. 11. Reset command returns device to reading array. 12. Cycle 4 programs the addressed locking bit. Cycle 5 and 6 validate bit has been fully programmed when DQ0=1. If DQ0=0 in cycle 6, program command must be issued and verified again. 13. All addresses are don't care except A22. A22 has to be fixed to select each chip. (A22 = L : Chip1, A22 = H : Chip2) 14. One unlock bypass command is valid on one chip. To enable unlock bypass function in all chips, unlock bypass command should be invoked on each chip. 15. OTP block command is valid on chip1 only. (A22 has to be fixed to A22 = L) Table 7. K8Q2815UQB K8Q2815UQB Autoselect Codes, (High Voltage Method) Description Manufacturer ID CE OE WE A22 to A12 A10 A9 A8 A7 A6 A5 to A4 A3 A2 A1 A0 DQ15 to DQ7 to DQ0 L L H DA X VID X L L X L L L L X ECH L L L H 25H 7EH H H H L 25H 06H H H H H 25H 01H Read Cycle 1 Devi ce ID Read Cycle 2 L L H DA X VID X L L L Read Cycle 3 Block Protection Verification OTP Indicator Bit (DQ7. DQ6) Master locking bit Indicator Bit Notes : L L H BA X VID X L L L L L H L X 01H (Proected) 00H (Unproteced) L L H DA X VID X X L L L L H H X DQ7=1(Factory locked) DQ6=1(Customer locked) L L H BA X VID X L L L L H H H X 01H(Protected) 00H (Unproteced) 1. L=Logic Low=VIL, H=Logic High=VIH, DA= Bank Address, BA=Block Address, X=Don't care. 10 Revision 1.1 June 2007 K8Q2815UQB K8Q2815UQB FLASH MEMORY DEVICE OPERATION Read Mode The K8Q2815UQB K8Q2815UQB is controlled by Chip Enable (CE), Output Enable (OE) and Write Enable (WE). When CE and OE are low and WE is high, the data stored at the specified address location,will be the output of the device. The outputs are in high impedance state whenever CE or OE is high. The K8Q2815UQB K8Q2815UQB is available for Page mode. Page mode provides fast access time for high performance system. Standby Mode The K8Q2815UQB K8Q2815UQB features Stand-by Mode to reduce power consumption. This mode puts the device on hold when the device is deselected by making CE high (CE = VIH). Refer to the DC characteristics for more details on stand-by modes. Output Disable The device outputs are disabled when OE is High (OE = VIH). The output pins are in high impedance state. Automatic Sleep Mode The K8Q2815UQB K8Q2815UQB features Automatic Sleep Mode to minimize the device power consumption. When addresses remain steady for tAA+30ns, the device automatically activates the Automatic Sleep Mode. In the sleep mode, output data is latched and always available to the system. When addresses are changed, the device provides new data without wait time. tAA + 30ns Address Outputs Data Data Data Data Data Data Auto Sleep Mode Figure 1. AutoSleep Mode Operation Autoselect Mode The K8Q2815UQB K8Q2815UQB offers the Autoselect Mode to identify manufacturer, device type and block protection verification by reading a binary code. The Autoselect Mode allows programming equipment to automatically match the device to be programmed with its corresponding programming algorithm. In addition, this mode allows the verification of the status of write protected blocks. This mode is used by two method. The one is high voltage method to be required VID (8.5V - 9.5V) on address pin A9. When A9 is held at VID and the bank address or block address is asserted, the device outputs the valid data via DQ pins(see Table 7 and Figure 2). The rest of addresses except A0, A1 and A6 are dont care. The other is autoselect command method that the autoselect code is accessable by the commamd sequence without VID. The manufacturer, device code and block protection verification can be read via the command register. The Command Sequence is shown in Table 7 and Figure 3. The autoselect operation of block protection verification is initiated by first writing two unlock cycle. The third cycle must contain the bank address and autoselect command (90H). If Block address while (A6, A1, A0) = (0,1,0) is finally asserted on the address pin, it will produce a logical "1" at the device output DQ0 to indicate a write protected block or a logical "0" at the device output DQ0 to indicate a write unprotected block. To terminate the autoselect operation, write Reset command (F0H) into the command register. Note that Manufacturer and Device codes in the Autoselect mode can be read by A22=L only. (Chip1) 11 Revision 1.1 June 2007 K8Q2815UQB K8Q2815UQB FLASH MEMORY VID V = VIH or VIL A9 A6,A1,A0* DQ15-DQ0 DQ15-DQ0 0EH 01H 00H ECH 0FH 2506H 2506H 257EH 257EH Manufacturer ID 2501H 2501H Device ID (K8Q2815UQB K8Q2815UQB is same with K8P6415UQB K8P6415UQB) Return to Read Mode Note : The addresses other than A0 , A1 and A6 are Dont care. Please refer to Table 7 for device code. Figure 2. Autoselect Operation ( by High Voltage Method ) WE Address DQ15DQ0 DQ15DQ0 555H 2AAH 555H ECH 90H 55H AAH 0EH 01H 00H 257EH 257EH 0FH 2501H 2501H 2506H 2506H Manufacturer ID Device ID (K8Q2815UQB K8Q2815UQB is same with K8P6415UQB K8P6415UQB) Note : The 3rd Cycle and 4th Cycle address must include the same bank address. Please refer to Table 7 for device code. Figure 3. Autoselect Operation ( by Command Sequence Method ) Write (Program/Erase) Mode The K8Q2815UQB K8Q2815UQB executes its program/erase operations by writing commands into the command register. In order to write the commands to the register, CE and WE must be low and OE must be high. Addresses are latched on the falling edge of CE or WE (whichever occurs last) and the data are latched on the rising edge of CE or WE (whichever occurs first). The device uses standard microprocessor write timing. Program The K8Q2815UQB K8Q2815UQB can be programmed in units of a word. Programming is writing 0's into the memory array by executing the Internal Program Routine. In order to perform the Internal Program Routine, a four-cycle command sequence is necessary. The first two cycles are unlock cycles. The third cycle is assigned for the program setup command. In the last cycle, the address of the memory location and the data to be programmed at that location are written. The device automatically generates adequate program pulses and verifies the programmed cell margin by the Internal Program Routine. During the execution of the Routine, the system is not required to provide further controls or timings. During the Internal Program Routine, commands written to the device will be ignored. Note that a hardware reset during a program operation will cause data corruption at the corresponding location. WE Address DQ15-DQ0 DQ15-DQ0 555H 2AAH 555H AAH 55H Program Address A0H Program Data Program Start RY/BY Figure 4. Program Command Sequence 12 Revision 1.1 June 2007 K8Q2815UQB K8Q2815UQB FLASH MEMORY In accross block boundaries and any sequence programming is allowed. A bit cannot be programmed from '0' back to '1'. If attempting to do, it may cause that bank to set DQ5 = 1, or cause the DQ7 and DQ6 status bits to indicate the operation was successful. However, a succeeding read will show that the data is still '0'. Only erase operations can convert a '0' to a '1'. Unlock Bypass The K8Q2815UQB K8Q2815UQB provides the unlock bypass mode to save its operation time. This mode is possible for program, block erase and chip erase operation. There are two methods to enter the unlock bypass mode. The mode is invoked by the unlock bypass command sequence. Unlike the standard program/erase command sequence that contains four to six bus cycles, the unlock bypass program/ erase command sequence comprises only two bus cycles. The unlock bypass mode is engaged by issuing the unlock bypass command sequence which is comprised of three bus cycles. Writing first two unlock cycles is followed by a third cycle containing the unlock bypass command (20H). Once the device is in the unlock bypass mode, the unlock bypass program/erase command sequence is necessary. The unlock bypass program command sequence is comprised of only two bus cycles; writing the unlock bypass program command (A0H) is followed by the program address and data. This command sequence is the only valid one for programming the device in the unlock bypass mode. Also, The unlock bypass erase command sequence is comprised of two bus cycles; writing the unlock bypass block erase command(80H-30H 80H-30H) or writing the unlock bypass chip erase command(80H-10H 80H-10H). This command sequences are the only valid ones for erasing the device in the unlock bypass mode. The unlock bypass reset command sequence is the only valid command sequence to exit the unlock bypass mode. The unlock bypass reset command sequence consists of two bus cycles. The first cycle must contain the data (90H). The second cycle contains only the data (00H). Then, the device returns to the read mode. One unlock bypass command is valid on one chip. To enable unlock bypass function in all chips, unlock bypass command should be invoked on each chip. Chip Erase To erase a chip is to write 1s into the entire memory array by executing the Internal Erase Routine. The Chip Erase requires six bus cycles to write the command sequence. The erase set-up command is written after first two "unlock" cycles. Then, there are two more write cycles prior to writing the chip erase command. The Internal Erase Routine automatically pre-programs and verifies the entire memory for an all zero data pattern prior to erasing. The automatic erase begins on the rising edge of the last WE or CE pulse in the command sequence and terminates when DQ7 is "1". After that the device returns to the read mode. The device does not support 'full chip erase'. Only 'half chip erase' by selecting A22 to "0" or "1" is available. WE Address DQ15-DQ0 DQ15-DQ0 555H 2AAH AAH 555H 55H 555H 80H 2AAH AAH 555H 55H 10H Chip Erase Start RY/BY Figure 5. Chip Erase Command Sequence Block Erase To erase a block is to write 1s into the desired memory block by executing the Internal Erase Routine. The Block Erase requires six bus cycles to write the command sequence shown in Table 6. After the first two "unlock" cycles, the erase setup command (80H) is written at the third cycle. Then there are two more "unlock" cycles followed by the Block Erase command. The Internal Erase Routine automatically pre-programs and verifies the entire memory prior to erasing it. The block address is latched on the falling edge of WE or CE, while the Block Erase command is latched on the rising edge of WE or CE. Multiple blocks can be erased sequentially by writing the six bus-cycle operation in Figure 6. Upon completion of the last cycle for the Block Erase, additional block address and the Block Erase command (30H) can be written to perform the Multi-Block Erase. An 50us (typical) "time window" is required between the Block Erase command writes. The Block Erase command must be written within the 50us "time window", otherwise the Block Erase command will be ignored. The 50us "time window" is reset when the falling edge of the WE occurs within the 50us of "time window" to latch the Block Erase command. During the 50us of "time window", any command other than the Block Erase or the Erase Suspend command written to the device will reset the device to read mode. After the 50 us of "time window", the Block Erase command will initiate the Internal Erase Routine to erase the selected blocks. Any Block Erase address and command following the exceeded "time window" may or may not be accepted. No other commands will be recognized except the Erase Suspend command. Note : It is not possible to do multi-block erase over two chips. (Chip1 : Bank 0 ~ Bank 3, Chip2 : Bank 4 ~ Bank 7) 13 Revision 1.1 June 2007 K8Q2815UQB K8Q2815UQB FLASH MEMORY WE Address 555H DQ15-DQ0 DQ15-DQ0 2AAH AAH 555H 555H 80H 55H 2AAH AAH Block Address 55H 30H Block Erase Start RY/BY Figure 6. Block Erase Command Sequence Erase Suspend / Resume The Erase Suspend command interrupts the Block Erase to read or program data in a block that is not being erased. The Erase Suspend command is only valid during the Block Erase operation including the time window of 50us. The Erase Suspend command is not valid while the Chip Erase or the Internal Program Routine sequence is running. When the Erase Suspend command is written during a Block Erase operation, the device requires a maximum of 20us to suspend the erase operation. But, when the Erase Suspend command is written during the block erase time window (50us), the device immediately terminates the block erase time window and suspends the erase operation. After the erase operation has been suspended, the device is availble for reading or programming data in a block that is not being erased. The system may also write the autoselect command sequence when the device is in the Erase Suspend mode. When the Erase Resume command is executed, the Block Erase operation will resume. When the Erase Suspend or Erase Resume command is executed, the addresses are in Don't Care state. WE Address DQ15-DQ0 DQ15-DQ0 555H Block Address AAH Block Erase Command Sequence XXXH 30H XXXH B0H Block Erase Start Erase Suspend 30H Erase Resume Figure 7. Erase Suspend/Resume Command Sequence Program Suspend / Resume The Program Suspend command interrupts the Program operation. Also the Program Suspend command interrupts the Program operation during Erase Suspend Mode. The Read operation is available only during Program Suspend. When the Program Suspend command is written during a Program operation, the device requires a maximum of 10us to suspend the Program operation. The system may also write the autoselect command sequence when the device is in the Program Suspend mode. When the Program Resume command is executed, the Program operation will resume. When the Program Suspend or Program Resume command is executed, the addresses are in Don't Care state. 14 Revision 1.1 June 2007 K8Q2815UQB K8Q2815UQB FLASH MEMORY Read While Write The K8Q2815UQB K8Q2815UQB provides multi-bank memory architecture that divides the memory array into four banks. The device is capable of reading data from one bank and writing data to the other bank simultaneously. This is so called the Read While Write operation with multi-bank architecture; this feature provides the capability of executing the read operation during Program/Erase or Erase-SuspendProgram operation. The Read While Write operation is prohibited during the chip erase operation. It is also allowed during erase operation when either single block or multiple blocks from same bank are loaded to be erased. It means that the Read While Write operation is prohibited when blocks from one Bank and another blocks from the other Bank are loaded all together for the multi-block erase operation. Write Protect (WP) The WP/ACC pin has two useful functions. The one is that certain boot block is protected by the hardware method not to use VID. The other is that program operation is accelerated to reduce the program time (Refer to Accelerated program Operation Paragraph). When the WP/ACC pin is asserted at VIL, the device can not perform program and erase operation in the two "outermost" 4Kword boot blocks on both ends of the flash array independently of whether those blocks were protected or unprotected using the method described in "Block protection/Unprotection". (BA0 and BA1, BA140 BA140 and BA141 BA141 for chip1), (BA142 BA142 and BA143 BA143, BA282 BA282 and BA283 BA283 for chip2) The write protected blocks can only be read. This is useful method to preserve an important program data. When the WP/ACC pin is asserted at VIH, the device reverts to whether the two outermost 4Kword boot blocks were last set to be protected or unprotected. That is, block protection or unprotection for these two blocks depends on whether they were last protected or unprotected using the method described in "Block protection/unprotection". Recommend that the WP/ACC pin must not be in the state of floating or unconnected, otherwise the device may be led to malfunction. Software Reset The reset command provides that the bank is reseted to read mode or erase-suspend-read mode. The addresses are in Don't Care state except A22. A22 has to be fixed to '0' or '1'. The reset command is vaild between the sequence cycles in an erase command sequence before erasing begins, or in a program command sequence before programming begins. This resets the bank in which was operating to read mode. if the device is be erasing or programming, the reset command is invalid until the operation is completed. Also, the reset command is valid between the sequence cycles in an autoselect command sequence. In the autoselect mode, the reset command returns the bank to read mode. If a bank entered the autoselect mode in the Erase Suspend mode, the reset command returns the bank to erase-suspend-read mode. If DQ5 is high on erase or program operation, the reset command return the bank to read mode or erase-suspend-read mode if the bank was in the Erase Suspend state. Hardware Reset The K8Q2815UQB K8Q2815UQB offers a reset feature by driving the RESET pin to VIL. The RESET pin must be kept low (VIL) for at least 500ns. When the RESET pin is driven low, any operation in progress will be terminated and the internal state machine will be reset to the standby mode after 20us. If a hardware reset occurs during a program operation, the data at that particular location will be lost. Once the RESET pin is taken high, the device requires 200ns of wake-up time until outputs are valid for read access. Also, note that all the data output pins are tri-stated for the duration of the RESET pulse. The RESET pin may be tied to the system reset pin. If a system reset occurs during the Internal Program and Erase Routine, the device will be automatically reset to the read mode ; this will enable the systems microprocessor to read the boot-up firmware from the Flash memory. 15 Revision 1.1 June 2007 K8Q2815UQB K8Q2815UQB FLASH MEMORY Power-up Protection To avoid initiation of a write cycle during Vcc Power-up, RESET low must be asserted during power-up. After RESET goes high, the device is reset to the read mode. Low Vcc Write Inhibit To avoid initiation of a write cycle during Vcc power-up and power-down, a write cycle is locked out for Vcc less than 2.3V. If Vcc < VLKO (Lock-Out Voltage), the command register and all internal program/erase circuits are disabled. Under this condition the device will reset itself to the read mode. Subsequent writes will be ignored until the Vcc level is greater than VLKO. It is the users responsibility to ensure that the control pins are logically correct to prevent unintentional writes when Vcc is above 2.3V. Write Pulse Glitch Protection Noise pulses of less than 5ns(typical) on CE, OE, or WE will not initiate a write cycle. Logical Inhibit Writing is inhibited under any one of the following conditions : OE = VIL, CE = VIH or WE = VIH. To initiate a write, CE and WE must be "0", while OE is "1". Commom Flash Memory Interface Common Flash Momory Interface is contrived to increase the compatibility of host system software. It provides the specific information of the device, such as memory size, word configuration, and electrical features. Once this information has been obtained, the system software will know which command sets to use to enable flash writes, block erases, and control the flash component. When the system writes the CFI command(98H) to address 55H in word mode, the device enters the CFI mode. And then if the system writes the address shown in Table 11, the system can read the CFI data. Query data are always presented on the lowest-order data outputs(DQ0-7) only. In word(x16) mode, the upper data outputs(DQ8-15 DQ8-15) is 00h. To terminate this operation, the system must write the reset command. Note that CFI information can be read by A22=L only. (Chip1) OTP Block Region The OTP Block feature provides a 256-word Flash memory region that enables permanent part identification through an Electronic Serial Number (ESN). The OTP Block is customer lockable and shipped with itself unlocked, allowing customers to untilize the that block in any manner they choose. Indicator bits DQ6 and DQ7 are used to indicate the factory-locked and customer locked status of the part. The data is DQ6 = "1" for customer locked and DQ7 = "1" for factory locked. The system accesses the OTP Block through a command sequence (see "Enter OTP Block / Exit OTP Block Command sequence" at Table 6). After the system has written the "Enter OTP Block" Command sequence, it may read the OTP Block by using the addresses (000000h~0000FFh) normally and may check the Protection Verify Bit (DQ7,DQ6) by using the "Autoselect Block Protection Verify" Command sequence with OTP Block address. This mode of operation continues until the system issues the "Exit OTP Block" Command suquence, a hardware reset or until power is removed from the device. On power-up, or following a hardware reset, the device reverts to sending commands to main blocks. Note that the Accelerated function and unlock bypass modes are not available when the OTP Block is enabled. Customer Lockable In a Customer lockable device, The OTP Block is one-time programmable and can be locked only once. Note that the Accelerated programming and Unlock bypass functions are not available when programming the OTP Block. Locking operation to the OTP Block is started by writing the "Enter OTP Block" Command sequence, and it can be permanently locked to "1" by issuing the OTP Protection bit program Command sqeunce. Once the OTP block is locked and verified, the system must write the Exit OTP block command to return to reading and writing the remainder of the array. OTP Protection Bits OTP protection bits prevent programming of the OTP block memory area. Once set, the OTP area are non-modifiable. · The OTP Block Lock operation must be used with caution since, once locked, there is no procedure available for unlocking and none of the bits in the OTP Block space can be modified in any way. · Suspend and resume operation are not supported during OTP protect, nor is OTP protect supported during any suspend operation. 16 Revision 1.1 June 2007 K8Q2815UQB K8Q2815UQB FLASH MEMORY High Voltage Block Protection Block protection and unprotection may also be implemented using programming equipment. The procedure requires high voltage (Vid) to be placed on the RESET# pin. Refer to Figure 8 for details on this procedure. Note that for block unprotect, all unprotected blocks must first be protected prior to the first sector write cycle. Accelerated Program Operation Accelerated program operation is one of two functions provided by the WP/ACC pin. When the WP/ACC pin is asserted as VHH, the device automatically enters the Unlock Bypass mode, temporarily unprotecting any protected blocks. The system would use a twocycle program command sequence as required by the Unlock Bypass mode. Removing VHH from the WP/ACC pin returns the device to normal operation. Recommend that the WP/ACC pin must not be asserted at VHH except on accelerated program operation, or the device may be damaged. In addition, the WP/ACC pin must not be in the state of floating or unconnected, otherwise the device may be led to malfunction. Single word accelerated program operation The system would use two-cycle program sequence (One-cycle (XXX - A0H) is for single word program command, and Next onecycle (PA - PD) is for program address and data ). Quadruple word accelerated program operation As well as Single word accelerated program, the system would use five-cycle program sequence (One-cycle (XXX - A5H) is for quadruple word program command, and four cycles are for program address and data). · · · · Only four words programming is possible Each program address must have the same A22~A2 address The device automatically generates adequate program pulses and ignores other command after program command Program/Erase cycling must be limited below 100cycles for optimum performance. · Read while Write mode is not guaranteed Requirements : Ambient temperature : TA=30°C±10°C 17 Revision 1.1 June 2007 K8Q2815UQB K8Q2815UQB FLASH MEMORY START COUNT = 1 RESET=VID Wait 4µs First Write Cycle=60h? No Temporary Block Group Unprotect Mode Yes Yes Block Group Protection ? No Block Protect Algorithm No Set up Block Group address All Block Groups Protected ? Yes Block Unprotect Algorithm Block Group , i= 0 Block Group Unprotect Write 60H with A6=1,A1=1 A0=0 Block Group Protect: Write 60H to Block Group address with A6=0,A1=1 A0=0 Wait 3ms Wait 120µs Verify Block Group Protect:Write 40H to Block Group address with A6=0, A1=1,A0=0 Increment COUNT No COUNT =1000? Yes Yes Yes Device failed Read from Block Group address with A6=1, A1=1,A0=0 No Data=01h? Protect another Block Group? Verify Block Group Unprotect:Write 40H to Block Group address with A6=1, A1=1,A0=0 Increment COUNT Read from Block Group address with A6=0, A1=1,A0=0 No COUNT =25? Reset COUNT=1 Device failed No Set up next Block Group address Data=00h? Yes Last Block Group verified ? No Yes Yes Remove VID from RESET No Remove VID from RESET Write RESET command Write RESET command END END Note : All blocks must be protected before unprotect operation is executing. Figure 8. Block Group Protection & Unprotection Algorithms 18 Revision 1.1 June 2007 K8Q2815UQB K8Q2815UQB FLASH MEMORY Table 8. Block Protection Schemes DYB PPB PPB Lock Block State 0 0 0 Unprotected-PPB and DYB are changeable 0 0 1 Unprotected-PPB not changeable and DYB are changeable 0 1 0 1 0 0 1 1 0 0 1 1 1 0 1 1 1 1 Protected-PPB and DYB are changeable Protected-PPB not changeable, DYB is changeable Block Protection The K8Q2815UQB K8Q2815UQB features several levels of block protection, which can disable both the program and erase operations in certain blocks or block groups: Persistent Block Protection A command block protection method that replaces the old 12 V controlled protection method. Password Block Protection A highly sophisticated protection method that requires a password before changes to certain blocks or block groups are permitted Selecting a Block Protection Mode All parts default to operate in the Persistent Block Protection mode. The customer must then choose if the Persistent or Password Protection method is most desirable. There are two one-time programmable non-volatile bits that define which block protectionmethod will be used. If the Persistent Block Protection method is desired, programming the Persistent Block Protection Mode Locking Bit permanently sets the device to the Persistent Block Protection mode. If the Password Block Protection method is desired, programming the Password Mode Locking Bit permanently sets the device to the Password Block Protection mode. It is not possible to switch between the two protection modes once a locking bit has been set. One of the two modes must be selected when the device is first programmed. This prevents a program or virus from later setting the Password Mode Locking Bit, which would cause an unexpected shift from the default Persistent Block Protection Mode into the Password Protection Mode. The device is shipped with all blocks unprotected. Optional Samsung programming services enable programming and protecting blocks at the factory prior to shipping the device. Contact your local sales office for details. It is possible to determine whether a block is protected or unprotected. See Autoselect Mode for details. Persistent Block Protection The Persistent Block Protection method replaces the 12 V controlled protection method in previous flash devices. This new method provides three different block protection states: Persistently Locked - The block is protected and cannot be changed. Dynamically Locked - The block is protected and can be changed by a simple command. Unlocked - The block is unprotected and can be changed by a simple command. To achieve these states, three types of "bits" are used: Persistent Protection Bit Persistent Protection Bit Lock Persistent Block Protection Mode Locking Bit Persistent Protection Bit (PPB) A single Persistent (non-volatile) Protection Bit is assigned to a maximum four blocks (see the block address tables for specific block protection groupings). All 4 Kword boot-block sectors have individual block Persistent Protection Bits(PPBs) for greater flexibility. Each PPB is individually modifiable through the PPB Write Command. 19 Revision 1.1 June 2007 K8Q2815UQB K8Q2815UQB FLASH MEMORY The device erases all PPBs in parallel. If any PPB requires erasure, the device must be instructed to preprogram all of the block PPBs prior to PPB erasure. Otherwise, a previously erased block PPBs can potentially be over-erased. The flash device does not have a built-in means of preventing block PPBs over-erasure. Persistent Protection Bit Lock (PPB Lock) The Persistent Protection Bit Lock (PPB Lock) is a global volatile bit. When set to "1", the PPBs cannot be changed. When cleared "0", the PPBs are changeable. There is only one PPB Lock bit per device. The PPB Lock is cleared after power-up or hardware reset. There is no command sequence to unlock the PPB Lock. Dynamic Protection Bit (DYB) A volatile protection bit is assigned for each block. After power-up or hardware reset, the contents of all DYBs is "0". Each DYB is individually modifiable through the DYB Write Command. When the parts are first shipped, the PPBs are cleared, the DYBs are cleared, and PPB Lock is defaulted to power up in the cleared state - meaning the PPBs are changeable. When the device is first powered on the DYBs power up cleared (blocks not protected). The Protection State for each sector is determined by the logical OR of the PPB and the DYB related to that block. For the blocks that have the PPBs cleared, the DYBs control whether or not the block is protected or unprotected. By issuing the DYB Write command sequences, the DYBs will be set or cleared, thus placing each block in the protected or unprotected state. These are the so-called Dynamic Locked or Unlocked states. They are called dynamic states because it is very easy to switch back and forth between the protected and unprotected conditions. This allows software to easily protect blocks against inadvertent changes yet does not prevent the easy removal of protection when changes are needed. The DYBs maybe set or cleared as often as needed. The PPBs allow for a more static, and difficult to change, level of protection. The PPBs retain their state across power cycles because they are non-volatile. Individual PPBs are set with a command but must all be cleared as a group through a complex sequence of program and erasing commands. The PPBs are also limited to 100 erase cycles. The PPB Lock bit adds an additional level of protection. Once all PPBs are programmed to the desired settings, the PPB Lock may be set to "1". Setting the PPB Lock disables all program and erase commands to the non-volatile PPBs. In effect, the PPB Lock Bit locks the PPBs into their current state. The only way to clear the PPB Lock is to go through a power cycle. System boot code can determine if any changes to the PPB are needed; for example, to allow new system code to be downloaded. If no changes are needed then the boot code can set the PPB Lock to disable any further changes to the PPBs during system operation. The WP#/ACC write protect pin adds a final level of hardware protection to blocks BA269 BA269 and BA268 BA268, BA0 and BA1. When this pin is low it is not possible to change the contents of these blocks. These blocks generally hold system boot code. The WP#/ACC pin can prevent any changes to the boot code that could override the choices made while setting up block protection during system initialization. For customers who are concerned about malicious viruses there is another level of security - the persistently locked state. To persistently protect a given block or block group, the PPBs associated with that block need to be set to "1". Once all PPBs are programmed to the desired settings, the PPB Lock should be set to "1". Setting the PPB Lock automatically disables all program and erase commands to the Non-Volatile PPBs. In effect, the PPB Lock "freezes" the PPBs into their current state. The only way to clear the PPB Lock is to go through a power cycle. It is possible to have blocks that have been persistently locked, and blocks that are left in the dynamic state. The blocks in the dynamic state are all unprotected. If there is a need to protect some of them, a simple DYB Write command sequence is all that is necessary. The DYB write command for the dynamic blocks switch the DYBs to signify protected and unprotected, respectively. If there is a need to change the status of the persistently locked blocks, a few more steps are required. First, the PPB Lock bit must be disabled by either putting the device through a power-cycle, or hardware reset. The PPBs can then be changed to reflect the desired settings. Setting the PPB lock bit once again will lock the PPBs, and the device operates normally again. The best protection is achieved by executing the PPB lock bit set command early in the boot code, and protect the boot code by holding WP#/ACC = VIL. Table 8 contains all possible combinations of the DYB, PPB, and PPB lock relating to the status of the block. In summary, if the PPB is set, and the PPB lock is set, the block is protected and the protection can not be removed until the next power cycle clears the PPB lock. If the PPB is cleared, the block can be dynamically locked or unlocked. The DYB then controls whether or not the block is protected or unprotected. 20 Revision 1.1 June 2007 K8Q2815UQB K8Q2815UQB FLASH MEMORY If the user attempts to program or erase a protected block, the device ignores the command and returns to read mode. A program command to a protected block enables status polling for approximately 1us before the device returns to read mode without having modified the contents of the protected block. An erase command to a protected block enables status polling for approximately 50us after which the device returns to read mode without having erased the protected block. The programming of the DYB, PPB, and PPB lock for a given block can be verified by writing a DYB/PPB/PPB lock verify command to the device. Persistent Block Protection Mode Locking Bit Like the password mode locking bit, a Persistent Block Protection mode locking bit exists to guarantee that the device remain in software block protection. Once set, the Persistent Block Protection locking bit prevents programming of the password protection mode locking bit. This guarantees that a hacker could not place the device in password protection mode. Password Protection Mode The Password Block Protection Mode method allows an even higher level of security than the Persistent Block Protection Mode. There are two main differences between the Persistent Block Protection and the Password Block Protection Mode: When the device is first powered on, or comes out of a reset cycle, the PPB Lock bit set to the locked state, rather than cleared to the unlocked state. The only means to clear the PPB Lock bit is by writing a unique 64-bit Password to the device. The Password Block Protection method is otherwise identical to the Persistent Block Protection method. A 64-bit password is the only additional tool utilized in this method. Once the Password Mode Locking Bit is set, the password is permanently set with no means to read, program, or erase it. The password is used to clear the PPB Lock bit. The Password Unlock command must be written to the flash, along with a password. The flash device internally compares the given password with the pre-programmed password. If they match, the PPB Lock bit is cleared, and the PPBs can be altered. If they do not match, the flash device does nothing. There is a built-in 2us delay for each "password check." This delay is intended to thwart any efforts to run a program that tries all possible combinations in order to crack the password. Password and Password Mode Locking Bit In order to select the Password block protection scheme, the customer must first program the password. The password may be correlated to the unique Electronic Serial Number (ESN) of the particular flash device. Each ESN is different for every flash device; therefore each password should be different for every flash device. While programming in the password region, the customer may perform Password Verify operations. Once the desired password is programmed in, the customer must then set the Password Mode Locking Bit. This operation achieves two objectives: Permanently sets the device to operate using the Password Protection Mode. It is not possible to reverse this function. Disables all further commands to the password region. All program, and read operations are ignored. Both of these objectives are important, and if not carefully considered, may lead to unrecoverable errors. The user must be sure that the Password Protection method is desired when setting the Password Mode Locking Bit. More importantly, the user must be sure that the password is correct when the Password Mode Locking Bit is set. Due to the fact that read operations are disabled, there is no means to verify what the password is afterwards. If the password is lost after setting the Password Mode Locking Bit, there will be no way to clear the PPB Lock bit. The Password Mode Locking Bit, once set, prevents reading the 64-bit password on the DQ bus and further password programming. The Password Mode Locking Bit is not erasable. Once Password Mode Locking Bit is programmed, the Persistent Block Protection Locking Bit is disabled from programming, guaranteeing that no changes to the protection scheme are allowed. 64-bit Password The 64-bit Password is located in its own memory space and is accessible through the use of the Password Program and Verify commands (see "Password Verify Command"). The password function works in conjunction with the Password Mode Locking Bit, which when set, prevents the Password Verify command from reading the contents of the password on the pins of the device. Write Protect (WP#) The Write Protect feature provides a hardware method of protecting the upper two and lower two blocks without using VID. This function is provided by the WP# pin and overrides the previously discussed "High Voltage Block Protection" section method. 21 Revision 1.1 June 2007 K8Q2815UQB K8Q2815UQB FLASH MEMORY If the system asserts VIL on the WP#/ACC pin, the device disables program and erase functions in the two outermost 4 Kword blocks on both ends of the flash array independent of whether it was previously protected or unprotected. If the system asserts VIH on the WP#/ACC pin, the device reverts the upper two and lower two blocks to whether they were last set to be protected or unprotected. That is, block protection or unprotection for these sectors depends on whether they were last protected or unprotected using the method described in the "High Voltage Block Protection" section. Persistent Protection Bit Lock The Persistent Protection Bit (PPB) Lock is a volatile bit that reflects the state of the Password Mode Locking Bit after power-up reset. If the Password Mode Lock Bit is also set after a hardware reset (RESET# asserted) or a power-up reset, the ONLY means for clearing the PPB Lock Bit in Password Protection Mode is to issue the Password Unlock command. Successful execution of the Password Unlock command clears the PPB Lock Bit, allowing for block PPBs modifications. Asserting RESET#, taking the device through a power-on reset, or issuing the PPB Lock Bit Set command sets the PPB Lock Bit to a "1" when the Password Mode Lock Bit is not set. If the Password Mode Locking Bit is not set, including Persistent Protection Mode, the PPB Lock Bit is cleared after power-up or hardware reset. The PPB Lock Bit is set by issuing the PPB Lock Bit Set command. Once set the only means for clearing the PPB Lock Bit is by issuing a hardware or power-up reset. The Password Unlock command is ignored in Persistent Protection Mode. Master locking bit set This Master locking bit can ensure that protected blocks be permanently unalterable. Master locking bit is non-volatile bit. Master locking bit controls protection status of entire blocks. The usage of the master locking bit command sequence is absolutely required to ensure full protection of data from future alterations. If master locking bit is set ("1"), entire blocks are permanently protected. They are not changed and altered by any future lock/ unlock commands. Anyone who uses this fuction needs much attention. Because there is no way to return to unlock status. Default status of master locking bit is unlock status("0"). If Master locking bit sets on unprotected block, the block still are remaining in status of unprotected block. The unprotected block can be protected by protection command. Note : If user wants to use Password mode / Master locking bit function / PPB lock bit function, it is needed to be set it on each chip. 22 Revision 1.1 June 2007 K8Q2815UQB K8Q2815UQB FLASH MEMORY Table 9. K8Q28K8Q2815UQB K8Q28K8Q2815UQB Boot Block/Block Addresses for Protection / Unprotection (Chip1, A22='0') Block A22-A12 A22-A12 Block Size BA0 00000000000 4 Kwords BA1 00000000001 4 Kwords BA2 00000000010 4 Kwords BA3 00000000011 4 Kwords BA4 00000000100 4 Kwords BA5 00000000101 4 Kwords BA6 00000000110 4 Kwords BA7 00000000111 4 Kwords BA8 00000001XXX 00000001XXX 32 Kwords BA9 00000010XXX 00000010XXX 32 Kwords BA10 00000011XXX 00000011XXX 32 Kwords BA11-BA14 BA11-BA14 000001XXXXX 000001XXXXX 128 (4x32) Kwords BA15-BA18 BA15-BA18 000010XXXXX 000010XXXXX 128 (4x32) Kwords BA19-BA22 BA19-BA22 000011XXXXX 000011XXXXX 128 (4x32) Kwords BA23-BA26 BA23-BA26 000100XXXXX 000100XXXXX 128 (4x32) Kwords BA27-BA30 BA27-BA30 000101XXXXX 000101XXXXX 128 (4x32) Kwords BA31-BA34 BA31-BA34 000110XXXXX 000110XXXXX 128 (4x32) Kwords BA35-BA38 BA35-BA38 000111XXXXX 000111XXXXX 128 (4x32) Kwords BA39-BA42 BA39-BA42 001000XXXXX 001000XXXXX 128 (4x32) Kwords BA43-BA46 BA43-BA46 001001XXXXX 001001XXXXX 128 (4x32) Kwords BA47-BA50 BA47-BA50 001010XXXXX 001010XXXXX 128 (4x32) Kwords BA51-BA54 BA51-BA54 001011XXXXX 001011XXXXX 128 (4x32) Kwords BA55-BA58 BA55-BA58 001100XXXXX 001100XXXXX 128 (4x32) Kwords BA59-BA62 BA59-BA62 001101XXXXX 001101XXXXX 128 (4x32) Kwords BA63-BA66 BA63-BA66 001110XXXXX 001110XXXXX 128 (4x32) Kwords BA67-BA70 BA67-BA70 001111XXXXX 001111XXXXX 128 (4x32) Kwords BA71-BA74 BA71-BA74 010000XXXXX 010000XXXXX 128 (4x32) Kwords BA75-BA78 BA75-BA78 010001XXXXX 010001XXXXX 128 (4x32) Kwords BA79-BA82 BA79-BA82 010010XXXXX 010010XXXXX 128 (4x32) Kwords BA83-BA86 BA83-BA86 010011XXXXX 010011XXXXX 128 (4x32) Kwords BA87-BA90 BA87-BA90 010100XXXXX 010100XXXXX 128 (4x32) Kwords BA91-BA94 BA91-BA94 010101XXXXX 010101XXXXX 128 (4x32) Kwords BA95-BA98 BA95-BA98 010110XXXXX 010110XXXXX 128 (4x32) Kwords BA99-BA102 BA99-BA102 010111XXXXX 010111XXXXX 128 (4x32) Kwords BA103-BA106 BA103-BA106 011000XXXXX 011000XXXXX 128 (4x32) Kwords BA107-BA110 BA107-BA110 011001XXXXX 011001XXXXX 128 (4x32) Kwords BA111-BA114 BA111-BA114 011010XXXXX 011010XXXXX 128 (4x32) Kwords BA115-BA118 BA115-BA118 011011XXXXX 011011XXXXX 128 (4x32) Kwords BA119-BA122 BA119-BA122 011100XXXXX 011100XXXXX 128 (4x32) Kwords BA123-BA126 BA123-BA126 011101XXXXX 011101XXXXX 128 (4x32) Kwords BA127-BA130 BA127-BA130 011110XXXXX 011110XXXXX 128 (4x32) Kwords BA131 BA131 01111100XXX 01111100XXX 32 Kwords BA132 BA132 01111101XXX 01111101XXX 32 Kwords BA133 BA133 01111110XXX 01111110XXX 32 Kwords BA134 BA134 01111111000 4 Kwords BA135 BA135 01111111001 4 Kwords 23 Revision 1.1 June 2007 K8Q2815UQB K8Q2815UQB FLASH MEMORY Table 9. K8Q2815UQB K8Q2815UQB Boot Block/Block Addresses for Protection / Unprotection (Continued) (Chip1, A22='0') Block A22-A12 A22-A12 Block Size BA136 BA136 01111111010 4 Kwords BA137 BA137 01111111011 4 Kwords BA138 BA138 01111111100 4 Kwords BA139 BA139 01111111101 4 Kwords BA140 BA140 01111111110 4 Kwords BA141 BA141 01111111111 4 Kwords 24 Revision 1.1 June 2007 K8Q2815UQB K8Q2815UQB FLASH MEMORY Table 9. K8Q2815UQB K8Q2815UQB Boot Block/Block Addresses for Protection / Unprotection (Chip2, A22='1') Block A22-A12 A22-A12 Block Size BA142 BA142 10000000000 4 Kwords BA143 BA143 10000000001 4 Kwords BA144 BA144 10000000010 4 Kwords BA145 BA145 10000000011 4 Kwords BA146 BA146 10000000100 4 Kwords BA147 BA147 10000000101 4 Kwords BA148 BA148 10000000110 4 Kwords BA149 BA149 10000000111 4 Kwords BA150 BA150 10000001XXX 10000001XXX 32 Kwords BA151 BA151 10000010XXX 10000010XXX 32 Kwords BA152 BA152 10000011XXX 10000011XXX 32 Kwords BA153-BA156 BA153-BA156 100001XXXXX 100001XXXXX 128 (4x32) Kwords BA157-BA160 BA157-BA160 100010XXXXX 100010XXXXX 128 (4x32) Kwords BA161-BA164 BA161-BA164 100011XXXXX 100011XXXXX 128 (4x32) Kwords BA165-BA168 BA165-BA168 100100XXXXX 100100XXXXX 128 (4x32) Kwords BA169-BA172 BA169-BA172 100101XXXXX 100101XXXXX 128 (4x32) Kwords BA173-BA176 BA173-BA176 100110XXXXX 100110XXXXX 128 (4x32) Kwords BA177-BA180 BA177-BA180 100111XXXXX 100111XXXXX 128 (4x32) Kwords BA181-BA184 BA181-BA184 101000XXXXX 101000XXXXX 128 (4x32) Kwords BA185-BA188 BA185-BA188 101001XXXXX 101001XXXXX 128 (4x32) Kwords BA189-BA192 BA189-BA192 101010XXXXX 101010XXXXX 128 (4x32) Kwords BA193-BA196 BA193-BA196 101011XXXXX 101011XXXXX 128 (4x32) Kwords BA197-BA200 BA197-BA200 101100XXXXX 101100XXXXX 128 (4x32) Kwords BA201-BA204 BA201-BA204 101101XXXXX 101101XXXXX 128 (4x32) Kwords BA205-BA208 BA205-BA208 101110XXXXX 101110XXXXX 128 (4x32) Kwords BA209-BA212 BA209-BA212 101111XXXXX 101111XXXXX 128 (4x32) Kwords BA213-BA216 BA213-BA216 110000XXXXX 110000XXXXX 128 (4x32) Kwords BA217-BA220 BA217-BA220 110001XXXXX 110001XXXXX 128 (4x32) Kwords BA221-BA224 BA221-BA224 110010XXXXX 110010XXXXX 128 (4x32) Kwords BA225-BA228 BA225-BA228 110011XXXXX 110011XXXXX 128 (4x32) Kwords BA229-BA132 BA229-BA132 110100XXXXX 110100XXXXX 128 (4x32) Kwords BA233-BA236 BA233-BA236 110101XXXXX 110101XXXXX 128 (4x32) Kwords BA237-BA240 BA237-BA240 110110XXXXX 110110XXXXX 128 (4x32) Kwords BA241-BA244 BA241-BA244 110111XXXXX 110111XXXXX 128 (4x32) Kwords BA245-BA248 BA245-BA248 111000XXXXX 111000XXXXX 128 (4x32) Kwords BA249-BA252 BA249-BA252 111001XXXXX 111001XXXXX 128 (4x32) Kwords BA253-BA256 BA253-BA256 111010XXXXX 111010XXXXX 128 (4x32) Kwords BA257-BA260 BA257-BA260 111011XXXXX 111011XXXXX 128 (4x32) Kwords BA261-BA264 BA261-BA264 111100XXXXX 111100XXXXX 128 (4x32) Kwords BA265-BA268 BA265-BA268 111101XXXXX 111101XXXXX 128 (4x32) Kwords BA269-BA272 BA269-BA272 111110XXXXX 111110XXXXX 128 (4x32) Kwords BA273 BA273 11111100XXX 11111100XXX 32 Kwords BA274 BA274 11111101XXX 11111101XXX 32 Kwords BA275 BA275 11111110XXX 11111110XXX 32 Kwords BA276 BA276 11111111000 4 Kwords BA277 BA277 11111111001 4 Kwords 25 Revision 1.1 June 2007 K8Q2815UQB K8Q2815UQB FLASH MEMORY Table 9. K8Q2815UQB K8Q2815UQB Boot Block/Block Addresses for Protection / Unprotection (Continued) (Chip2, A22='1') Block A22-A12 A22-A12 BA278 BA278 11111111010 Block Size 4 Kwords BA279 BA279 11111111011 4 Kwords BA280 BA280 11111111100 4 Kwords BA281 BA281 11111111101 4 Kwords BA282 BA282 11111111110 4 Kwords BA283 BA283 11111111111 4 Kwords 26 Revision 1.1 June 2007 K8Q2815UQB K8Q2815UQB FLASH MEMORY Table 10. Block Protection Command Sequences Cycl Command Sequence Password Program(1,2) Password Verify(2,4,5) Password Unlock(3,6,7) Addr Data Addr Data Addr Data Addr PPB Program(1,2,8) Master locking bit Set PPB Status All PPB Erase(1,2,9,10) PPB Lock Bit Set PPB Lock Bit Status(11) DYB Write(3) DYB Erase(3) DYB Status(2) PPMLB Program(1,2,8) PPMLB Status(1) SPMLB Program(1,2,8) SPMLB Status(1) Data Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data 4 4 7 6 3 4 6 3 4 4 4 4 6 5 6 5 1st Cycle 2nd Cycle 3rd Cycle 4th Cycle 555H 2AAH 555H XX[0-3]H AAH 55H 38H 2AAH 555H 6th Cycle 7th Cycle PWA[1] PWA[2] PWA[3] PWD[3] PD[0-3] 555H 5th Cycle PWA[0-3] AAH 55H C8H PWD[0-3] 555H 2AAH 555H PWA[0] AAH 55H 28H PWD[0] PWD[1] PWD[2] 555H 2AAH 555H (BA)WP (BA)WP (BA)WP AAH 55H 60H 68H 48H RD(0) 555H 2AAH 555H AAH 55H F1H 555H 2AAH 555H (BA)WP AAH 55H 90H RD(0) 555H 2AAH 555H WP (BA) (BA)WP AAH 55H 60H 60H 40H RD(0) 555H 2AAH 555H AAH 55H 78H 555H 2AAH 555H BA AAH 55H 58H RD(1) 555H 2AAH 555H BA AAH 55H 48H X1H 555H 2AAH 555H BA X0H AAH 55H 48H 555H 2AAH (DA)555H BA AAH 55H 58H RD(0) 555H 2AAH 555H PL PL PL AAH 55H 60H 68H 48H RD(0) 555H 2AAH 555H PL PL AAH 55H 60H 48H RD(0) 555H 2AAH 555H BL BL BL RD(0) AAH 55H 60H 68 48 555H 2AAH 555H BL BL AAH 55H 60H 48 RD(0) Legend: DYB = Dynamic Protection Bit OW = Address (A7:A0) is (00011010) PD[3:0] = Password Data (1 of 4 portions) PPB = Persistent Protection Bit PWA = Password Address. A1:A0 selects portion of password. PWD = Password Data being verified. PL = Password Protection Mode Lock Address (A7:A0) is (00001010) RD(0) = Read Data DQ0 for protection indicator bit. RD(1) = Read Data DQ1 for PPB Lock status. BA = Block Address where security command applies. Address bits Amax:A12 uniquely select any block. BL = Persistent Protection Mode Lock Address (A7:A0) is (00010010) WP = PPB Address (A7:A0) is (00000010) X = Don't care PPMLB = Password Protection Mode Locking Bit SPMLB = Persistent Protection Mode Locking Bit 27 Revision 1.1 June 2007 K8Q2815UQB K8Q2815UQB FLASH MEMORY Notes: · See the description of bus operations. · All values are in hexadecimal. · Shaded cells in table denote read cycles. All other cycles are write operations. · During unlock and command cycles, when lower address bits are 555 or 2AAh as shown in table, address bits higher than A11 (except where BA is required) and data bits higher than DQ7 are don't cares. 1. The reset command returns device to reading array. 2. Cycle 4 programs the addressed locking bit. Cycles 5 and 6 validate bit has been fully programmed when DQ0 = 1. If DQ0 = 0 in cycle 6, program command must be issued and verified again. 3. Data is latched on the rising edge of WE#. 4. Entire command sequence must be entered for each portion of password. 5. Command sequence returns FFh if PPMLB is set. 6. The password is written over four consecutive cycles, at addresses 0-3. 7. A 2us timeout is required between any two portions of password. 8. A 120us timeout is required between cycles 4 and 5. 9. A 3ms timeout is required between cycles 4 and 5. 10. Cycle 4 erases all PPBs. Cycles 5 and 6 validate bits have been fully erased when DQ0 = 0. If DQ0 = 1 in cycle 6, erase command must be issued and verified again. Before issuing erase command, all PPBs should be programmed to prevent PPB overerasure. 11. DQ1 = 1 if PPB locked, 0 if unlocked. 12. A22 has to be fixed whenever command is issued to the device in order to select one chip of the whole chip. For example, when A22 is Low, 1st chip is selected. And when A22 is High, : 2nd chip is selected. 28 Revision 1.1 June 2007 K8Q2815UQB K8Q2815UQB FLASH MEMORY Table 11. Common Flash Memory Interface Code Addresses (Word Mode) Data Query Unique ASCII string "QRY" 10H 11H 12H 0051H 0051H 0052H 0052H 0059H 0059H Primary OEM Command Set 13H 14H 0002H 0002H 0000H 0000H Address for Primary Extended Table 15H 16H 0040H 0040H 0000H 0000H Alternate OEM Command Set (00h = none exists) 17H 18H 0000H 0000H 0000H 0000H Address for Alternate OEM Extended Table (00h = none exists) 19H 1AH 0000H 0000H 0000H 0000H Vcc Min. (write/erase) D7-D4: volt, D3-D0: 100 millivolt 1BH 0027H 0027H Vcc Max. (write/erase) D7-D4: volt, D3-D0: 100 millivolt 1CH 0036H 0036H Vpp Min. voltage(00H = no Vpp pin present) 1DH 0000H 0000H Vpp Max. voltage(00H = no Vpp pin present) 1EH 0000H 0000H Typical timeout per single word write 2N us 1FH 0003H 0003H Typical timeout for Min. size buffer write 2 us(00H = not supported) 20H 0000H 0000H Typical timeout per individual block erase 2 ms 21H 0009H 0009H Typical timeout for full chip erase 2N ms(00H = not supported) 22H 0000H 0000H Description N N Max. timeout for word write 2 times typical 23H 0004H 0004H Max. timeout for buffer write 2N times typical 24H 0000H 0000H Max. timeout per individual block erase 2N times typical 25H 0004H 0004H Max. timeout for full chip erase 2N times typical(00H = not supported) 26H 0000H 0000H Device Size = 2 byte 27H 0017H 0017H Flash Device Interface description 28H 29H 0001H 0001H 0000H 0000H Max. number of byte in multi-byte write = 2N 2AH 2BH 0000H 0000H 0000H 0000H Number of Erase Block Regions within device 2CH 0003H 0003H Erase Block Region 1 Information 2DH 2EH 2FH 30H 0007H 0007H 0000H 0000H 0020H 0020H 0000H 0000H Erase Block Region 2 Information 31H 32H 33H 34H 007DH 007DH 0000H 0000H 0000H 0000H 0001H 0001H Erase Block Region 3 Information 35H 36H 37H 38H 0007H 0007H 0000H 0000H 0020H 0020H 0000H 0000H Erase Block Region 4 Information 39H 3AH 3BH 3CH 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H N N 29 Revision 1.1 June 2007 K8Q2815UQB K8Q2815UQB FLASH MEMORY Table 11. Common Flash Memory Interface Code Addresses (Word Mode) Data Query-unique ASCII string "PRI" 40H 41H 42H 0050H 0050H 0052H 0052H 0049H 0049H Major version number, ASCII 43H 0030H 0030H Minor version number, ASCII 44H 0030H 0030H Address Sensitive Unlock(Bits 1-0) 0 = Required, 1= Not Required Silcon Revision Number(Bits 7-2) 45H 0000H 0000H Erase Suspend 0 = Not Supported, 1 = To Read Only, 2 = To Read & Write 46H 0002H 0002H Block Protect 00 = Not Supported, 01 = Supported 47H 0001H 0001H Block Temporary Unprotect 00 = Not Supported, 01 = Supported 48H 0001H 0001H Block Protect/Unprotect scheme, 00 = Not Supported, 01 = Supported 49H 0001H 0001H Simultaneous Operation 00 = Not Supported, 01 = Supported 4AH 0001H 0001H Burst Mode Type 00 = Not Supported, 01 = Supported 4BH 0000H 0000H Page Mode Type 00 = Not Supported, 01 = 4 Word Page 02 = 8 Word Page 4CH 0002H 0002H ACC(Acceleration) Supply Minimum 00 = Not Supported, D7 - D4 : Volt, D3 - D0 : 100mV 4DH 0085H 0085H ACC(Acceleration) Supply Maximum 00 = Not Supported, D7 - D4 : Volt, D3 - D0 : 100mV 4EH 0095H 0095H Top/Bottom Boot Block Flag 02H = Bottom Boot Device, 03H = Top Boot Device, 04H = Top and Bottom Device 4FH 0004H 0004H Description Note : The K8Q2815UQB K8Q2815UQB has C.F.I information that is same with 64Mb (K8P6415UQB K8P6415UQB) 30 Revision 1.1 June 2007 K8Q2815UQB K8Q2815UQB FLASH MEMORY DEVICE STATUS FLAGS The K8Q2815UQB K8Q2815UQB has means to indicate its status of operation in the bank where a program or erase operation is in processes. Address must include bank address being excuted internal routine operation. The status is indicated by raising the device status flag via corresponding DQ pins or the RY/ BY pin. The corresponding DQ pins are DQ7, DQ6, DQ5, DQ3 and DQ2. The statuses are as follows : A22 has to be fixed whenever command is issued to the device in order to select one chip of the whole chip. For example, when A22 is Low, 1st chip is selected. And when A22 is High, : 2nd chip is selected. Table 12. Hardware Sequence Flags Status DQ6 DQ5 DQ3 DQ7 Toggle 0 0 Programming Block Erase or Chip Erase DQ7 DQ2 RY/BY Toggle 0 0 1 0 1 Toggle 0 1 1 1 0 0 Toggle (Note 1) Non-Erase Suspended Block Data Data Data Data Data 1 Erase Suspend Program Non-Erase Suspended Block DQ7 Toggle 0 0 1 0 Program Suspend Read Program Suspended Block DQ7 1 0 0 Toggle (Note 1) 1 Program Suspend Read Non-Program Suspended Block Data Data Data Data Data 1 DQ7 Toggle 1 0 No Toggle 0 0 Toggle 1 1 (Note 2) 0 0 No Toggle 0 Erase Suspend Read Erase Suspended Block Erase Suspend Read In Progress Programming Exceeded Time Limits Block Erase or Chip Erase Erase Suspend Program DQ7 Toggle 1 Notes : 1. DQ2 will toggle when the device performs successive read operations from the erase/program suspended block. 2. If DQ5 is High (exceeded timing limits), successive reads from a problem block will cause DQ2 to toggle. DQ7 : Data Polling When an attempt to read the device is made while executing the Internal Program, the complement of the data is written to DQ7 as an indication of the Routine in progress. When the Routine is completed an attempt to access to the device will produce the true data written to DQ7. When a user attempts to read the block being erased, DQ7 will be low. If the device is placed in the Erase/Program Suspend Mode, the status can be detected via the DQ7 pin. If the system tries to read an address which belongs to a block that is being erase suspended, DQ7 will be high. And, if the system tries to read an address which belongs to a block that is being program suspended, the output will be the true data of DQ7 itself. If a non-erase-suspended or non-program-suspended block address is read, the device will produce the true data to DQ7. If an attempt is made to program a protected block, DQ7 outputs complements the data for approximately 1µs and the device then returns to the Read Mode without changing data in the block. If an attempt is made to erase a protected block, DQ7 outputs complement data in approximately 100us and the device then returns to the Read Mode without erasing the data in the block. DQ6 : Toggle Bit Toggle bit is another option to detect whether an Internal Routine is in progress or completed. Once the device is at a busy state, DQ6 will toggle. Toggling DQ6 will stop after the device completes its Internal Routine. If the device is in the Erase/Program Suspend Mode, an attempt to read an address that belongs to a block that is being erased or programmed will produce a high output of DQ6. If an address belongs to a block that is not being erased or programmed, toggling is halted and valid data is produced at DQ6. If an attempt is made to program a protected block, DQ6 toggles for approximately 1us and the device then returns to the Read Mode without changing the data in the block. If an attempt is made to erase a protected block, DQ6 toggles for approximately 100µs and the device then returns to the Read Mode without erasing the data in the block. #OE or #CE should be toggled in each toggle bit status read. 31 Revision 1.1 June 2007 K8Q2815UQB K8Q2815UQB FLASH MEMORY DQ5 : Exceed Timing Limits If the Internal Program/Erase Routine extends beyond the timing limits, DQ5 will go High, indicating program/erase failure. DQ3 : Block Erase Timer The status of the multi-block erase operation can be detected via the DQ3 pin. DQ3 will go High if 50µs of the block erase time window expires. In this case, the Internal Erase Routine will initiate the erase operation.Therefore, the device will not accept further write commands until the erase operation is completed. DQ3 is Low if the block erase time window is not expired. Within the block erase time window, an additional block erase command (30H) can be accepted. To confirm that the block erase command has been accepted, the software may check the status of DQ3 following each block erase command. DQ2 : Toggle Bit 2 The device generates a toggling pulse in DQ2 only if an Internal Erase Routine or an Erase/Program Suspend is in progress. When the device executes the Internal Erase Routine, DQ2 toggles only if an erasing bank is read. Although the Internal Erase Routine is in the Exceeded Time Limits, DQ2 toggles only if an erasing block in the Exceeded Time Limits is read. When the device is in the Erase/Program Suspend mode, DQ2 toggles only if an address in the erasing or programming block is read. If a non-erasing or nonprogrammed block address is read during the Erase/Program Suspend mode, then DQ2 will produce valid data. DQ2 will go High if the user tries to program a non-erase suspend block while the device is in the Erase Suspend mode. #OE or #CE should be toggled in each toggle bit status read. RY/BY : Ready/Busy The K8Q2815UQB K8Q2815UQB has a Ready / Busy output that indicates either the completion of an operation or the status of Internal Algorithms. If the output is Low, the device is busy with either a program or an erase operation. If the output is High, the device is ready to accept any read/write or erase operation. When the RY/ BY pin is low, the device will not accept any additional program or erase commands with the exception of the Erase Suspend command. If the K8Q2815UQB K8Q2815UQB is placed in an Erase Suspend mode, the RY/ BY output will be High. For programming, the RY/ BY is valid (RY/ BY = 0) after the rising edge of the fourth WE pulse in the four write pulse sequence. For Chip Erase, RY/ BY is also valid after the rising edge of WE pulse in the six write pulse sequence. For Block Erase, RY/ BY is also valid after the rising edge of the sixth WE pulse. The pin is an open drain output, allowing two or more Ready/ Busy outputs to be OR-tied. An appropriate pull-up resistor is required for proper operation. Rp VCC Rp = 3.2 V Vcc (Max.) - VOL (Max.) IOL + IL = 2.1mA + IL Ready / Busy open drain output where IL is the sum of the input currents of all devices tied to the Ready / Busy pin. GND Device 32 Revision 1.1 June 2007 K8Q2815UQB K8Q2815UQB FLASH MEMORY Start Read(DQ0~DQ7) Valid Address Start Read(DQ0~DQ7) Valid Address DQ7 = Data ? Read(DQ0~DQ7) Valid Address DQ6 = Toggle ? Yes No Yes No No No DQ5 = 1 ? DQ5 = 1 ? Yes Yes Read(DQ0~DQ7) Valid Address Read twice(DQ0~DQ7) Valid Address Yes No DQ7 = Data ? DQ6 = Toggle ? No Fail Yes Fail Pass Pass Figure 10. Toggle Bit Algorithms Figure 9. Data Polling Algorithms 33 Revision 1.1 June 2007 K8Q2815UQB K8Q2815UQB FLASH MEMORY ABSOLUTE MAXIMUM RATINGS Parameter Symbol Vcc Voltage on any pin relative to VSS Rating Vcc -0.5 to +4.0 A9, OE , RESET -0.5 to +9.5 VIN WP/ACC V -0.5 to +9.5 All Other Pins Temperature Under Bias Unit -0.5 to +(Vcc+0.5) Commercial -10 to +125 Tbias Extended °C -25 to +125 Storage Temperature Tstg -65 to +150 °C Short Circuit Output Current IOS 5 mA TA (Industrial Temp.) -40 to +85 °C TA (Extended Temp.) -25 to + 85 °C TA (Commercial Temp.) 0 to + 70 °C Operating Temperature Notes : 1. Minimum DC voltage is -0.5V on Input/ Output pins. During transitions, this level may fall to -2.0V for periods