K6F1016V3M K6F1016S3M K6F1016R3M KM616FS1000 44-TSOP2-400F K6F1016V3M-C - Datasheet Archive

 

CMOS SRAM Document Title 64K x16 bit Super Low Power and Low Voltage Full CMOS Static RAM Revision History Revision No. History

 

K6F1016V3M K6F1016V3M, K6F1016S3M K6F1016S3M, K6F1016R3M K6F1016R3M Family CMOS SRAM Document Title 64K x16 bit Super Low Power and Low Voltage Full CMOS Static RAM Revision History Revision No. History Draft Date Remark 0.0 Initial draft March 15, 1996 Advance 0.1 Revise - Erase 100ns part from KM616FS1000 KM616FS1000 Family - Add 150ns part on KM616FS1000 KM616FS1000 Family - Add 32-sTSOP1 new package - Add high power version ISB1=5.0µA(Max) - Change VDR(Min) 1.0 to 1.5V June 3, 1996 Preliminary 1.0 Finalize - Concept change high power version to low low power version ISB1=5.0µA(Max) - Change super low power version with special handling ISB1=1.0µA(Max) - Reduce Icc & Icc1 Read : 15mA to 10mA Write : 25mA to 20mA December 1, 1996 Final 2.0 Revise - Change datasheet format - Erase reverse type package February 26, 1998 Final 3.0 Revise - Add 48-µBGA type package May 3, 1999 Final The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications and products. SAMSUNG Electronics will answer to your questions about device. If you have any questions, please contact the SAMSUNG branch offices. 1 Revision 3.0 May 1999 K6F1016V3M K6F1016V3M, K6F1016S3M K6F1016S3M, K6F1016R3M K6F1016R3M Family CMOS SRAM 64Kx16 bit Super Low Power and Low Voltage Full CMOS Static RAM FEATURES GENERAL DESCRIPTION · Process Technology: Full CMOS · Organization: 64Kx16 bit · Power Supply Voltage K6F1016V3M K6F1016V3M Family: 3.0V~3.6V K6F1016S3M K6F1016S3M Family: 2.3V~3.3V K6F1016R3M K6F1016R3M Family: 1.8V~2.7V · Low Data Retention Voltage: 1.5V(Min) · Three state output status and TTL Compatible · Package Type: 44-TSOP2-400F 44-TSOP2-400F, 48-µBGA-6.00x8.00 The K6F1016V3M K6F1016V3M, K6F1016S3M K6F1016S3M and K6F1016R3M K6F1016R3M families are fabricated by SAMSUNGs advanced Full CMOS process technology. The families support various operating temperature ranges for user flexibility of system design. The families also support low data retention voltage for battery back-up operation with low data retention current. PRODUCT FAMILY Power Dissipation Product Family Operating Temperature Vcc Range Speed(ns) 3.0~3.6V 701)/85@VCC=3.3±0.3V K6F1016V3M-C K6F1016V3M-C Standby (ISB1, Max) Operating (ICC2, Max) 80mA 1) Commercial(0~70°C) 80mA 1) K6F1016S3M-C K6F1016S3M-C 50mA 70 /85@VCC=3.0±0.3V 2.3~3.3V 120 /150@VCC=2.5±0.2V K6F1016R3M-C K6F1016R3M-C 1.8~2.7V K6F1016V3M-I K6F1016V3M-I 3.0~3.6V 3001)@VCC=2.0±0.2V 5µA2) Industrial(-40~85°C) 70 /85@VCC=3.3±0.3V 80mA 701)/85@VCC=3.0±0.3V 80mA 50mA 3001)@VCC=2.0±0.2V 20mA 1) 2.3~3.3V K6F1016R3M-I K6F1016R3M-I 44-TSOP2 44-TSOP2 Forward 20mA 1201)/150@VCC=2.5±0.2V K6F1016S3M-I K6F1016S3M-I PKG Type 1.8~2.7V 44-TSOP2 44-TSOP2 Forward 48-µBGA 3) 1. The parameter is measured with 30pF test load. 2. Super low power product=1µA with special handling. 3. Availiable parts are 100ns@VCC=3.0±0.3V, 150ns@V CC=2.5±0.2V and 300ns@VCC=2.0±0.2V with 30pF test load. PIN DESCRIPTION A4 A3 A2 A1 A0 CS I/OI I/O2 I/O3 I/O4 Vcc Vss I/O5 I/O6 I/O7 I/O8 WE A15 A14 A13 A12 N.C 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44-TSOP2 44-TSOP2 Forward 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A5 A6 A7 A OE UB B LB I/O16 I/O16 I/O15 I/O15 C I/O14 I/O14 I/O13 I/O13 Vss D Vcc I/O12 I/O12 E I/O11 I/O11 I/O10 I/O10 I/O9 F N.C A8 G A9 A10 A11 H N.C FUNCTIONAL BLOCK DIAGRAM 48-µBGA Top View 1 2 3 4 5 6 LB OE A0 A1 A2 N.C I/O9 UB A3 A4 CS I/O1 I/O10 I/O10 I/O11 I/O11 A5 A6 I/O2 I/O3 Clk gen. Precharge circuit. A7 Vcc Vss A6 A5 A4 Vss I/O12 I/O12 N.C A7 I/O4 I/O13 I/O13 N.C N.C I/O5 Vss Memory array 1024 rows 64×16 columns Data cont A2 Vcc Vcc Row select A3 I/O Circuit Column select A1 A0 A15 I/O15 I/O15 I/O14 I/O14 A14 A15 I/O6 I/O16 I/O16 N.C A12 A13 WE I/O8 N.C A8 A9 A10 A11 A14 I/O7 N.C I/O1~I/O8 Data cont I/O 9~I/O16 I/O16 Data cont Name Function Name A10 Chip Select Input OE Output Enable Input UB Write Enable Input Vcc Power Address Inputs Vss Ground OE N.C. No Connection A13 A12 A11 A9 A8 Upper Byte(I/O9~16) WE LB A0~A15 I/O1~I/O16 I/O16 Data Inputs/Outputs LB Function CS Lower Byte(I/O1~8) WE UB Control logic CS SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice. 2 Revision 3.0 May 1999 K6F1016V3M K6F1016V3M, K6F1016S3M K6F1016S3M, K6F1016R3M K6F1016R3M Family CMOS SRAM PRODUCT LIST Commercial Temperature Products(0~70°C) Part Name Industrial Temperature Products(-40~85°C) Function Part Name Function K6F1016V3M-TB70 K6F1016V3M-TB70 K6F1016V3M-TB85 K6F1016V3M-TB85 44-TSOP2 44-TSOP2 F, 70ns, 3.3V, LL 44-TSOP2 44-TSOP2 F, 85ns, 3.3V, LL K6F1016V3M-TF70 K6F1016V3M-TF70 K6F1016V3M-TF85 K6F1016V3M-TF85 44-TSOP2 44-TSOP2 F, 70ns, 3.3V, LL 44-TSOP2 44-TSOP2 F, 85ns, 3.3V, LL K6F1016S3M-TB12 K6F1016S3M-TB12 K6F1016S3M-TB15 K6F1016S3M-TB15 44-TSOP2 44-TSOP2 F, 120/70ns, 2.5/3.0V, LL 44-TSOP2 44-TSOP2 F, 150/85ns, 2.5/3.0V, LL K6F1016S3M-TF12 K6F1016S3M-TF12 K6F1016S3M-TF15 K6F1016S3M-TF15 K6F1016S3M-ZF15 K6F1016S3M-ZF15 44-TSOP2 44-TSOP2 F, 120/70ns, 2.5/3.0V, LL 44-TSOP2 44-TSOP2 F, 150/85ns, 2.5/3.0V, LL 48-µBGA, 2.5V/3.0V, 150/100ns K6F1016R3M-TB30 K6F1016R3M-TB30 44-TSOP2 44-TSOP2 F, 300ns, 2.0/2.5V, LL K6F1016R3M-TF30 K6F1016R3M-TF30 K6F1016R3M-ZF30 K6F1016R3M-ZF30 44-TSOP2 44-TSOP2 F, 300ns, 2.0/2.5V, LL 48-µBGA, 1.8V/2.5V, 300ns FUNCTIONAL DESCRIPTION CS OE WE LB UB I/O1~8 I/O9~16 1) 1) Mode Power H X X X X High-Z High-Z Deselected Standby L H H X1) X1) High-Z High-Z Output Disabled Active 1) 1) L X X H H High-Z High-Z Output Disabled Active L L H L H Dout High-Z Lower Byte Read Active L L H H L High-Z Dout Upper Byte Read Active L L H L L Dout Dout Word Read Active L L L 1) 1) 1) L L H Din High-Z Lower Byte Write Active 1) L H L High-Z Din Upper Byte Write Active 1) L L L Din Din Word Write Active X X X 1. X means dont care. (Must be in low or high state) ABSOLUTE MAXIMUM RATINGS1) Item Voltage on any pin relative to Vss Voltage on Vcc supply relative to Vss Power Dissipation Symbol Ratings Unit Remark VIN,VOUT -0.2 to 3.6V 2) V - VCC -0.2 to 4.0V3) V - Operating Temperature Soldering temperature and time PD 1.0 W - TSTG -55 to 150 °C - 0 to 70 °C K6F1016V3M-C K6F1016V3M-C, K6F1016S3M-C K6F1016S3M-C , K6F1016R3M-C K6F1016R3M-C -40 to 85 Storage temperature °C K6F1016V3M-I K6F1016V3M-I, K6F1016S3M-I K6F1016S3M-I, K6F1016R3M-I K6F1016R3M-I - - TA TSOLDER 260°C, 5sec(Lead Only) 1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. VIN/VOUT=-0.2 to 3.9V for K6F1016V3M K6F1016V3M Family. 3. VCC=-0.2 to 4.6V for K6F1016V3M K6F1016V3M Family. 3 Revision 3.0 May 1999 K6F1016V3M K6F1016V3M, K6F1016S3M K6F1016S3M, K6F1016R3M K6F1016R3M Family CMOS SRAM RECOMMENDED DC OPERATING CONDITIONS 1) Item Symbol Product Min K6F1016V3M K6F1016V3M Family 3.0 3.3 3.6 Vcc K6F1016S3M K6F1016S3M Family 2.3 2.5/3.0 3.3 K6F1016R3M K6F1016R3M Family 1.8 2.0/2.5 2.7 0 0 0 V - Vcc+0.22) V - 0.4 V Supply voltage Ground Vss All Family K6F1016V3M K6F1016V3M Family Vcc=3.0±0.3V Vcc=2.5±0.2V K6F1016R3M K6F1016R3M Family Input low voltage VIL 2.0 Unit V 2.2 Vcc=2.5±0.2V K6F1016S3M K6F1016S3M Family VIH Max 2.2 2.0 Vcc=2.0±0.2V Input high voltage Vcc=3.3±0.3V Typ 1.6 All Family -0.23) Note 1 Commercial Product : TA=0 to 70°C, unless otherwise specified Industrial Product : TA=-40 to 85°C, unless otherwise specified 2. Overshoot : Vcc + 1.0V in case of pulse width 20ns 3. Undershoot : -1.0V in case of pulse width 20ns 4. Overshoot and undershoot are sampled, not 100% tested. CAPACITANCE1) (f=1MHz, TA=25°C) Item Symbol Test Condition Min Max Unit Input capacitance CIN VIN=0V - 8 pF Input/Output capacitance CIO VIO=0V - 10 pF 1. Capacitance is sampled, not 100% tested DC AND OPERATING CHARACTERISTICS Item Typ Max Unit VIN=Vss to Vcc -1 - 1 µA -1 - 1 µA - - 2 mA Read - - 5 Write - - 20 Vcc=3.3V@70ns - - 65 Vcc=2.7V@120ns - - 55 - - 20 - - 0.4 -1.0mA at Vcc=3.0/3.3V 2.4 - - -0.5mA at Vcc=2.5V 2.0 - - -0.44mA at Vcc=2.0V ILI Min Vcc=2.2V@300ns Input leakage current Symbol Test Conditions 1.6 - - Output leakage current ILO CS=VIH or OE=VIH or WE=VIL, VIO=Vss to Vcc Operating power supply current ICC IIO=0mA, CS=VIL, VIN=VIL or VIH, Read ICC1 Cycle time=1µs, 100% duty, IIO=0mA, CS0.2V, VIN0.2V or VINVCC-0.2V Average operating current ICC2 Cycle time=Min, 100% duty, IIO=0mA, CS=VIL, VIN=VIL or VIH mA mA 2.1mA at Vcc=3.0/3.3V Output low voltage VOL IOL 0.5mA at Vcc=2.5V V 0.33mA at Vcc=2.0V Output high voltage VOH IOH V Standby Current(TTL) ISB CS=VIH, Other inputs=V IL or V IH - - 0.3 mA Standby Current(CMOS) ISB1 CSVcc-0.2V, Other inputs=0~Vcc - - 51) µA 1. Super low power product=1µA with special handling. 4 Revision 3.0 May 1999 K6F1016V3M K6F1016V3M, K6F1016S3M K6F1016S3M, K6F1016R3M K6F1016R3M Family CMOS SRAM AC OPERATING CONDITIONS VTM3) TEST CONDITIONS (Test Load and Test Input/Output Reference) R12) Input pulse level: 0.4 to 2.2V for Vcc=3.3V, 3.0V, 2.5V 0.4 to 1.8V for Vcc=2.0V Input rising and falling time: 5ns Input and output reference voltage: 1.5V for Vcc=3.3V, 3.0V 1.1V for Vcc=2.5V 0.9V for Vcc=2.0V Output load (See right):CL=100pF+1TTL CL=30pF+1TTL CL1) R22) 1. Including scope and jig capacitance 2. R1 =3070, R 2=3150 3. VTM =2.8V for V CC=3.0/3.3V =2.3V for V CC=2.5V =1.8V for V CC=2.0V AC CHARACTERISTICS (Commercial product:TA=0 to 70°C, Industrial product: TA=-40 to 85°C K6F1016V3M K6F1016V3M Family: Vcc=3.0~3.6V, K6F1016S3M K6F1016S3M Family: Vcc=2.3~3.3V, K6F1016R3M K6F1016R3M Family: Vcc=1.8~2.7V) Speed Bins Parameter List Symbol 70ns 85ns 100ns 120ns 150ns Units 300ns Min Max Min Max Min Max Min Max Min Max Min Max Read cycle time 70 - 85 - 100 - 120 - 150 - 300 - ns Address access time tAA - 70 - 85 - 100 - 120 - 150 - 300 ns Chip select to output tCO - 70 - 85 - 100 - 120 - 150 - 300 ns Output enable to valid output Read tRC tOE - 35 - 45 - 50 - 60 - 75 - 150 ns UB, LB Access Time tBA - 35 - 45 - 50 - 60 - 75 - 150 ns tLZ 10 - 10 - 10 - 20 - 20 - 50 - ns Output enable to low-Z output Chip select to low-Z output tOLZ, tBLZ 5 - 5 - 5 - 20 - 20 - 30 - ns Chip disable to high-Z output tHZ 0 25 0 25 0 30 0 35 0 40 0 60 ns Output disable to high-Z output tOHZ, tBHZ 0 25 0 25 0 30 0 35 0 40 0 60 ns Output hold from address change tOH 10 - 15 - 15 - 15 - 15 - 30 - ns Write cycle time tWC 70 - 85 - 100 - 120 - 150 - 300 - ns Chip select to end of write tCW 65 - 70 - 80 - 100 - 120 - 300 - ns Address set-up time tAS 0 - 0 - 0 - 0 - 0 - 0 - ns Address valid to end of write tAW 65 - 70 - 80 - 100 - 120 - 300 - ns Write pulse width tWP 55 - 60 - 70 - 80 - 100 - 200 - ns tBW 65 - 70 - 80 - 100 - 120 - 300 - ns Write recovery time tWR 0 - 0 - 0 - 0 - 0 - 0 - ns Write to output high-Z tWHZ 0 25 0 25 0 30 0 35 0 40 0 60 ns Data to write time overlap tDW 30 - 35 - 40 - 50 - 60 - 120 - ns Data hold from write time tDH 0 - 0 - 0 - 0 - 0 - 0 - ns End write to output low-Z tOW 5 - 5 - 5 - 5 - 5 - 20 - ns Write UB, LB Valid to End of Write DATA RETENTION CHARACTERISTICS Item Symbol Test Condition Vcc for data retention VDR Data retention current IDR Vcc=3.0V Data retention set-up time tSDR Recovery time tRDR Min Typ Max Unit 1.5 CSVcc-0.2V - 3.6 V - 5.0 - - tRC See data retention waveform - 0 - µA - 1) ns 1. Super low power product=1µA with special handling. 5 Revision 3.0 May 1999 K6F1016V3M K6F1016V3M, K6F1016S3M K6F1016S3M, K6F1016R3M K6F1016R3M Family CMOS SRAM TIMMING DIAGRAMS TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS=OE=VIL, WE=VIH, UB or/and LB=VIL) tRC Address tAA tOH Data Out Data Valid Previous Data Valid TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH) tRC Address tOH tAA tCO CS tHZ tBA UB, LB tBHZ tOE OE Data out High-Z tOLZ tBLZ tLZ tOHZ Data Valid NOTES (READ CYCLE) 1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device interconnection. 6 Revision 3.0 May 1999 K6F1016V3M K6F1016V3M, K6F1016S3M K6F1016S3M, K6F1016R3M K6F1016R3M Family CMOS SRAM TIMING WAVEFORM OF WRITE CYCLE(1) (WE Controlled) tWC Address tCW(2) tWR(4) CS tAW tBW UB, LB tWP(1) WE tAS(3) tDW Data in High-Z tDH tWHZ Data out High-Z Data Valid tOW Data Undefined TIMING WAVEFORM OF WRITE CYCLE(2) (CS Controlled) tWC Address tAS(3) tCW(2) tWR(4) CS tAW tBW UB, LB tWP(1) WE tDW Data Valid Data in Data out tDH High-Z High-Z 7 Revision 3.0 May 1999 K6F1016V3M K6F1016V3M, K6F1016S3M K6F1016S3M, K6F1016R3M K6F1016R3M Family CMOS SRAM TIMING WAVEFORM OF WRITE CYCLE(3) (UB, LB Controlled) tWC Address tCW(2) tWR(4) CS tAW tBW UB, LB tAS(3) tWP(1) WE tDW Data in Data out tDH Data Valid High-Z High-Z NOTES (WRITE CYCLE) 1. A write occurs during the overlap(tWP ) of low CS and low WE. A write begins when CS goes low and WE goes low with asserting UB or LB for single byte operation or simultaneously asserting UB and LB for double byte operation. A write ends at the earliest transition when CS goes high and WE goes high. The tWP is measured from the beginning of write to the end of write. 2. tCW is measured from the CS going low to end of write. 3. tAS is measured from the address valid to the beginning of write. 4. tWR is measured from the end or write to the address change. tWR applied in case a write ends as CS or WE going high. DATA RETENTION WAVE FORM CS controlled VCC tSDR Data Retention Mode tRDR 3.0/2.7/2.3/1.8V 2.2V VDR CSVCC - 0.2V CS GND 8 Revision 3.0 May 1999 K6F1016V3M K6F1016V3M, K6F1016S3M K6F1016S3M, K6F1016R3M K6F1016R3M Family CMOS SRAM PACKAGE DIMENSIONS Units: millimeters(inches) 44 PIN THIN SMALL OUTLINE PACKAGE TYPE II (400F) 0~8° 0.25 ( ) 0.010 #23 0.45 ~0.75 0.018 ~ 0.030 11.76 ±0.20 0.463 ±0.008 #1 10.16 0.400 #44 0 + 0.1 0.05 0.15 - .0 04 +0 06 - 0.002 #22 18.81 MAX. 0.741 18.41 ±0.10 0.725 ±0.004 0.0 1.00 ±0.10 0.039 ±0.004 ( 0.805 ) 0.032 0.35 ±0.10 0.014 ±0.004 ( 0.50 ) 0.020 1.20 MAX. 0.047 0.10 0.004 MAX 0.05 MIN. 0.002 0.80 0.0315 9 Revision 3.0 May 1999 K6F1016V3M K6F1016V3M, K6F1016S3M K6F1016S3M, K6F1016R3M K6F1016R3M Family CMOS SRAM PACKAGE DIMENSIONS Units: millimeters 48 BALL MICRO BALL GRID ARRAY- 0.75mm ball pitch Top View Bottom View Ball #A1 B B 6 5 4 3 2 1 C/2 C/2 A B Ball #A1 C C C C1 D E F G H B1 B/2 B/2 SRAM Die Elastomer Detail A Detail A 0.25/Typ. Side View E2 D A Y Min Typ - 0.75 5.90 6.00 6.10 B1 - 3.75 - C 7.90 8.00 8010 C1 - 5.25 - D 0.30 0.35 0.40 E - 0.80 0.81 E1 - 0.55 - E2 - 0.25 - Y - - 0.42/Typ. - B Elastomer Die Max A 0.32/Typ. 0.55/Typ. E1 E C 0.08 Notes. 1. Bump counts: 48(8row x 6column) 2. Bump pitch: (x,y)=(0.75 x 0.75)(typ.) 3. All tolerence are +/-0.050 unless otherwise specified. 4. Typ: Typical 5. Y is coplanarity: 0.08(Max) 10 Revision 3.0 May 1999