K4J55323QI K4J55323QI-BJ1A K4J55323QI-BJ11 K4J55323QI-BC12 K4J55323QI-BC14 - Datasheet Archive

 

K4J55323QI 256Mbit GDDR3 SDRAM Revision 1.3 May 2007 Notice INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG

 

256M GDDR3 SDRAM K4J55323QI K4J55323QI 256Mbit GDDR3 SDRAM Revision 1.3 May 2007 Notice INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL INFORMATION IN THIS DOCUMENT IS PROVIDED ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND. 1. For updates or additional information about Samsung products, contact your nearest Samsung office. 2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar applications where Product failure could result in loss of life or personal or physical harm, or any military or defense application, or any governmental procurement to which special terms or provisions may apply. * Samsung Electronics reserves the right to change products or specification without notice. 1 / 54 Rev. 1.3 May 2007 256M GDDR3 SDRAM K4J55323QI K4J55323QI Revision History Revision Month Year 0.0 March 2006 - Target Spec History 0.1 November 2006 - Changed speed bin organization 1.0 January 2007 - Final Spec - Added current data and IBIS data 1.1 February 2007 - Added Power dissipation data on page 48. - Added comment on page 23. - Corrected typo 1.2 March 2007 - Corrected typo on page 53. 1.3 May 2007 - Added revision ID on page 16. 2 / 54 Rev. 1.3 May 2007 256M GDDR3 SDRAM K4J55323QI K4J55323QI 2M x 32Bit x 4 Banks Graphic Double Data Rate 3 Synchronous DRAM with Uni-directional Data Strobe 1.0 FEATURES · · · · · · · · · · · · · · · · 1.8V + 0.1V power supply for device operation for -BC* 1.8V + 0.1V power supply for I/O interface for -BC* 1.9V + 0.1V power supply for device operation for -BJ* 1.9V + 0.1V power supply for I/O interface for -BJ* On-Die Termination (ODT) Output Driver Strength adjustment by EMRS Calibrated output drive 1.8V Pseudo Open drain compatible inputs/outputs 4 internal banks for concurrent operation Differential clock inputs (CK and CK) Commands entered on each positive CK edge CAS latency : 7, 8, 9, 10, 11, 12 (clock) Programmable Burst length : 4 and 8 Programmable Write latency : 1, 2, 3, 4, 5, 6 and 7 (clock) Single ended READ strobe (RDQS) per byte Single ended WRITE strobe (WDQS) per byte · · · · · · · · · · · · RDQS edge-aligned with data for READs WDQS center-aligned with data for WRITEs Data Mask(DM) for masking WRITE data Auto & Self refresh modes Auto Precharge option 32ms, auto refresh (4K cycle) 136 Ball FBGA Maximum clock frequency up to 1000MHz Maximum data rate up to 2.0Gbps/pin DLL for outputs Boundary scan function with SEN pin Mirror function with MF pin 2.0 ORDERING INFORMATION Part NO. Max Freq. Max Data Rate K4J55323QI-BJ1A K4J55323QI-BJ1A 1000MHz 2.0Gbps/pin K4J55323QI-BJ11 K4J55323QI-BJ11 900MHz 1.8Gbps/pin K4J55323QI-BC12 K4J55323QI-BC12 800MHz 1.6Gbps/pin K4J55323QI-BC14 K4J55323QI-BC14 700MHz 1.4Gbps/pin VDD&VDDQ Package 1.9V+0.1V 136 Ball FBGA 1.8V+0.1V 3.0 GENERAL DESCRIPTION FOR 2M x 32Bit x 4 Bank GDDR3 SDRAM The K4J55323QI K4J55323QI is 268,435,456 bits of hyper synchronous data rate Dynamic RAM organized as 4 x 2,097,152 words by 32 bits, fabricated with SAMSUNG's high performance CMOS technology. Synchronous features with Data Strobe allow extremely high performance up to 8.0GB/s/chip. I/O transactions are possible on both edges of the clock cycle. Range of operating frequencies, and programmable latencies allow the device to be useful for a variety of high performance memory system applications. 3 / 54 Rev. 1.3 May 2007 256M GDDR3 SDRAM K4J55323QI K4J55323QI 4.0 PIN CONFIGURATION Normal Package (Top View) 1 2 3 A VDDQ VDD VSS B VSSQ DQ0 C VDDQ D 4 5 6 7 8 9 10 11 12 ZQ MF VSS VDD VDDQ DQ1 VSSQ VSSQ DQ9 DQ8 VSSQ DQ2 DQ3 VDDQ VDDQ DQ11 DQ10 VDDQ VSSQ WDQS0 RDQS0 VSSQ VSSQ RDQS1 WDQS1 VSSQ E VDDQ DQ4 DM0 VDDQ VDDQ DM1 DQ12 VDDQ F VDD DQ6 DQ5 CAS CS DQ13 DQ14 VDD G VSS VSSQ DQ7 BA0 BA1 DQ15 VSSQ VSS H VREF A1 RAS CKE WE RFM A5 VREF J VSSA RFU1 RFU2 VDDQ VDDQ CK CK VSSA K VDDA A10 A2 A0 A4 A6 A8/AP VDDA L VSS VSSQ DQ25 A11 A7 DQ17 VSSQ VSS M VDD DQ24 DQ27 A3 A9 DQ19 DQ16 VDD N VDDQ DQ26 DM3 VDDQ VDDQ DM2 DQ18 VDDQ P VSSQ WDQS3 RDQS3 VSSQ VSSQ RDQS2 WDQS2 VSSQ R VDDQ DQ28 DQ29 VDDQ VDDQ DQ21 DQ20 VDDQ T VSSQ DQ30 DQ31 VSSQ VSSQ DQ23 DQ22 VSSQ V VDDQ VDD VSS SEN RESET VSS VDD VDDQ Note : 1. RFU1 is reserved for future use 2. RFU2 is reserved for future use 3. RFM : When the MF ball is tied LOW, RFM(H10) receiver is disabled and it recommended to be driven to a static LOW state, however, either static HIGH or floating state on this pin will not cause any problem for the DRAM. When the MF ball is tied HIGH, RAS(H3) becomes RFM due to mirror function and the receiver is disabled. It recommended to be driven to a static LOW state, however, either static HIGH or floating state on this pin will not cause any problem for the DRAM Please refer to Mirror Function Signal Mapping table at page 22. 4 / 54 Rev. 1.3 May 2007 256M GDDR3 SDRAM K4J55323QI K4J55323QI 5.0 INPUT/OUTPUT FUNCTIONAL DESCRIPTION Symbol Type Function CK, CK Input Clock: CK and CK are differential clock inputs. CMD, ADD inputs are sampled on the crossing of the positive edge of CK and negative edge of CK. Output (read) data is referenced to the crossings of CK and CK (both directions of crossing). CK, CK should be maintained stable, except self-refresh mode CKE Input Clock Enable: CKE HIGH activates, and CKE Low deactivates, internal clock signals and device input buffers and output drivers. Taking CKE Low provides Precharge Power-Down and Self Refresh operation (all banks idle), or Active Power-Down (row Active in any bank). CKE is synchronous for power down entry and exit, and for self refresh entry. CKE is asynchronous for self refresh exit. CKE must be maintained high throughout read and write accesses. Input buffers, excluding CK, CK and CKE are disabled during power-down. Input buffers, excluding CKE, are disabled during self refresh. CS Input Chip Select: All commands are masked when CS is registered HIGH. CS provides for external bank selection on systems with multiple banks. CS is considered part of the command code. RAS, CAS, WE Input Command Inputs: RAS, CAS and WE (along with CS) define the command being entered. DM0 ~DM3 Input Input Data Mask: DM is an input mask signal for write data. Input data is masked when DM is sampled HIGH coincident with that input data during a Write access. DM is sampled on both edges of clock. Although DM pins are input only, the DM loading matches the DQ and WDQS loading. BA0,BA1 Input Bank Address Inputs: BA0 and BA1 define to which bank an Active, Read, Write or Precharge command is being applied. A0 ~ A11 Input Address Inputs: Provided the row address for Active commands and the column address and Auto Precharge bit for Read/Write commands to select one location out of the memory array in the respective bank. A8 is sampled during a Precharge command to determine whether the Precharge applies to one bank (A8 LOW) or all banks (A8 HIGH). If only one bank is to be precharged, the bank is selected by BA0, BA1,BA2. The address inputs also provide the op-code during Mode Register Set commands. Row addresses : RA0 ~ RA11, Column addresses : CA0 ~ CA7, CA9 . Column address CA8 is used for auto precharge. DQ0 ~ DQ31 Input/ Output Data Input/ Output: Bi-directional data bus. RDQS0 ~ RDQS3 Output READ Data Strobe: Output with read data. RDQS is edge-aligned with read data. WDQS0 ~ WDQS3 Input NC/RFU WRITE Data Strobe: Input with write data. WDQS is center-aligned to the inout data. No Connect: No internal electrical connection is present. VDDQ Supply VSSQ Supply DQ Ground VDD Supply Power Supply VSS Supply Ground VDDA Supply DLL Power Supply VSSA Supply DLL Ground Supply Reference voltage: 0.7*VDDQ , 2 Pins : (H12) for Data input , (H1) for CMD and ADDRESS VREF MF ZQ Input DQ Power Supply Mirror Function for clamshell mounting of DRAMs. VDDQ CMOS input. Reference Resistor connection pin for On-die termination. RES Input Reset pin: RESET pin is a VDDQ CMOS input SEN Input Scan enable : Must tie to the ground in case not in use. VDDQ CMOS input. RFM Input Reserved for Mirror Function : When the MF ball is tied low, RFM(H10) is recommended to be driven to logic low state. When the MF ball is tied high, RAS(H3) switch to RFM and is recommended to be driven to logic low state 5 / 54 Rev. 1.3 May 2007 256M GDDR3 SDRAM K4J55323QI K4J55323QI 6.0 BLOCK DIAGRAM (2Mbit x 32I/O 32I/O x 4 Bank) WDQS Input Buffer 32 Input Buffer I/O Control Data Input Register Serial to parallel Bank Select LWE LDMi 128 2M x 32 32 Output Buffer 2M x 32 128 4-bit prefetch Sense AMP Row Decoder Refresh Counter Row Buffer ADDR Address Register iCK 2M x 32 x32 DQi 2M x 32 Column Decoder Col. Buffer LCBR LRAS Latency & Burst Length LRAS LCBR Strobe Gen. Programming Register LCKE Output DLL RDQS LWE LCAS LWCBR CK,CK LDMi Timing Register iCK CKE CS RAS CAS WE DMi * iCK : internal clock 6 / 54 Rev. 1.3 May 2007 256M GDDR3 SDRAM K4J55323QI K4J55323QI 7.0 FUNCTIONAL DESCRIPTION 7.1 Simplified State Diagram Power Applied Power On Self Refresh Precharge PREALL REFS REFSX MRS EMRS MRS Auto Refresh REFA Idle CKEL CKEH Active Power Down ACT Precharge Power Down CKEH CKEL Row Active Read Write Write A Write Write Read A Read Read Read A Write A Read A PRE Write A PRE PRE PRE Read A Precharge PREALL Automatic Sequence Command Sequence PREALL = Precharge All Banks MRS = Mode Register Set EMRS = Extended Mode Register Set REFS = Enter Self Refresh REFSX = Exit Self Refresh REFA = Auto Refresh 7 / 54 CKEL = Enter Power Down CKEH = Exit Power Down ACT = Active Write A = Write with Autoprecharge Read A = Read with Autoprecharge PRE = Precharge Rev. 1.3 May 2007 256M GDDR3 SDRAM K4J55323QI K4J55323QI 7.2 INITIALIZATION GDDR3 SDRAMs must be powered up and initialized in a predefined manner. Operational procedures other than those specified may result in undefined operation. 1. Apply power and keep CKE/RESET at low state ( All other inputs may be undefined) - Apply VDD and VDDQ simultaneously - Apply VDDQ before Vref. ( Inputs are not recognized as valid until after VREF is applied ) - The VDD voltage ramp time must be no greater than 200 ms from when VDD ramps from 300 mV to VDD min and the power voltage ramps are without any slope reversal 2. Required minimum 100us for the stable power before RESET pin transition to HIGH - Upon power-up the address/command active termination value will automatically be set based off the state of RESET and CKE. - On the rising edge of RESET the CKE pin is latched to determine the address and command bus termination value. If CKE is sampled at a zero the address termination is set to 1/2 of ZQ. If CKE is sampled at a one the address termination is set to ZQ. - RESET must be maintained at a logic LOW level and CS at a logic high value during power-up to ensure that the DQ outputs will be in a High-Z state, all active terminators off, and all DLLs off. 3. Minimum 200us delay required prior to applying any executable command after stable power and clock. 4. Once the 200us delay has been satisfied, a DESELECT or NOP command should be applied, then RESET and CKE should be brought to HIGH, 5. Issue a PRECHARGE ALL command following after NOP command. 6. Issue a EMRS command (BA1BA0="01") to enable the DLL. 7. Issue MRS command (BA0BA1 = "00") to reset the DLL and to program the operating parameters. 20K clock cycles are required between the DLL to lock. 8. Issue a PRECHARGE ALL command 9. Issue at least two AUTO refresh command to update the driver impedance and calibrate the output drivers. Following these requirements, the GDDR3 SDRAM is ready for normal operation. VDDQ VDD VREF T0 T1 Ta0 Tb0 Tc0 Td0 Te0 Tf0 PRE LMR LMR PRE AR AR ACT CK CK RES t t ATS t t IS ATH CH tCL t IH CKE CKE t IS COMMAND t IH NOP DM t IS tIH CODE CODE t IS t ALL BANKS A0-A7, A9-A11 A9-A11 IS t CODE A8 t IS t IH t CODE RA t IH IS BAO=H, BA1 =L BA0, BA1 RA ALL BANKS IH t IH BAO=L, BA1 =L BA High RDQS High WDQS High DQ T = 200us T=10ns Power-up: VDD and CK stable tRP Precharge All Banks Load Extended Mode Register 8 / 54 tMRD tMRD Load Mode Register DLL Reset tRP Precharge All Banks 20K tRFC 1st Auto Refresh tRFC 2nd Auto Refresh Rev. 1.3 May 2007 256M GDDR3 SDRAM K4J55323QI K4J55323QI 7.3 MODE REGISTER SET(MRS) The mode register stores the data for controlling the various operating modes of GDDR3 SDRAM. It programs CAS latency, addressing mode, test mode and various vendor specific options to make GDDR3 SDRAM useful for variety of different applications. The default value of the mode register is not defined, therefore the mode register must be written after EMRS setting for the proper operation. The mode register is written by asserting low on CS, RAS, CAS and WE (The GDDR3 SDRAM should be in active mode with CKE already high prior to writing into the mode register). The state of address pins A0 ~ A11 and BA0, BA1 in the same cycle as CS, RAS, CAS and WE going low is written in the mode register. Minimum clock cycles specified as tMRD are required to complete the write operation in the mode register. The mode register contents can be changed using the same command and clock cycle requirements during operation as long as all banks are in the idle state. The mode register is divided into various fields depending on functionality. The Burst length uses A0 ~ A1. CAS latency (read latency from column address) uses A2, A6 ~ A4. A7 is used for test mode. A8 is used for DLL reset. A9 ~ A11 are used for Write latency. Refer to the table for specific codes for various addressing modes and CAS latencies. BA1 BA0 0 A11 A10 0 A9 A8 DLL WL A7 A6 TM A5 A4 A3 A1 BT CAS Latency A2 A0 CL Burst Length Test Mode BA1 BA0 An ~ A0 A7 0 0 MRS 0 Normal 0 1 EMRS 1 Test mode Burst Type A3 0 DLL Reset 0 Write Latency Write Latency Reserved No 1 Sequential 1 DLL A8 Burst Type Yes A11 A10 A9 0 0 0 Reserved 0 0 1 1 0 1 0 2 A2 A6 A5 A4 0 1 1 3 0 0 0 1 0 0 4 0 0 1 0 1 5 0 1 1 0 6 1 1 1 7 Note : DLL reset is self-clearing Burst Length CAS Latency A0 0 0 Reserved 0 8 0 1 Reserved 0 1 9 1 0 4 0 1 0 10 1 1 8 0 0 1 1 11 0 1 0 0 Reserved(4) 0 RFU(Reserved for future use) should stay "0" during MRS cycle A1 CAS Latency 1 0 1 Reserved(5) 0 1 1 0 Reserved(6) 0 1 1 1 7 1 0 0 0 12 1 0 0 1 Reserved(13) 1 0 1 0 Reserved(14) 1 0 1 1 Reserved(15) 1 1 0 0 Reserved 1 1 0 1 Reserved 1 1 1 0 Reserved 1 1 1 1 Reserved 9 / 54 Burst Length Rev. 1.3 May 2007 256M GDDR3 SDRAM K4J55323QI K4J55323QI PROGRAMMABLE IMPEDANCE OUTPUT BUFFER AND ACTIVE TERMINATOR The GDDR3 SDRAM is equipped with programmable impedance output buffers and Active Terminators. This allows a user to match the driver impedance to the system. To adjust the impedance, an external precision resistor(RQ) is connected between the ZQ pin and Vss. The value of the resistor must be six times of the desired output impedance. For example, a 240 resistor is required for an output impedance of 40 . To ensure that output impedance is one sixth the value of RQ (within 10 %), the range of RQ is 120 to 360 (20 to 60) output impedance. MF,SEN, RES, CK and /CK are not internally terminated. CK and /CK will be terminated on the system module using external 1% resisters. The output impedance is updated during all AUTO REFRESH commands and NOP commands when a READ is not in progress to compensate for variations in voltage supply and temperature. The output impedance updates are transparent to the system. Impedance updates do not affect device operation, and all data sheet timing and current specifications are met during update. To guarantee optimum output driver impedance after power-up, the GDDR3(x32) needs at least 20us after the clock is applied and stable to calibrate the impedance upon power-up. The user may operate the part with less than 20us, but the optimal output impedance is not guaranteed. The value of ZQ is also used to calibrated the internal address/command termination resisters. The two termination values that are selectable during power up are 1/2 of ZQ and ZQ. The value of ZQ is used to calibrate the internal DQ termination resisters. The two termination values that are selectable are 1/4 of ZQ and 1/2 of ZQ. BURST LENGTH Read and write accesses to the GDDR3 SDRAM are burst oriented, with the burst length being programmable, as shown in MRS table. The burst length determines the maximum number of column locations that can be accessed for a given READ or WRITE command. Reserved states should not be used, as unknown operation or incompatibility with future versions may result. When a READ or WRITE command is issued, a block of columns equal to the burst length is effectively selected. All accesses for that burst take place within the block, meaning that the burst will wrap within the block if a boundary is reached. The block is uniquely selected by A2-Ai when the burst length is set to four (Where Ai is the most significant column address bit for a given configuration). The remaining (least significant) address bit(s) is (are) used to select the starting location within the block. The programmable burst length applies to both READ and WRITE bursts. BURST TYPE Accesses within a given burst must be programmed to be sequential; this is referred to as the burst type and is selected via bit M3. This device does not support the interleaved burst mode found in GDDR SDRAM devices. The ordering of accesses within a burst is determined by the burst length, the burst type, and the starting column address, as shown in below table: Burst Definition Burst Definition Burst Length 4 Starting Column Address Order of Accesses Within a Burst Type= Sequential A2 A1 A0 0 0 A1 A0 0 0 0 0-1-2-3-4-5-6-7 1 8 0 A2 0-1-2-3 0 0 4-5-6-7-0-1-2-3 Note : 1. For a burst length of four, A2-A7 select the block of four burst; A0-A1 select the starting column within the block and must be set to zero 2. For a burst length of eight, A3-A7 select the block of eight burst; A0-A2 select the starting column within the block. 10 / 54 Rev. 1.3 May 2007 256M GDDR3 SDRAM K4J55323QI K4J55323QI CAS LATENCY (READ LATENCY) The CAS latency is the delay, in clock cycles, between the registration of a READ command and the availability of the first bit of output data. The latency can be set to 7~12 clocks. If a READ command is registered at clock edge n, and the latency is m clocks, the data will be available nominally coincident with clock edge n+m. Below table indicates the operating frequencies at which each CAS latency setting can be used. Reserved states should not be used as unknown operation or incompatibility with future versions may result. CAS Latency SPEED -BJ1A Allowable operating frequency (MHz ) CL=12 CL=11 CL=10 CL=7 - - - 700 - - - 900 -BC12 -BC12 CL=8 - 1000 -BJ11 -BJ11 CL=9 800 -BC14 -BC14 T0 COMMAND READ RDQS DQ T5 /CK CK T0 COMMAND RDQS DQ READ T7 NOP NOP T7 T8 NOP NOP T7n NOP CL = 7 T6 /CK CK T6 NOP T8n CL = 8 Burst Length = 4 in the cases shown Shown with nominal tAC and nominal tDSDQ DON'T CARE TRANSITIONING DATA 11 / 54 Rev. 1.3 May 2007 256M GDDR3 SDRAM K4J55323QI K4J55323QI WRITE LATENCY The Write latency (WL) is the delay, in clock cycles, between the registration of a WRITE command and the availability of the first bit of input data. The latency can be set from 1 to 7 clocks depending in the operating frequency and desired current draw. When the write latencies are set to 1 or 2 or 3 clocks, the input receivers never turn off when the WRITE command is registered. If a WRITE command is registered at clock edge n, and the latency is m clocks, the data will be available nominally coincident with clock edge n+m. Reserved states should not be used as unknown operation or incompatibility with future versions may result. T1 T2 T3 NOP T0 NOP NOP T3 T4 NOP NOP T3n /CK CK COMMAND WRITE WL = 3 WDQS DQ T0 COMMAND WDQS DQ WRITE T2 /CK CK NOP T4n WL = 4 Burst Length = 4 in the cases shown DON'T CARE TRANSITIONING DATA 12 / 54 Rev. 1.3 May 2007 256M GDDR3 SDRAM K4J55323QI K4J55323QI TEST MODE The normal operating mode is selected by issuing a MODE REGISTER SET command with bits A7 set to zero, and bits A0-A6 and A8A11 A8A11 set to the desired values. Test mode is entered by issuing a MODE REGISTER SET command with bit A7 set to one, and bits A0A6 and A8-A11 A8-A11 set to the desired values. Test mode functions are specific to each Dram Manufacturer and its exact functions are hidden from the user. DLL RESET The normal operating mode is selected by issuing a MODE REGISTER SET command with bit A7 set to zero, and bits A0-A6 and A8A11 A8A11 set to the desired values. A DLL reset is initiated by issuing a MODE REGISTER SET command with bit A8 set to one, and bits A0A7 and A9-A11 A9-A11 set to the desired values. When a DLL Reset is complete the GDDR3 SDRAM reset bit 8 of the mode register to a zero. After DLL Reset MRS, Power down can not be issued within 10 clock. In case the clock frequency need to be changed after the power-up, 256Mb GDDR3 doesn't require DLL reset. Instead, DLL should be disabled first before the frequency changed and then change the clock frequency as needed. After the clock frequency changed, there needed some time till clock become stable and then enable the DLL and then 20K cycle required to lock the DLL Clock frequency change sequence after the power-up(example) Command EMRS DLL Disable Wait until clock stable 13 / 54 EMRS DLL Enable ~ ~ CK,CK ~ 1000Mbps ~ 700Mbps Any Command 20K cycle for DLL locking time Rev. 1.3 May 2007 256M GDDR3 SDRAM K4J55323QI K4J55323QI 7.4 EXTENDED MODE REGISTER SET(EMRS) The extended mode register stores the data output driver strength and on-die termination options. The extended mode register is written by asserting low on CS, RAS, CAS, WE and high on BA0(The GDDR3 SDRAM should be in all bank precharge with CKE already high prior to writing into the extended mode register). The state of address pins A0 ~ A11 and BA0,BA1 in the same cycle as CS, RAS, CAS and WE going low are written in the extended mode register. The minimum clock cycles specified as tMRD are required to complete the write operation in the extended mode register. 4 kinds of the output driver strength are supported by EMRS (A1, A0) code. The mode register contents can be changed using the same command and clock cycle requirements during operation as long as all banks are in the idle state. "High" on BA0 is used for EMRS. Refer to the table for specific codes. BA1 BA0 A11 A10 A9 A8 A7 A6 A5 0 1 Term ID RON 0 tWR DLL A4 tWR A3 A2 A1 Termination A0 Drive Strength DLL Vendor ID 1 MRS EMRS A10 Drive Strength 0 Off 1 On DLL A1 A0 1 Vendor ID Enable Disable 0 0 1 30 0 40 1 0 0 An ~ A0 0 1 0 BA0 A6 0 BA1 1 50 Drive Strength Autocal ADDR/CMD Termination A11 Termination 0 Default 1 Half of default Data Termination A3 Default value is determined by CKE status at the rising edge of RESET during power-up tWR A7 Ron of Pull-up A5 A4 tWR 0 0 0 11 RON 0 0 1 13 0 40 0 1 0 60 0 1 1 0 0 0 1 1 0 1 1 1 Reserved 1 0 ZQ/4 1 1 ZQ/2 9 1 0 8 1 ODT Disabled*1 7 1 Termination 6 1 0 5 1 A2 0 10 A9 RFU(Reserved for future use) should stay "0" during EMRS cycle * ZQ : Resistor connection pin for On-die termination * 1 : ALL ODT will be disabled 14 / 54 Rev. 1.3 May 2007 256M GDDR3 SDRAM K4J55323QI K4J55323QI DLL ENABLE/DISABLE The DLL must be enabled for normal operation. DLL enable is required during power-up initialization and upon returning to normal operation after disabling the DLL for debugging or evaluation. (When the device exits self refresh mode, the DLL is enabled automatically.) Any time the DLL is enabled, 20K clock cycles must occur before an any command can be issued. DATA TERMINATION The Data Termination, DT, is used to determine the value of the internal data termination resisters. The GDDR3 SDRAM supports 60 and 120 termination. The termination may also be disabled for testing and other purposes. DATA DRIVER IMPEDANCE The Data Driver impedance (DZ) is used to determine the value of the data drivers impedance. When auto calibration is used the data driver impedance is set to RQ/6 and it's tolerance is determined by the calibration accuracy of the device. When any other value is selected the target impedance is set nominally to the desired impedance. However, the accuracy is now determined by the device's specific process corner, applied voltage and operating temperature. ADDITIVE LATENCY The Additive Latency function (AL) is used to optimize the command bus efficiency. The AL value is used to determine the number of clock cycles that is to be added to CL after CAS is captured by the rising edge of CK. Thus the total CAS latency is determined by adding CL and AL. 15 / 54 Rev. 1.3 May 2007 256M GDDR3 SDRAM K4J55323QI K4J55323QI 7.5 MANUFACTURERS VENDOR CODE AND REVISION IDENTIFICATION The Manufacturers Vendor Code, V, is selected by issuing a EXTENDED MODE REGISTER SET command with bits A10 set to one, and bits A0-A9 and A11 set to the desired values. When the V function is enabled the GDDR3 SDRAM will provide its manufacturers vendor code on DQ[3:0] and revision identification on DQ[7:4] Manufacturer DQ[3:0] Manufacturer DQ[3:0] Manufacturer DQ[3:0] Reserved 0 Hynix 6 Reserved C G-die 0000 Samsung 1 Mosel 7 Reserved D I-die 1001 Infineon 2 Winbond 8 Reserved E Elpida 3 ESMT 9 Micron F Etron 4 Reserved A Nanya 5 Reserved B Tc4 Td5 Revision ID DQ[7:4] Vendor ID Read T0 T1 Ta2 Tb3 Te6 Tf7 ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ CK tCH ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ RES ~ ~ CK tCL ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ CKE ~ ~ ~ ~ tIS tIH ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ COMMAND ~ ~ ~ ~ ~ ~ tIS tIH 200 cycle High ~ ~ ~ ~ ~ ~ ~ ~ tRP Precharge All Banks ~ ~ >20ns ~ ~ >20ns DQ[3:0] tMRD tMRD tMRD tMRD tRP Dummy_MRS w/ specified value Vendor Code EMRS Vendor_ID Off EMRS Vendor_ID On DON'T CARE 16 / 54 MRS Precharge All Banks 1st Auto Refresh TRANSITIONING DATA Rev. 1.3 May 2007 256M GDDR3 SDRAM K4J55323QI K4J55323QI 7.6 Clock frequency change sequence during the device operation Both existing tCK and desired tCK are in DLL-On mode - Change frequency from existing frequency to desired frequency - Issue Precharge All Banks command - Issue MRS command to reset the DLL while other fields are valid and required 20K tCK to lock the DLL - Issue Precharge All Banks command. Issue at least Auto-Refresh command NOP NOP Frequency Change PRE All Banks Precharge tFCHG MRS NOP AR NOP All Banks Precharge DLL Reset tRP PRE NOP NOP NOP NOP CMD CK CK tMRD 20tCK (DLL locking time) Existing tCK is in DLL-on mode while desired tCK is in DLL-off mode - Issue Precharge All Banks command - Issue EMRS command to disable the DLL - Issue Precharge All Banks command - Change the frequency from existing to desired. - Issue Auto-Refresh command at least two. Issue MRS command EMRS PRE All Banks Precharge DLL OFF All Banks Precharge tRP NOP NOP NOP AR PRE CMD CK CK MRS NOP NOP NOP NOP Frequency Change tMRD tFCHG Clock frequency change in case existing tCK is in DLL-off mode while desired tCK is in DLL-on mode - Issue Precharge All Banks command and issue EMRS command to disable the DLL. - Issue Precharge All Banks command. - Change the clock frequency from existing to desired - Issue Precharge All Banks command. - Issue EMRS command to enable the DLL - Issue MRS command to reset the DLL and required 20K tCK to lock the DLL. - Issue Precharge All Banks command. - Issue Auto-Refresh command at least two tFCHG tRP 17 / 54 DLL On MRS DLL Reset tMRD PRE NOP All Banks Precharge EMRS PRE Frequency Change NOP tMRD NOP All Banks Precharge NOP tRP DLL OFF PRE All Banks Precharge EMRS PRE CMD CK CK AR All Banks Precharge tMRD 20tCK (DLL locking time) Rev. 1.3 May 2007 256M GDDR3 SDRAM K4J55323QI K4J55323QI 7.7 BOUNDARY SCAN FUNCTION GENERAL INFORMATION The 256Mb GDDR3 incorporates a modified boundary scan test mode as an optional feature. This mode doesn't operate in accordance with IEEE Standard 1149.1 - 1990. To save the current GDDR3 ball-out, this mode will scan parallel data input and output and the scanned data through WDQS0 pin controlled by an add-on pin, SEN which is located at V4 of 136 ball package. For the normal device operation other than boundary scan, there required device re-initialization by device power-off and then power-on. DISABLING THE SCAN FEATURE It is possible to operate the 256Mb GDDR3 without using the boundary scan feature. SEN(at V-4 of 136 ball package) should be tied LOW(VSS) to prevent the device from entering the boundary scan mode. The other pins which are used for scan mode, RES, MF, WDQS0 and CS# will be operating at normal GDDR3 function when SEN is de-asserted. Figure 1. Internal Block Diagram (Reference Only) Dedicated Scan Flops (1per signal under test) Tie to Iogic 0 DM0 D DQ CK Pins under test DQS D DQ CK DQ4 D DQ CK The following lists the rest of the signals on the scan chain: DQ[3:0], DQ[31:6], RDQS[3:1], WDQS[3:1], DM[3:1], RFU, CAS#, WE#, CKE, BA[1:0], A[11:0], CK, CK# and ZQ Two RFU's(J-2 and J-3 on 136-ball package) and one RFM(H-10 on 136-ball package) will be on the scan chain and will be read as a logic "0" RDQS0 RES (SSH,Scan Shift) D The following lists signals not on the scan chain: NC, VDD, VSS, VDDQ, VSSQ, VREF DQ CK In case ZQ pin is connected to the external resistor, it will be read as logic "0". However, if the ZQ pin is open, it will be read as floating. Accordingly, ZQ pin should be driven by any signal. CS# (SCK, Scan Clock) WDQS0 (SOUT,Scan Out) RFU at V-4 (SEN, Scan Enable) Puts device into scan mode and re-maps pins to scan functionality MF (SOE#, Output Enable) 18 / 54 Rev. 1.3 May 2007 256M GDDR3 SDRAM K4J55323QI K4J55323QI BOUNDARY SCAN EXIT ORDER BIT# BALL BIT# BALL BIT# BALL BIT# BALL BIT# BALL BIT# BALL 1 D-3 13 E-10 25 K-11 37 R-10 49 L-3 61 G-4 2 C-2 14 F-10 26 K-10 38 T-11 50 M-2 62 F-4 3 C-3 15 E-11 27 K-9 39 T-10 51 M-4 63 F-2 4 B-2 16 G-10 28 M-9 40 T-3 52 K-4 64 G-3 5 B-3 17 F-11 29 M-11 41 T-2 53 K-3 65 E-2 6 A-4 18 G-9 30 L-10 42 R-3 54 K-2 66 F-3 7 B-10 19 H-9 31 N-11 43 R-2 55 L-4 67 E-3 8 B-11 20 H-10 32 M-10 44 P-3 56 J-3 9 C-10 21 H-11 33 N-10 45 P-2 57 J-2 10 C-11 22 J-11 34 P-11 46 N-3 58 H-2 11 D-10 23 J-10 35 P-10 47 M-3 59 H-3 12 D-11 24 L-9 36 R-11 48 N-2 60 H-4 *Note : 1. When the device is in scan mode, the mirror function will be disabled and none of the pins are remapped. 2. Since the other input of the MUX for DM0 tied to GND, the device will output the continuous zeros after scanning a bit #67, if the chip stays in scan shift mode. 3. Two RFU balls(#56and #57) and one RFM ball(#20) in the scan order will be read as a logic"0". SCAN PIN DESCRIPTION Package Ball Symbol Normal Function Type V-9 SSH RES Input Scan shift. Capture the data input from the pad at logic LOW and shift the data on the chain at logic HIGH. F-9 SCK CS Input Scan Clock. Not a true clock, could be a single pulse or series of pulses. All scan inputs will be referenced to rising edge of the scan clock. D-2 SOUT WDQS0 Output V-4 A-9 SEN SOE RFU MF Description Scan Output. Input Scan Enable. Logic HIGH would enable the device into scan mode and will be disabled at logic LOW. Must be tied to GND when not in use. Input Scan Output Enable. Enables (registered LOW) and disables (registered HIGH) SOUT data. This pin will be tied to VDD or GND through a resistor (typically 1K ) for normal operation. Tester needs to overdrive this pin guarantee the required input logic level in scan mode. *Note : 1. When SEN is asserted, no commands are to be executed by the GDDR3 SDRAM. This applies to both user commands and manufacturing commands which may exist while RES is de-asserted. 2. All scan functionalities are valid only after the appropriate power-up and initialization sequence. (RES and CKE, to set the ODT of the C/A) 3. In scan mode, the ODT for the address and control lines set to a nominal termination value of ZQ. The ODT for DQ's will be disabled. It is not necessary for the termination to be calibrated. 4. In a double-load clam-shell configuration, SEN will be asserted to both devices. Separate two SOE's should be provided to top and bottom devices to access the scanned output. When either of the devices is in scan mode, SOE for the other device which not in a scan will be disabled. 19 / 54 Rev. 1.3 May 2007 256M GDDR3 SDRAM K4J55323QI K4J55323QI SCAN DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS PARAMETER/CONDITON SYMBOL MIN MAX UNITS NOTES Input High (Logic 1) Voltage VIH(DC) VREF+0.15 - V 1,2 Input Low (Logic 0) Voltage VIL(DC) - VREF-0.15 V 1,2 *Note : 1. The parameter applies only when SEN is asserted. 2. All voltages referenced to GND. Figure 2. Scan Capture Timing Not a true clock, but a single pulse or series of pulses SCK tSES SEN SSH LOW tSCS SOE tSDS tSDS Pins under Test VALID DON'T CARE Figure 3.Scan Shift Timing SCK tSES SEN tSCS SSH tSCS SOE SOUT tSAC Scan Out bit 0 Scan Out bit 1 Scan Out bit 2 Scan Out bit 3 tSOH TRANSITIONING DATA 20 / 54 Rev. 1.3 May 2007 256M GDDR3 SDRAM K4J55323QI K4J55323QI SCAN AC ELECTRICAL CHARACTERISTICS PARAMETER/CONDITON SYMBOL MIN MAX UNITS NOTES tSCK 40 - ns 1 Scan enable setup time tSES 20 - ns 1,2 Scan enable hold time tSEH 20 - ns 1 Clock Clock cycle time Scan Command Time Scan command setup time for SSH, SOE# and SOUT tSCS 14 - ns 1 Scan command hold time for SSH, SOE# and SOUT tSCH 14 - ns 1 Scan Capture Time Scan capture setup Time tSDS 10 - ns 1 Scan capture hold Time tSCH 10 - ns 1 Scan Shift Time Scan clock to valid scan output tSAC - 6 ns 1 Scan clock to scan output hold tSOH 1.5 - ns 1 *Note : 1. The parameter applies only when SEN is asserted. 2. Scan Enable should be issued earlier than other Scan Commands by 3ns. Figure 4. Scan Initialization Sequence tSCH tSCS tSCH tSES tSCS tSCS VALID VALID tSDS tSDH SOE# SCK SEN tSCS tSDS tSDH CKE (Quad-load C/A) tATS tATS CKE (Dual-load C/A) RES (SSH in Scan Mode) VREF VDDQ VDD SOUT Scan Out Bit0 tSDS tSDH VALID Pins Under Test T = 200us RESET at power - up Boundary Scan Mode Note : To set the pre-defined ODT for C/A, a boundary scan mode should be issued after an appropriate ODT initialization sequence with RES and CKE signals 21 / 54 Rev. 1.3 May 2007 256M GDDR3 SDRAM K4J55323QI K4J55323QI 7.8 Mirror Function The GDDR3 SDRAM provides a mirror function (MF) ball to change the physical location of the control lines and all address lines which helps to route devices back to back. The MF ball will affect RAS, CAS, WE, CS and CKE on balls H3, F4, H9, F9 and H4 respectively and A0, A1, A2, A3, A4, A5, A6, A7, A8, A9, A10, A11, BA0 and BA1 on balls K4, H2, K3, M4, K9, H11, K10, L9, K11, M9, K2, L4, G4 and G9 respectively and only detects a DC input. The MF ball should be tied directly to VSS or VDD depending on the control line orientation desired. When the MF ball is tied low the ball orientation is as follows, RAS - H3, CAS - F4, WE - H9, CS - F9, CKE H4, A0 - K4, A1 - H2, A2 - K3, A3 - M4, A4 - K9, A5 - H11, A6 - K10, A7 - L9, A8 - K11, A9 - M9, A10 - K2, A11 - L4, BA0 - G4 and BA1 - G9. The high condition on the MF ball will change the location of the control balls as follows; CS - F4, CAS - F9, RAS - H10, WE - H4, CKE - H9, A0 - K9, A1 - H11, A2 - K10, A3 - M9, A4 - K4, A5 - H2, A6 - K3, A7 - L4, A8 - K2, A9 - M4, A10 - K11, A11 - L9, BA0 - G9 and BA1 - G4. Mirror Function Signal Mapping PIN MF LOGIC STATE HIGH LOW RAS H10 H3 CAS F9 F4 WE H4 H9 CS F4 F9 CKE H9 H4 A0 K9 K4 A1 H11 H2 A2 K10 K3 A3 M9 M4 A4 K4 K9 A5 H2 H11 A6 K3 K10 A7 L4 L9 A8 K2 K11 A9 M4 M9 A10 K11 K2 A11 L9 L4 BA0 G9 G4 BA1 G4 G9 22 / 54 Rev. 1.3 May 2007 256M GDDR3 SDRAM K4J55323QI K4J55323QI 7.9 OPERATIONS /CK CK 7.9.1 BANK/ROW ACTIVATION Before any READ or WRITE commands can be issued to a banks within the GDDR3 SDRAM, a row in that bank must be "opened." This is accomplished via the ACTIVE command, which selects both the bank and the row to be activated. After a row is opened with an ACTIVE command, a READ or WRITE command may be issued to that row, subject to the tRCD specification. tRCD(min) should be divided by the clock period and rounded up to the next whole number to determine the earliest clock edge after the ACTIVE command in which a READ or WRITE command can be entered. For example, a tRCD specification of 16ns with a 800MHz clock (1.25ns period) results in 12.8 clocks rounded to 13. This is reflected in below figure, which covers any case where 12