K4E170811C K4E160811C K4E170812C K4E160812C K4E170811C-B K4E160811C-B - Datasheet Archive

 

K4E170812C, K4E160812C CMOS DRAM 2M x 8Bit CMOS Dynamic RAM with Extended Data Out DESCRIPTION This is a family of 2,097,152 x 8

 

K4E170811C K4E170811C, K4E160811C K4E160811C K4E170812C K4E170812C, K4E160812C K4E160812C CMOS DRAM 2M x 8Bit CMOS Dynamic RAM with Extended Data Out DESCRIPTION This is a family of 2,097,152 x 8 bit Extended Data Out CMOS DRAMs. Extended Data Out Mode offers high speed random access of memory cells within the same row, so called Hyper Page Mode. Power supply voltage (+5.0V or +3.3V), refresh cycle (2K Ref. or 4K Ref.), access time (-50 or -60), power consumption(Normal or Low power) and package type(SOJ or TSOP-II) are optional features of this family. All of this family have CAS-before-RAS refresh, RAS-only refresh and Hidden refresh capabilities. Furthermore, Self-refresh operation is available in L-version. This 2Mx8 EDO Mode DRAM family is fabricated using Samsungs advanced CMOS process to realize high band-width, low power consumption and high reliability. It may be used as graphic memory unit for microcomputer and personal computer. FEATURES · Extended Data Out Mode operation · Part Identification (Fast page mode with Extended Data Out) · CAS-before-RAS refresh capability - K4E170811C-B K4E170811C-B(F) (5V, 4K Ref.) - K4E160811C-B K4E160811C-B(F) (5V, 2K Ref.) - K4E170812C-B K4E170812C-B(F) (3.3V, 4K Ref.) - K4E160812C-B K4E160812C-B(F) (3.3V, 2K Ref.) · RAS-only and Hidden refresh capability · Self-refresh capability (L-ver only) · Fast parallel test mode capability · TTL(5V)/LVTTL(3.3V) compatible inputs and outputs · Active Power Dissipation · Early Write or output enable controlled write Unit : mW 3.3V Speed · JEDEC Standard pinout 5V · Available in Plastic SOJ and TSOP(II) packages 4K 2K 4K 2K · Single +5V±10% power supply (5V product) -50 324 396 495 605 · Single +3.3V±0.3V power supply (3.3V product) -60 288 360 440 550 FUNCTIONAL BLOCK DIAGRAM · Refresh Cycles VCC K4E170811C K4E170811C 5V K4E170812C K4E170812C Refresh cycle Refresh period Normal 3.3V K4E160811C K4E160811C 5V K4E160812C K4E160812C 4K L-ver RAS CAS W Control Clocks Vcc Vss VBB Generator 64ms Data in 128ms 3.3V 2K Refresh Timer 32ms Refresh Control Refresh Counter · Performance Range Speed tRAC tCAC tRC tHPC Remark -50 50ns 13ns 84ns 20ns 5V/3.3V -60 60ns 15ns 104ns 25ns A0-A11 A0-A11 (A0 - A10) *1 A0 - A8 (A0 - A9)*1 Buffer Row Decoder Memory Array 2,097,152 x8 Cells Row Address Buffer 5V/3.3V Sense Amps & I/O Part NO. DQ0 to DQ7 Data out Col. Address Buffer Column Decoder Note) *1 : 2K Refresh SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice. Buffer OE K4E170811C K4E170811C, K4E160811C K4E160811C K4E170812C K4E170812C, K4E160812C K4E160812C CMOS DRAM PIN CONFIGURATION (Top Views) · K4E17 K4E17(6)0811(2)C-F · K4E17 K4E17(6)0811(2)C-B VCC DQ0 DQ1 DQ2 DQ3 W RAS *A11(N.C) A10 A0 A1 A2 A3 VCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC DQ0 DQ1 DQ2 DQ3 W RAS *A11(N.C) A10 A0 A1 A2 A3 VCC VSS DQ7 DQ6 DQ5 DQ4 CAS OE A9 A8 A7 A6 A5 A4 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 *A11 is N.C for K4E160811 K4E160811(2)C(5V/3.3V, 2K Ref. product) B : 300mil 28 SOJ F : 300mil 28 TSOP II Pin Name Pin Function A0 - A11 Address Inputs (4K Product) A0 - A10 Address Inputs (2K Product) DQ0 - 7 Data In/Out VSS Ground RAS Row Address Strobe CAS Column Address Strobe W Read/Write Input OE Data Output Enable VCC Power(+5V) Power(+3.3V) N.C No Connection (2K Ref. product) 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VSS DQ7 DQ6 DQ5 DQ4 CAS OE A9 A8 A7 A6 A5 A4 VSS K4E170811C K4E170811C, K4E160811C K4E160811C K4E170812C K4E170812C, K4E160812C K4E160812C CMOS DRAM ABSOLUTE MAXIMUM RATINGS Parameter Rating Symbol Units 3.3V 5V VIN,VOUT -0.5 to +4.6 -1.0 to +7.0 V Voltage on VCC supply relative to VSS VCC -0.5 to +4.6 -1.0 to +7.0 V Storage Temperature Tstg -55 to +150 -55 to +150 °C Power Dissipation PD 1 1 W IOS Address 50 50 mA Voltage on any pin relative to V SS Short Circuit Output Current * Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS (Voltage referenced to Vss, TA= 0 to 70°C) Parameter 3.3V Symbol 5V Units Min Typ Max Min Typ Max Supply Voltage VCC 3.0 3.3 3.6 4.5 5.0 5.5 V Ground VSS 0 0 0 0 0 0 V Input High Voltage VIH 2.0 - VCC+0.3*1 2.4 - VCC+1.0*1 V Input Low Voltage VIL -0.3*2 - 0.8 -1.0*2 - 0.8 V *1 : VCC+1.3V/15ns(3.3V), VCC+2.0V/20ns(5V), Pulse width is measured at VCC *2 : -1.3V/15ns(3.3V), -2.0V/20ns(5V), Pulse width is measured at VSS DC AND OPERATING CHARACTERISTICS (Recommended operating conditions unless otherwise noted.) Max Min Max Units II(L) -5 5 uA Output Leakage Current (Data out is disabled, 0VVOUTVCC) IO(L) -5 5 uA Output High Voltage Level(IOH=-2mA) VOH 2.4 - V Output Low Voltage Level(IOL=2mA) VOL - 0.4 V Input Leakage Current (Any input 0VINVIN+0.5V, all other input pins not under test=0 Volt) 5V Symbol Input Leakage Current (Any input 0VINVIN+0.3V, all other input pins not under test=0 Volt) 3.3V Parameter II(L) -5 5 uA Output Leakage Current (Data out is disabled, 0VVOUTVCC) IO(L) -5 5 uA Output High Voltage Level(IOH=-5mA) VOH 2.4 - V Output Low Voltage Level(IOL=4.2mA) VOL - 0.4 V K4E170811C K4E170811C, K4E160811C K4E160811C K4E170812C K4E170812C, K4E160812C K4E160812C CMOS DRAM DC AND OPERATING CHARACTERISTICS (Continued) Symbol Power Speed ICC1 Dont care ICC2 Max Units K4E170812C K4E170812C K4E160812C K4E160812C K4E170811C K4E170811C K4E160811C K4E160811C -50 -60 90 80 110 100 90 80 110 100 mA mA mA Normal L Dont care 1 1 1 1 2 1 2 1 mA mA ICC3 Dont care -50 -60 90 80 110 100 90 80 110 100 mA mA mA ICC4 Dont care -50 -60 80 70 90 80 80 70 90 80 mA mA mA ICC5 Normal L Dont care 0.5 200 0.5 200 1 250 1 250 mA uA ICC6 Dont care -50 -60 90 80 110 100 90 80 110 100 mA mA mA ICC7 L Dont care 250 250 300 300 uA ICCS L Dont care 200 200 250 250 uA ICC1* : Operating Current (RAS and CAS cycling @tRC=min.) ICC2 : Standby Current (RAS=CAS=W=VIH) ICC3* : RAS-only Refresh Current (CAS=VIH, RAS cycling @tRC=min.) ICC4* : Hyper Page Mode Current (RAS=VIL, CAS, Address cycling @tHPC=min.) ICC5 : Standby Current (RAS=CAS=W=VCC-0.2V) ICC6* : CAS-Before-RAS Refresh Current (RAS and CAS cycling @t RC=min.) ICC7 : Battery back-up current, Average power supply current, Battery back-up mode Input high voltage(VIH)=VCC-0.2V, Input low voltage(VIL)=0.2V, CAS=0.2V, DQ=Dont care, TRC=31.25us(4K/L-ver), 62.5us(2K/L-ver), TRAS=TRASmin~300ns ICCS : Self Refresh Current RAS=CAS=VIL, W=OE=A0 ~ A11=VCC-0.2V or 0.2V, DQ0 ~ DQ7=VCC-0.2V, 0.2V or Open *Note : ICC1, ICC3, I CC4 and ICC6 are dependent on output loading and cycle rates. Specified values are obtained with the output open. ICC is specified as an average current. In ICC1, ICC3 and ICC6, address can be changed maximum once while RAS=VIL. In ICC4, address can be changed maximum once within one Hyper page mode cycle time, tHPC. K4E170811C K4E170811C, K4E160811C K4E160811C K4E170812C K4E170812C, K4E160812C K4E160812C CMOS DRAM CAPACITANCE (TA=25°C, VCC=5V or 3.3V, f=1MHz) Parameter Symbol Min Max Units Input capacitance [A0 ~ A11] CIN1 - 5 pF Input capacitance [RAS, CAS, W, OE] CIN2 - 7 pF Output capacitance [DQ0 - DQ7] CDQ - 7 pF AC CHARACTERISTICS (0°CTA70 CTA70°C, See note 1,2) Test condition (5V device) : VCC=5.0V±10%, Vih/Vil=2.4/0.8V, Voh/Vol=2.0/0.8V Test condition (3.3V device) : VCC=3.3V±0.3V, Vih/Vil=2.0/0.8V, Voh/Vol=2.0/0.8V Parameter -50 Symbol Min -60 Max Min Units Notes Max Random read or write cycle time tRC 84 104 ns Read-modify-write cycle time tRWC 116 140 ns Access time from RAS tRAC 50 60 ns 3,4,10 Access time from CAS tCAC 13 15 ns 3,4,5 Access time from column address tAA 25 30 ns 3,10 CAS to output in Low-Z tCLZ 3 ns 3 Output buffer turn-off delay from CAS tCEZ 3 ns 6,14 OE to output in Low-Z tOLZ 3 ns 3 Transition time (rise and fall) tT 2 ns 2 RAS precharge time tRP 30 RAS pulse width tRAS 50 RAS hold time tRSH 13 15 ns CAS hold time tCSH 38 45 ns CAS pulse width tCAS 8 10K 10 10K ns RAS to CAS delay time tRCD 20 37 20 45 ns 4 RAS to column address delay time tRAD 15 25 15 30 ns 10 CAS to RAS precharge time tCRP 5 5 ns Row address set-up time tASR 0 0 ns Row address hold time tRAH 10 10 ns Column address set-up time tASC 0 0 ns Column address hold time tCAH 8 10 ns Column address to RAS lead time tRAL 25 30 ns Read command set-up time tRCS 0 0 ns Read command hold time referenced to CAS tRCH 0 0 ns 8 Read command hold time referenced to RAS tRRH 0 0 ns 8 Write command hold time tWCH 10 10 ns Write command pulse width tWP 10 10 ns Write command to RAS lead time tRWL 13 15 ns Write command to CAS lead time tCWL 8 10 ns 3 13 3 15 3 50 2 50 40 10K 60 ns 10K ns K4E170811C K4E170811C, K4E160811C K4E160811C K4E170812C K4E170812C, K4E160812C K4E160812C CMOS DRAM AC CHARACTERISTICS (Continued) Parameter -50 Symbol Min Data set-up time tDS tDH 8 Refresh period (2K, Normal) Refresh period (4K, Normal) Max 0 Data hold time -60 Min Units Notes ns 9 ns 9 Max 0 10 tREF 32 32 ms tREF 64 64 ms Refresh period (L-ver) tREF 128 128 ms Write command set-up time tWCS 0 0 ns 7 CAS to W delay time tCWD 30 34 ns 7 RAS to W delay time tRWD 67 79 ns 7 Column address to W delay time tAWD 42 49 ns 7 CAS precharge to W delay time tCPWD 47 54 ns CAS set-up time (CAS -before-RAS refresh) tCSR 5 5 ns CAS hold time (CAS -before-RAS refresh) tCHR 10 10 ns RAS to CAS precharge time tRPC 5 5 ns Access time from CAS precharge tCPA ns 3 tHPC 20 25 ns 13 tHPRWC 47 56 ns 13 CAS precharge time (Hyper Page cycle) tCP 8 10 ns RAS pulse width (Hyper Page cycle) tRASP 50 RAS hold time from CAS precharge tRHCP 30 OE access time tOEA OE to data delay tOED 13 Output buffer turn off delay time from OE tOEZ 3 OE command hold time tOEH 13 15 ns Write command set-up time (Test mode in) tWTS 10 10 ns 11 Write command hold time (Test mode in) tWTH 10 10 ns 11 W to RAS precharge time(C-B-R refresh) tWRP 10 10 ns W to RAS hold time(C-B-R refresh) tWRH 10 10 ns Output data hold time tDOH 5 5 ns Output buffer turn off delay from RAS tREZ 3 13 3 15 ns 6,14 Output buffer turn off delay from W tWEZ 3 13 3 15 ns 6 W to data delay Hyper Page cycle time Hyper Page read-modify-write cycle time 28 200K 35 60 200K 35 13 ns 15 15 13 3 ns ns ns 15 ns 6 tWED 15 15 ns OE to CAS hold time tOCH 5 5 ns CAS hold time to OE tCHO 5 5 ns OE precharge time tOEP 5 5 ns W pulse width (Hyper Page Cycle) tWPE 5 5 ns RAS pulse width (C-B-R self refresh) tRASS 100 100 us RAS precharge time (C-B-R self refresh) tRPS 90 110 ns 15,16,17 tCHS -50 -50 ns 15,16,17 CAS hold time (C-B-R self refresh) 15,16,17 K4E170811C K4E170811C, K4E160811C K4E160811C K4E170812C K4E170812C, K4E160812C K4E160812C CMOS DRAM ( Note 11 ) TEST MODE CYCLE Parameter -50 Symbol Min Random read or write cycle time tRC tRWC Max 89 Read-modify-write cycle time -60 121 Access time from RAS Min Units Note Max 109 ns 145 ns tRAC 55 65 ns 3,4,10,12 Access time from CAS tCAC 18 20 ns 3,4,5,12 Access time from column address tAA 30 35 ns 3,10,12 RAS pulse width tRAS 55 10K 65 10K ns CAS pulse width tCAS 13 10K 15 10K ns RAS hold time tRSH 18 20 ns CAS hold time tCSH 43 50 ns Column address to RAS lead time tRAL 30 35 ns CAS to W delay time tCWD 35 39 ns 7 RAS to W delay time tRWD 72 84 ns 7 Column address to W delay time tAWD 47 54 ns 7 CAS precharge to W delay time tCPWD 52 59 ns Hyper Page cycle time tHPC 25 30 ns 13 Hyper Page read-modify-write cycle time tHPRWC 53 61 ns 13 RAS pulse width (Hyper Page cycle) tRASP 55 Access time from CAS precharge tCPA OE access time tOEA OE to data delay tOED 18 20 ns tOEH 18 20 ns OE command hold time 200K 65 200K ns 33 40 ns 18 20 ns 3 K4E170811C K4E170811C, K4E160811C K4E160811C K4E170812C K4E170812C, K4E160812C K4E160812C CMOS DRAM NOTES 1. An initial pause of 200us is required after power-up followed by any 8 RAS-only refresh or CAS-before-RAS refresh cycles before proper device operation is achieved. 2. VIH(min) and VIL(max) are reference levels for measuring timing of input signals. Transition times are measured between VIH(min) and V IL(max) and are assumed to be 2ns for all inputs. 3. Measured with a load equivalent to 2 TTL(5V)/1 TTL(3.3V) loads and 100pF. 4. Operation within the tRCD(max) limit insures that tRAC(max) can be met. tRCD(max) is specified as a reference point only. If tRCD is greater than the specified tRCD(max) limit, then access time is controlled exclusively by tCAC. 5. Assumes that tRCDtRCD(max). 6. This parameter defines the time at which the output achieves the open circuit condition and is not referenced to Voh or Vol. 7. tWCS, tRWD, tCWD and tAWD are non restrictive operating parameters. They are included in the data sheet as electrical characteristics only. If tWCStWCS(min), the cycle is an early write cycle and the data output will remain high impedance for the duration of the cycle. If tCWDtCWD(min), tRWDtRWD(min) and tAWDtAWD(min), then the cycle is a read-modify-write cycle and the data output will contain the data read from the selected address. If neither of the above conditions is satisfied, the condition of the data out is indeterminate. 8. Either tRCH or tRRH must be satisfied for a read cycle. 9. These parameters are referenced to CAS falling edge in early write cycles and to W falling edge in OE controlled write cycle and read-modify-write cycles. 10. Operation within the tRAD(max) limit insures that tRAC(max) can be met. tRAD(max) is specified as a reference point only. If tRAD is greater than the specified tRAD(max) limit, then access time is controlled by tAA. 11. These specifications are applied in the test mode. 12. In test mode read cycle, the value of tRAC, tAA, tCAC is delayed by 2ns to 5ns for the specified values. These parameters should be specified in test mode cycles by adding the above value to the specified value in this data sheet. 13. tASC6ns, Assume tT = 2.0ns 14. If RAS goes high before CAS high going, the open circuit condition of the output is achieved by CAS high going. If CAS goes high before RAS high going, the open circuit condition of the output is achieved by RAS high going. 15. If tRASS100us, then RAS precharge time must use tRPS instead of tRP. 16. For RAS-only refresh and burst CAS-before-RAS refresh mode, 4096(4K)/2048(2K) cycles of burst refresh must be executed within 64ms/32ms before and after self refresh, in order to meet refresh specification. 17. For distributed CAS-before-RAS with 15.6us interval CAS-before-RAS refresh should be executed with in 15.6us immediately before and after self refresh in order to meet refresh specification. K4E170811C K4E170811C, K4E160811C K4E160811C K4E170812C K4E170812C, K4E160812C K4E160812C CMOS DRAM READ CYCLE tRC tRAS RAS VIL - tCSH tCRP CAS tRP VIH - tRCD tCRP tRSH VIH - tCAS VIL - tRAD tASR A VIH VIL - tRAH tRAL tASC tCAH ROW ADDRESS COLUMN ADDRESS tRCH tRCS W tRRH VIH VIL - tWEZ tCEZ tAA OE VIH - tOEZ tOEA VIL - tOLZ tCAC DQ0 ~ DQ3(7) VOH VOL - tRAC OPEN tCLZ tREZ DATA-OUT Dont care Undefined K4E170811C K4E170811C, K4E160811C K4E160811C K4E170812C K4E170812C, K4E160812C K4E160812C CMOS DRAM WRITE CYCLE ( EARLY WRITE ) NOTE : DOUT = OPEN tRC tRAS RAS tRP VIH VIL - tCSH tCRP CAS tRSH VIH VIL - VIH VIL - tCRP tCAS tRAD tASR A tRCD tRAH tASC ROW ADDRESS tRAL tCAH COLUMN ADDRESS tCWL tRWL tWCS W OE VIH - tWCH tWP VIL - VIH VIL - DQ0 ~ DQ3(7) VIH VIL - tDS tDH DATA-IN Dont care Undefined K4E170811C K4E170811C, K4E160811C K4E160811C K4E170812C K4E170812C, K4E160812C K4E160812C CMOS DRAM WRITE CYCLE ( OE CONTROLLED WRITE ) NOTE : DOUT = OPEN tRC tRAS RAS VIL - tCSH tCRP CAS tRP VIH - tRCD tRSH tCAS VIH - tCRP VIL - tRAD tRAL tASR A VIH VIL - tRAH tASC tCAH ROW ADDRESS COLUMN ADDRESS tCWL tRWL W OE tWP VIH VIL - VIH VIL - DQ0 ~ DQ3(7) VIH - tOED tDS tOEH tDH DATA-IN VIL - Dont care Undefined K4E170811C K4E170811C, K4E160811C K4E160811C K4E170812C K4E170812C, K4E160812C K4E160812C CMOS DRAM READ - MODIFY - WRITE CYCLE tRWC tRAS RAS VIL - tCRP CAS tRP VIH - tRCD tRSH VIH - tCAS VIL - tASR tRAD tRAH tASC tCAH tCSH A VIH VIL - ROW ADDR COLUMN ADDRESS tAWD tRWL tCWD W tCWL VIH - tWP VIL - tRWD OE tOEA VIH VIL - DQ0 ~ DQ3(7) VI/OH VI/OL - tOLZ tCLZ tCAC tAA tOED tOEZ tRAC VALID DATA-OUT tDS tDH VALID DATA-IN Dont care Undefined K4E170811C K4E170811C, K4E160811C K4E160811C K4E170812C K4E170812C, K4E160812C K4E160812C CMOS DRAM HYPER PAGE READ CYCLE tRP tRASP RAS VIH VIL - ¡ó tRHCP tCSH tHPC tCRP CAS VIH VIL - VIH VIL - tHPC tCP tCAS tCP tCAS tHPC tCP tCAS tCAS tRAD tASR A tRCD tRAH tASC ROW ADDR tCAH tASC COLUMN ADDRESS tCAH tASC COLUMN ADDRESS tCAH COLUMN ADDR tASC tCAH tREZ COLUMN ADDRESS tRAL tRCS W VIH - tCAC VIL - tAA tAA tCPA tOCH VIH - tOEA tCPA tCAC tCAC tAA tCPA OE tRRH tRCH tAA tCHO tOEP tOEA VIL - tOEP tCAC DQ0 ~ DQ3(7) VOH VOL - tDOH tRAC VALID DATA-OUT tOLZ tCLZ tOEZ tOEA tOEZ VALID DATA-OUT tOEZ VALID DATA-OUT VALID DATA-OUT Dont care Undefined K4E170811C K4E170811C, K4E160811C K4E160811C K4E170812C K4E170812C, K4E160812C K4E160812C CMOS DRAM HYPER PAGE WRITE CYCLE ( EARLY WRITE ) NOTE : DOUT = OPEN tRP tRASP RAS VIH - tRHCP VIL - ¡ó tHPC tCRP CAS tRCD tHPC tCP VIH - tCP tCAS VIL - tRSH tCAS tCAS tRAD ¡ó tCSH tASR A VIH VIL - tRAH ROW ADDR. tASC tCAH tASC tCAH COLUMN ADDRESS COLUMN ADDRESS tASC ¡ó ¡ó tCAH COLUMN ADDRESS tRAL tWCS W VIH - tWCH tWCS tWP tWP ¡ó tWCH tWP VIL - tCWL OE tWCS tWCH tCWL tCWL tRWL VIH - ¡ó VIL - ¡ó DQ0 ~ DQ3(7) VIH VIL - tDS tDH tDS tDH tDS tDH ¡ó VALID DATA-IN VALID DATA-IN ¡ó VALID DATA-IN Dont care Undefined K4E170811C K4E170811C, K4E160811C K4E160811C K4E170812C K4E170812C, K4E160812C K4E160812C CMOS DRAM HYPER PAGE READ-MODIFY-WRITE CYCLE tRP tRASP RAS VIH - tCSH VIL - tCRP CAS tHPRWC tRCD tCAS VIL - VIH VIL - tCAS tRAD tRAH ROW ADDR tRAL tCAH tASC tCAH tASC COL. ADDR COL. ADDR tRCS W tCRP tCP VIH - tASR A tRSH tRWL tCWL tCWL VIH - tWP VIL - tWP tCWD tCWD tAWD tRWD OE VIH - tAWD tCPWD tOEA tOEA VIL - tOED tOED tCAC tAA DQ0 ~ DQ3(7) VI/OH VI/OL - tDH tOEZ tCAC tAA tDS tDH tOEZ tDS tRAC tCLZ tCLZ tOLZ VALID DATA-OUT VALID DATA-IN tOLZ VALID DATA-OUT VALID DATA-IN Dont care Undefined K4E170811C K4E170811C, K4E160811C K4E160811C K4E170812C K4E170812C, K4E160812C K4E160812C CMOS DRAM HYPER PAGE READ AND WRITE MIXED CYCLE tRP tRASP RAS VIH - READ(tCAC) READ(tCPA) tHPC VIH VIL - tCP tASR A VIH VIL - tCAS tRAD tRAH tASC ROW ADDR tCAH COLUMN ADDRESS tCP tCAS tCAS tCAS tCAH tASC tRHCP tHPC tHPC tCP CAS READ(tAA) WRITE VIL - tCAH tASC COLUMN ADDRESS COL. ADDR tASC tCAH COL. ADDR tRAL tRCS W tRCH tRCS tRCH tWCH tRCH tWCS VIH VIL - tWPE tCLZ tWED tCPA OE VIH VIL - DQ0 ~ DQ3(7) VI/OH VI/OL - tOEA tCAC tAA tWEZ tDH tWEZ tREZ tAA tDS tCLZ tRAC VALID DATA-OUT VALID DATA-OUT VALID DATA-IN VALID DATA-OUT Dont care Undefined K4E170811C K4E170811C, K4E160811C K4E160811C K4E170812C K4E170812C, K4E160812C K4E160812C CMOS DRAM RAS - ONLY REFRESH CYCLE* NOTE : W, OE, DIN = Don t care DOUT = OPEN tRC RAS VIH - tRP tRAS VIL - tRPC tCRP CAS VIH VIL - tASR A tCRP VIH VIL - tRAH ROW ADDR CAS - BEFORE - RAS REFRESH CYCLE NOTE : OE , A = Dont care tRC tRP RAS VIH VIL - tRPC tCP CAS tRAS VIH - tRPC tCSR tCHR VIL - tWRP W tRP tWRH VIH VIL - DQ0 ~ DQ3(7) VOH VOL - tCEZ OPEN Dont care Undefined K4E170811C K4E170811C, K4E160811C K4E160811C K4E170812C K4E170812C, K4E160812C K4E160812C CMOS DRAM HIDDEN REFRESH CYCLE ( READ ) tRC RAS tRAS VIH - tRP tRAS VIL - tCRP CAS tRC tRP tRCD tRSH tCHR VIH VIL - tRAD tRAL tASR A VIH VIL - tRAH tASC ROW ADDRESS tCAH COLUMN ADDRESS tWRH tRCS W VIH VIL - tAA OE VIH - tOEA VIL - tCEZ tOLZ tCAC DQ0 ~ DQ3(7) VOH VOL - tCLZ tRAC OPEN tREZ tWEZ tOEZ DATA-OUT Dont care Undefined K4E170811C K4E170811C, K4E160811C K4E160811C K4E170812C K4E170812C, K4E160812C K4E160812C CMOS DRAM HIDDEN REFRESH CYCLE ( WRITE ) NOTE : DOUT = OPEN tRC RAS tRAS VIH - tRCD tRSH tCHR VIH VIL - tRAD tASR A tRP tRAS VIL - tCRP CAS tRC tRP VIH VIL - tRAH tASC ROW ADDRESS tRAL tCAH COLUMN ADDRESS tWRH tWRP tWCS W OE VIH - tWCH tWP VIL - VIH VIL - tDS DQ0 ~ DQ3(7) VIH VIL - tDH DATA-IN Dont care Undefined K4E170811C K4E170811C, K4E160811C K4E160811C K4E170812C K4E170812C, K4E160812C K4E160812C CMOS DRAM CAS - BEFORE - RAS SELF REFRESH CYCLE NOTE : OE, A = Dont care tRP RAS VIL - tRPC VIH - tCHS tCSR VIL - DQ0 ~ DQ3(7) VOH - tCEZ OPEN VOL - W tRPS tRPC tCP CAS tRASS VIH - VIH VIL - tWRP tWRH TEST MODE IN CYCLE NOTE : OE , A = Dont care tRC tRP RAS tRP tRAS VIH VIL - tRPC tRPC tCP CAS tCSR VIH - tWTS W tCHR VIL - tWTH VIH VIL - DQ0 ~ DQ3(7) VOH VOL - tOFF OPEN Dont care Undefined K4E170811C K4E170811C, K4E160811C K4E160811C K4E170812C K4E170812C, K4E160812C K4E160812C CMOS DRAM PACKAGE DIMENSION 28 SOJ 300mil Units : Inches (millimeters) 0.280 (7.11) 0.260 (6.61) 0.300 (7.62) 0.330 (8.39) 0.340 (8.63) #28 0.006 (0.15) 0.012 (0.30) #1 0.148 (3.76) MAX 0.027 (0.69) MIN 0.741 (18.82) MAX 0.720 (18.30) 0.730 (18.54) 0.0375 (0.95) 0.050 (1.27) 0.026 (0.66) 0.032 (0.81) 0.015 (0.38) 0.021 (0.53) 28 TSOP(II) 300mil 0.300 (7.62) 0.355 (9.02) 0.371 (9.42) Units : Inches (millimeters) 0.004 (0.10) 0.010 (0.25) 0.741 (18.81) MAX 0.721 (18.31) 0.729 (18.51) 0.037 (0.95) 0.050 (1.27) 0.047 (1.20) MAX 0.002 (0.05) MIN 0.012 (0.30) 0.020 (0.50) 0.010 (0.25) TYP 0.018 (0.45) 0.030 (0.75) 0~8 O