K1B5616B2M K1B5616BAM K1B5616BBM K1B2816B2A K1B2816BAA K1B2816BBA K1B6416B6C

This Application Note is applied to below products. - K1B5616B2M, K1B5616BAM, K1B5616BBM - K1B2816B2A, K1B2816BAA, K1B2816BBA -

Write method & Mode Change This Application Note is applied to below products. - K1B5616B2M K1B5616B2M, K1B5616BAM K1B5616BAM, K1B5616BBM K1B5616BBM - K1B2816B2A K1B2816B2A, K1B2816BAA K1B2816BAA, K1B2816BBA K1B2816BBA - K1B6416B6C K1B6416B6C, K1B3216BDD K1B3216BDD June. 2006 Product Planning & Application Engineering Team MEMORY DIVISION SAMSUNG ELECTRONICS Co., LTD Product Planning & Product Planning & Application Eng. Team Application Eng. Team The Leader in Memory Technology UtRAM Write Asynchronous Write WC1 A0 Address WC2 A1 A: Address D: Data EOW : End of Write WC: Write Cycle WP: Write Pulse WEb D1 DQ D2 EOW1 EOW2 WP1 WP2 EOW1 WP2 EOW2 UtRAM UtRAM UtRAM Cell Array Cell Array Cell Array Cell(A0) A0 D1 Buffer D1 A0 A1 D2 Cell(A0) D1 Buffer A0 A1 D2 Cell(A0) D1 Buffer D2 A1 * UtRAM stores the current data in the buffer at the end of current write cycle and writes it to the cell during the next Write cycle. "Late Write" * UtRAM accesses `Buffer' instead of `Cell(A0)' when A0 is input for Read before WC2. * `Late Write' is applied only for the Asynchronous Write. Product Planning & Product Planning & Application Eng. Team Application Eng. Team The Leader in Memory Technology UtRAM Write Synchronous Write Burst Write Start 2 Burst Write Start 1 Latency: 1 Burst Length: 2 CLK ADVb Address A0 WEb W: Write A2 W1 DQ W2 D1 W1 W3 W4 D3 D2 W2 D4 W3 W4 UtRAM UtRAM UtRAM UtRAM Cell Array Cell Array Cell Array Cell Array D1 Cell(A0) D1 Cell(A1) D1 Cell(A0) D2 D2 Cell(A1) D1 Cell(A0) D3 D2 Cell(A1) D1 Cell(A0) D4 D2 Cell(A1) Cell(A2) Cell(A2) D3 Cell(A2) D3 Cell(A2) Cell(A3) Cell(A3) Cell(A3) D4 Cell(A3) * UtRAM writes the current data directly in the cell during current write cycle. * UtRAM always accesses `cell' when any address is input for Read. Product Planning & Product Planning & Application Eng. Team Application Eng. Team The Leader in Memory Technology UtRAM Write Example Asynch Write Address 0000h DQ 0001h 1111h 5555h WEb Cell & Buffer Status at the End of each Write Cell(0000h) Cell(0000h) Data: * Address: 0000h Data: 1111h Buffer Buffer Data: 1111h Address:0001h Data: 5555h Synch Write Burst Write2 Burst Write1 CLK ADVb Address 0000h DQ 0002h 0000h 0001h 0002h 0003h WEb Cell Status at the End of each Write Product Planning & Product Planning & Application Eng. Team Application Eng. Team Cell(0000h) Data: 0000h Cell(0002h) Data: 0002h Cell(0001h) Data: 0001h Cell(0003h) Data: 0003h The Leader in Memory Technology Write Mode & Mode Change Mode Change Rule * UtRAM has 3 operating mode - Mode 1 : Asynch. Read / Asynch. Write - Mode 2: Synch Read / Asynch. Write - Mode 3: Synch Read / Synch. Write * Different Write schematic between Asynch write & Synch Write makes the Mode change Rule to be needed. * Mode1 to Mode2: no rule Write method for Mode 1 & Mode2 is Asynchronous Write. * Mode1(2) to Mode3: 1 Dummy Write is necessary to any address with any data right before the `Mode3 to Mode1(or2) change' * Mode3 to Mode1(2): 1 Dummy Write is necessary to the same address with same data which are used right before the `Mode1(2) to Mode3 change' Product Planning & Product Planning & Application Eng. Team Application Eng. Team The Leader in Memory Technology Write Mode & Mode Change Mode 1 (or Mode 2) 1. Last Asynch Write Mode3 2. MRS (Mode1 Mode3) 3. Synch Read (Mode 3) CLK ADVb Address DQ . 0000h 1111h 0000h 0000h *h 0000h WEb Cell & Buffer Status at the End of each Write Cell(0000h) Buffer Data: *h Cell(0000h) Address: 0000h Data: 1111h Data: *h * It is assumed that data for address 0001h is 0000h 1. Last write data(1111h) stores in Buffer. 2. Implements MRS and change the mode from `1' to `3' 3. Output data is *h instead of 1111h when the address 0000h is accessed because cell(0000h) is directly accessed in Mode 3 while the actual data is in the Buffer. "Dummy write" to transfer the data in the Buffer to Cell(0000h) is necessary before implementing MRS to change the mode from `1(or2)' to `3' Product Planning & Product Planning & Application Eng. Team Application Eng. Team The Leader in Memory Technology Write Mode & Mode Change Mode 3 Mode 1 (or Mode 2) 1. Last Asynch Write Address 0000h DQ 3. MRS (Mode1 2. Dummy Write . FFFFh 1111h Mode3) FFFFh WEb Cell & Buffer Status at the End of each Write Cell(0000h) Buffer Data: *h Cell(0000h) Address: 0000h Data: 1111h Buffer Cell(FFFFh) 4. Synch Write 5. MRS (Mode3 Data: 1111h Address: FFFFh Data: FFFFh Data: *h Mode1) 6. Asynch Read CLK ADVb Address . FFFFh DQ 5555h FFFFh FFFFh 6666h WEb Cell & Buffer Status at the End of each Write Product Planning & Product Planning & Application Eng. Team Application Eng. Team Cell(FFFFh) Cell(FFFFh) Data: 5555h Buffer The Leader in Memory Technology Data: 5555h Address: FFFFh Data: FFFFh Write Mode & Mode Change Mode 3 Mode 1 (or Mode 2) 1. Last write data(1111h) stores in Buffer. 2. Dummy Write to `address FFFFh' transfers the last `data(1111h)' to the `cell(0000h)' and Buffer stores `address FFFFh' & `data (FFFFh)' 3. MRS is implemented to change the mode from `3' to `1(or2)' 4. Write is implemented during mode3 and the data(5555h) is written into cell(FFFFh). 5. MRS is implemented to change the mode from `3' to `1(or2)' 6. Output data is FFFFh instead of 5555h when the `address FFFFh' is input because, in Mode1 (or Mode2), UtRAM is supposed to access the buffer when the lastly input address when it was Mode1 is input. "Dummy write" is necessary to the same address with same data which are used right before the `Mode1(2) to Mode3 change' to make the the address & the data in the cell & Buffer to be the same. Product Planning & Product Planning & Application Eng. Team Application Eng. Team The Leader in Memory Technology