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JESD51

Catalog Datasheet MFG & Type PDF Document Tags

JESD51

Abstract: JEDEC51-12 Packages JESD51-4: Thermal Test Chip Guideline (Wire Bond Type Chip) JESD51-5: Extension of Thermal Test , thermal-characterization parameter, measured in units of °C/W. The JESD51-12, Guidelines for Reporting and Using Package , package, a fact that makes JB more useful for customer applications. Refer to the JEDEC standards JESD51-8 and JESD51-12 for more detailed specifications on this parameter. Designers can determine JB and JB , Semiconductor Device) JESD51-1: Integrated Circuit Thermal Measurement Method-Electrical Test Method (Single
Maxim Integrated Products
Original
AN4083 APP4083 JESD51 JEDEC51-12 JESD51-7 JESD-51 JEDEC51-1

JEDEC JESD51-8 BGA

Abstract: JESD51-8 is designed per JEDEC JESD51-3 and JEDEC JESD51-5. 3. Per JEDEC JESD51-6 with the board horizontal. 2s2p board is designed per JEDEC EIA/JESD51-5 and JEDEC JESD51-7. 4. Thermal resistance between the , convection environment. The 1s test board is designed per JEDEC JESD51-3 [6] and JEDEC JESD51-5 [7]. Another , two internal planes (2s2p). The 2s2p test board is designed per JEDEC JESD51-5 [7] and JEDEC JESD51-7 , surface of the board near the package. 2s2p board is designed per JEDEC JESD51-5 and JEDEC JESD51-7. 5
Freescale Semiconductor
Original
AN2388 JEDEC JESD51-8 BGA jesd51 8 800E-02 G38-87 JEDEC JESD51-8 BGA PACKAGE thermal resistance Freescale

JESD51-5

Abstract: JESD-51-5 board horizontal. Single layer board is designed per JEDEC JESD51-3 and JEDEC JESD51-5. 3. Per JEDEC JESD51-6 with the board horizontal. 2s2p board is designed per JEDEC EIA/JESD51-5 and JEDEC JESD51-7. 4 , . Junction-to-ambient thermal resistance (Theta-JA or RJA per JEDEC JESD51-2 [5]) is a one-dimensional value that , a natural convection environment. The 1s test board is designed per JEDEC JESD51-3 [6] and JEDEC JESD51-5 [7]. Another thermal resistance that is commonly reported is Theta-JMA or RJMA on a board with
Motorola
Original
JESD-51-5 outline of the heat slug for JEDEC MO-166 HSOP 30 36-Ld 44LD AN2388/D

JEP140

Abstract: JESD51-9 specs: - JESD51-5 add-on to JESD51-7: Most surface mount packages. - JESD51-9: Area array (e.g. BGA). , surface mount packages. - JESD51-9: Area array (e.g. BGA). - JESD51-10: Through-hole perimeter leaded , style). · Applicable JEDEC board specs: - JESD51-7: Most surface mount packages. - JESD51-9: Area array (e.g. BGA). - JESD51-10: Through-hole perimeter leaded (e.g. DIP, SIP). - JESD51-11 , PCB's. · Optional test in JESD51-2 and JESD51-6 JA standards. · For plastic packages, depends mainly
Intersil
Original
TB379 JEP140 pcb board 0.035mm PCB 1.2mm FR4 1oz cu JESD51-X JEP-140 jesd51 6 ISO9000

JESD51-9

Abstract: JEP140 specs: - JESD51-5 add-on to JESD51-7: Most surface mount packages. - JESD51-9: Area array (e.g. BGA). , surface mount packages. - JESD51-9: Area array (e.g. BGA). - JESD51-10: Through-hole perimeter leaded , style). · Applicable JEDEC board specs: - JESD51-7: Most surface mount packages. - JESD51-9: Area array (e.g. BGA). - JESD51-10: Through-hole perimeter leaded (e.g. DIP, SIP). - JESD51-11 , calculation of TJ rise above Tt for devices on application PCB's. · Optional test in JESD51-2 and JESD51-6
Intersil
Original
conductivity meter circuit Reliability Test Methods for Packaged Devices thermal resistance standards JC JB jt Theta JB

dap 010

Abstract: JESD51-3 ) JEDEC EIA/JESD51-3 Figure 1 4 PCB DAP TO-263 JA DAP JEDEC EIA/JESD51-5 EIA/JESD51-7 Figure 3 4 PCB DAP DAP JEDEC EIA/JESD51-5 EIA/JESD51-7 FIGURE 1 , : (TA) (PD) (TJ(MAX) (JA) JA 2 PCB (EIA/JESD51-3) Note 5: VADJ Note 6 , /W JA 67 /W DAP PCB 1 0.055 (0.22 × 0.25 ) JEDEC EIA/JESD51-3 PSOP-8 PSOP
National Semiconductor
Original
dap 010 dap11 100K adj dap 11 AN-1378 LP38511-ADJ DS300408-04-JP O-263 MRA08A

JESD51-5

Abstract: JESD-51-5 NOTES: Soldermast openings 1.Per JEDEC JESD51-2 at natural convection, still air condition. 2.2s2p thermal test board per JEDEC JESD51-5 and JESD51-7. 3.Per JEDEC JESD51-8, with the board temperature on the center trace near the center lead. 4.Single layer thermal test board per JEDEC JESD51-3 and JESD51-5. 5.Thermal resistance between the die junction and the exposed pad surface; cold plate , Direct Thermal Attachment According to JESD51-5 A AGND FS IN1 V+ V+ OUT1 OUT1 DNC PGND
Freescale Semiconductor
Original
MC33886 MC33886DHTAD 33886DH 20-TERMINAL 98ASH70702A

33186DH

Abstract: JESD51 Pattern for Direct Thermal Attachment According to JESD51-5 1.Per JEDEC JESD51-2 at natural convection, still air condition. 2.2s2p thermal test board per JEDEC JESD51-5 and JESD51-7. 3.Per JEDEC JESD51-8 , per JEDEC JESD51-3 and JESD51-5. 5.Thermal resistance between the die junction and the exposed pad
Freescale Semiconductor
Original
33186DH MC33186DHTAD MC33186 98ASH70273A

JESD51-7

Abstract: JESD51-1 the "JEDEC 1S" board. In addition to the above mentioned JEDEC specifications, JESD51-5 should be , will result in lower (better) thermal resistance values than a 1S or SEMI board. [3] EIA/JESD51-2 , provided. [2] EIA/JESD51-1 Integrated circuit thermal measurement method - electrical test method. [4] EIA/JESD51-6 Integrated circuit thermal test method environmental conditions - forced convection (moving air). [5] EIA/JESD51-3 Low effective thermal conductivity test board for leaded surface mount
Intersil
Original
G30-88 JESD-51-1

GR-1089-CORE

Abstract: I3124 /ITSM(t) 20 EIA/JESD51-2 ENVIRONMENT EIA/JESD51-3 PCB TA = 25 °C 15 10 9 8 7 6 5 4 3 , Applications Information and Figure 11 for current ratings at other temperatures. EIA/JESD51-2 environment and EIA/JESD51-3 PCB with standard footprint dimensions connected with 5 A rated printed wiring track , Junction to free air thermal resistance Test Conditions Min. EIA/JESD51-3 PCB, IT = ITSM(1000 , °C 113 °C /W 50 7: EIA/JESD51-2 environment and PCB has standard footprint dimensions
Bourns
Original
TISP4165H4BJ TISP4200H4BJ TISP4265H4BJ TISP4350H4BJ GR-1089-CORE I3124

TISP4070H3BJ

Abstract: TISP4095H3BJ at other temperatures. EIA/JESD51-2 environment and EIA/JESD51-3 PCB with standard footprint , TI4HAC 30 VGEN = 600 Vrms, 50/60 Hz RGEN = 1.4*VGEN/ITSM(t) EIA/JESD51-2 ENVIRONMENT EIA/JESD51-3 , MIN TEST CONDITIONS TYP MAX EIA/JESD51-3 PCB, IT = ITSM(1000), RJA 265 mm x 210 mm , ) Junction to free air thermal resistance °C/W 50 7: EIA/JESD51-2 environment and PCB has standard , 30 20 15 10 7 5 4 3 1 0·1 1000 ITSM(t) APPLIED FOR TIME t EIA/JESD51-2 ENVIRONMENT
Power Innovations
Original
TISP4070H3BJ TISP4095H3BJ TISP4125H3BJ TISP4200H3BJ TISP4240H3BJ TISP4400H3BJ

LITTELFUSE PTC

Abstract: GR-1089-CORE current ratings at other temperatures. EIA/JESD51-2 environment and EIA/JESD51-3 PCB with standard , VGEN = 600 Vrms, 50/60 Hz RGEN = 1.4*VGEN/ITSM(t) EIA/JESD51-2 ENVIRONMENT EIA/JESD51-3 PCB TA = 25 , TISP4360H3BJ IT(OV)M Figure 8. VDRM DERATING FACTOR 1.00 EIA/JESD51-2 ENVIRONMENT EIA/JESD51-3 PCB , PARAMETER TEST CONDITIONS MIN EIA/JESD51-3 PCB, IT = ITSM(1000), RJA Junction to free air , ) 265 mm x 210 mm populated line card, UNIT °C/W 50 6: EIA/JESD51-2 environment and PCB has
Power Innovations
Original
LITTELFUSE PTC K20/21
Abstract: . EIA/JESD51-2 environment and EIA/JESD51-3 PCB with standard footprint dimensions connected with 5 A , VGEN = 600 Vrms, 50/60 Hz RGEN = 1.4*VGEN/ITSM(t) EIA/JESD51-2 ENVIRONMENT EIA/JESD51-3 PCB TA = 25 °C , = VGEN/IT(OV)M EIA/JESD51-2 ENVIRONMENT EIA/JESD51-3 PCB TA = 25 °C TISP4360H3BJ IT(OV)M UL , Coff Off-state capacitance pF Thermal Characteristics Parameter Test Conditions EIA/JESD51-3 , resistance NOTE 6: EIA/JESD51-2 environment and PCB has standard footprint dimensions connected with 5 Bourns
Original
4360H3 TISP4360H3BJR-S TISP4360H3BJ-S

JESD-51-5

Abstract: JESD51-5 Soldermast openings NOTES: 1.Per JEDEC JESD51-2 at natural convection, still air condition. 2.2s2p thermal test board per JEDEC JESD51-5 and JESD51-7. 3.Per JEDEC JESD51-8, with the board temperature on the center trace near the center lead. 4.Single layer thermal test board per JEDEC JESD51-3 and JESD51-5. 5.Thermal resistance between the die junction and the exposed pad surface; cold plate , Thermal Attachment According to JESD51-5 A Tab AGND FS IN1 V+ V+ OUT1 OUT1 FB PGND PGND
Freescale Semiconductor
Original
MC33887 MC33887DHTAD 33887DH

JESD51

Abstract: JESD51-2 JEDEC JESD51-2 at natural convection, still air condition. 2. 2s2p thermal test board per JEDEC JESD51-7and JESD51-5. 3. Per JEDEC JESD51-8, with the board temperature on the center trace near the power outputs. 4. Single layer thermal test board per JEDEC JESD51-3 and JESD51-5. 5. Thermal resistance between , Figure 1. Thermal Land Pattern for Direct Thermal Attachment per JESD51-5 A VBAT GND 1 20
Freescale Semiconductor
Original
MC33486 MC33486A MC33486ADHTAD 33486ADH RJA11 RJA12

TISP4080H3BJ

Abstract: GR-1089-CORE 11 for current ratings at other temperatures. EIA/JESD51-2 environment and EIA/JESD51-3 PCB with , /60 Hz RGEN = 1.4*VGEN/ITSM(t) 20 EIA/JESD51-2 ENVIRONMENT EIA/JESD51-3 PCB TA = 25 °C 15 , ) APPLIED FOR TIME t EIA/JESD51-2 ENVIRONMENT EIA/JESD51-3 PCB TA = 25 °C 2 1.5 1 0·1 1000 t , /JESD51-3 PCB, IT = ITSM(1000), TA = 25 °C, (see Note 7) 265 mm x 210 mm populated line card, 4-layer PCB, IT = ITSM(1000), TA = 25 °C 113 °C/W 50 7: EIA/JESD51-2 environment and PCB has standard
Bourns
Original
TISP4115H3BJ TISP4220H3BJ TISP4350H3BJ TISP4070H3 TISP4080H3BJ UL1950 DO-214AA

JESD51-2

Abstract: JESD-51 Thermal Conductivity Test Board : JESD51-3/7 Area Array Thermal Test Board : JESD51-9 The Leader in , Resistance, ja - Natural Convection(using test chamber) : JEDEC Standard JESD51-2 - Forced Convection(using wind tunnel) : JEDEC Standard JESD51-6 Junction-to-Case Thermal Resistance, jc - Cold Plate Method
Samsung Electronics
Original
thermal resistance SAMSUNG TSOP Thermal Resistance Calculation TO JESD51-3/7

GR-1089-CORE

Abstract: TISP4070M3BJ at other temperatures. EIA/JESD51-2 environment and EIA/JESD51-3 PCB with standard footprint , , 50/60 Hz RGEN = 1.4*VGEN/ITSM(t) EIA/JESD51-2 ENVIRONMENT EIA/JESD51-3 PCB TA = 25 °C 20 15 , 0·1 ITSM(t) APPLIED FOR TIME t EIA/JESD51-2 ENVIRONMENT EIA/JESD51-3 PCB TA = 25 °C 1 10 , MIN TEST CONDITIONS TYP MAX EIA/JESD51-3 PCB, IT = ITSM(1000), RJA 265 mm x 210 mm , ) Junction to free air thermal resistance °C/W 52 7: EIA/JESD51-2 environment and PCB has standard
Power Innovations
Original
TISP4070M3BJ TISP4095M3BJ TISP4125M3BJ TISP4200M3BJ TISP4240M3BJ TISP4400M3BJ
Abstract: at other temperatures. EIA/JESD51-2 environment and EIA/JESD51-3 PCB with standard footprint , 5 4 3 2 1.5 0·1 1 10 100 1000 RGEN = 1.4*VGEN/ITSM(t) EIA/JESD51-2 ENVIRONMENT EIA/JESD51-3 PCB TA = , CONDITIONS EIA/JESD51-3 PCB, IT = ITSM(1000), RJA Junction to free air thermal resistance TA = 25 °C, (see , MAX 113 °C/W UNIT 7: EIA/JESD51-2 environment and PCB has standard footprint dimensions connected , 100 70 50 40 30 20 15 10 7 5 4 3 2 1.5 1 0·1 1 TI4HAE ITSM(t) APPLIED FOR TIME t EIA/JESD51-2 Power Innovations
Original

JESD-51-5

Abstract: JESD51-5 ), (3) 9.0 RJA (1), (4) 69 RJC (5) 1.0 2.0 Notes: 1. Per JEDEC JESD51-2 at natural convection, still air condition. 2. 2s2p thermal test board per JEDEC JESD51-5 and JESD51-7. 3. Per JEDEC JESD51-8, with the board temperature on the center trace near the center lead. 4. Single layer thermal test board per JEDEC JESD51-3 and JESD51-5. 5. Thermal resistance between the die junction and the , Thermal Attachment According to JESD51-5 A AGND SF IN1 VBAT VBAT OUT1 OUT1 COD PGND PGND
Freescale Semiconductor
Original
MC33186DH

SAC1205

Abstract: IPC-A-600G : 1. 2. Single Signal Layer - 1s (designed per JEDEC EIA / JESD51-3 [13]. Two Signal Layers, Two Internal Planes - 2s2p (designed per JEDEC EIA / JESD51-5 [14] and JEDEC EIA / JESD51-7 [15] Thermal , /JESD51-2 [16]) is a one-dimensional value that measures the conduction of heat from the junction , designed per JEDEC EIA/JESD51-3 and JEDEC EIA/JESD51-5. R JA helps estimate the thermal performance of the , internal planes (2s2p). The 2s2p test board is designed per JEDEC EIA/JESD51-5 and JEDEC EIA/JESD51-7. R
Freescale Semiconductor
Original
AN3846 SAC1205 IPC-A-600G IPC-6012 WLCSP stencil design JESD-B111
Abstract: (Theta-JA or RJA per JEDEC JESD51-5 [1]) is a one-dimensional value that measures the conduction of heat , internal planes (2s2p). The 2s2p test board is designed per JEDEC JESD51-5 [1] and JEDEC JESD51-7 [2]. , JEDEC EIA/JESD51-8 [3]) measures the horizontal spreading of heat between the junction and the board , resistance. 2. Per JEDEC JESD51-6 with the board horizontal. 2s2p board is designed per JEDEC EIA/JESD51-5 and JEDEC JESD51-7. 3. Thermal resistance between the die and the printed circuit board per JEDEC Freescale Semiconductor
Original
AN2409

MTTF analysis data

Abstract: JEDEC JESD51-8 BGA resistance (Theta-JA or RJA per JEDEC JESD51-5 [1]) is a one-dimensional value that measures the conduction , internal planes (2s2p). The 2s2p test board is designed per JEDEC JESD51-5 [1] and JEDEC JESD51-7 [2]. , EIA/JESD51-8 [3]) measures the horizontal spreading of heat between the junction and the board. The , resistance. 2. Per JEDEC JESD51-6 with the board horizontal. 2s2p board is designed per JEDEC EIA/JESD51-5 and JEDEC JESD51-7. 3. Thermal resistance between the die and the printed circuit board per JEDEC
Motorola
Original
MTTF analysis data JESD51-51 98ARL10519D QFN PACKAGE thermal resistance SOICW-32 1147 x motorola AN2409/D

4250M3

Abstract: Figure 12 for current ratings at other temperatures. 5. EIA/JESD51-2 environment and EIA/JESD51-3 PCB , Parameter Test Conditions EIA/JESD51-3 PCB, IT = ITSM(1000), TA = 25 °C, (see Note 7) 265 mm x 210 mm , Junction to free air thermal resistance NOTE 7: EIA/JESD51-2 environment and PCB has standard , 1.5 0·1 1 10 t - Current Duration - s 100 1000 RGEN = 1.4*VGEN /ITSM(t) EIA/JESD51-2 ENVIRONMENT EIA/JESD51-3 PCB TA = 25 °C TI4MAC THERMAL IMPEDANCE vs POWER DURATION 150 Z A(t) - Transie nt Thermal
Bourns
Original
4250M3 TISP4115M3BJ TISP4220M3BJ TISP4350M3BJ TISP4070M3 TISP4080M3 TISP4095M3

P3100EA

Abstract: 4180M3 . EIA/JESD51-2 environment and EIA/JESD51-3 PCB with standard footprint dimensions connected with 5 A , air thermal resistance Test Conditions Min EIA/JESD51-3 PCB, IT = ITSM(1000), TA = 25 °C , /W 57 7: EIA/JESD51-2 environment and PCB has standard footprint dimensions connected with 5 A , PEAK ON-STATE CURRENT vs CURRENT DURATION RGEN = 1.4*VGEN/ITSM(t) 20 EIA/JESD51-2 ENVIRONMENT EIA/JESD51-3 PCB TA = 25 °C 15 10 9 8 7 6 5 4 3 2 1.5 0·1 1 10 100
Bourns
Original
TISP4070M3LM TISP4115M3LM TISP4125M3LM TISP4220M3LM TISP4240M3LM TISP4400M3LM P3100EA 4180M3

GR-1089-CORE

Abstract: TISP4070M3BJ conditions. See Applications Information and 11 for current ratings at other temperatures. EIA/JESD51-2 environment and EIA/JESD51-3 PCB with standard footprint dimensions connected with 5 A rated printed wiring , MIN TEST CONDITIONS TYP MAX EIA/JESD51-3 PCB, IT = ITSM(1000), RJA 265 mm x 210 mm , ) Junction to free air thermal resistance °C/W 52 7: EIA/JESD51-2 environment and PCB has standard , /JESD51-2 ENVIRONMENT EIA/JESD51-3 PCB TA = 25 °C 20 15 10 9 8 7 6 5 4 3 2 1.5 0·1 1
Texas Instruments
Original
E132482

JESD51-8

Abstract: JESD51-2 JESD51-2 JESD51-8 GUIDELINES FOR SOLDERING: Motorola's broad array of Small Outline IC's (SOIC , 100°C/W RJA 10°C/W - 40°C/W RJL 1°C/W - 2°C/W RJC* *SOICW-Exposed Pad Test Condition JESD51-2 JESD51-8 JESD51-8 GUIDELINES FOR SOLDERING: Motorola's broad array of Small Outline IC's (SOIC , Test Condition JESD51-2 JESD51-8 JESD51-5 GUIDELINES FOR SOLDERING: The Motorola portfolio of , Test Condition JESD51-2 JESD51-8 JESD51-5 Power Dissipation: 2.0 W to 5.0 W For More
Motorola
Original
JEDEC-STD-020 surface mount package dimensions qfn 44 PACKAGE footprint 9mm FREESCALE PACKING JEDEC-STD020 tqfp 44 PACKAGE footprint BR1568/D

4350M3

Abstract: surge may be repeated after the TISP4xxxM3BJ returns to its initial conditions. 5. EIA/JESD51-2 environment and EIA/JESD51-3 PCB with standard footprint dimensions connected with 5 A rated printed wiring , EIA/JESD51-3 PCB, IT = ITSM(1000), TA = 25 °C, (see Note 7) 265 mm x 210 mm populated line card, 4 , resistance NOTE 7: EIA/JESD51-2 environment and PCB has standard footprint dimensions connected with 5 , 600 Vrms, 50/60 Hz 20 15 10 9 8 7 6 5 4 3 2 1.5 0·1 1 10 100 1000 RGEN = 1.4*VGEN/ITSM(t) EIA/JESD51
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4350M3 DO-214AA/SMB
Abstract: 12 for current ratings at other temperatures. EIA/JESD51-2 environment and EIA/JESD51-3 PCB with , tested with VD = -98 V. thermal characteristics PARAMETER TEST CONDITIONS EIA/JESD51-3 PCB, IT = ITSM , : EIA/JESD51-2 environment and PCB has standard footprint dimensions connected with 5 A rated printed , /JESD51-2 ENVIRONMENT EIA/JESD51-3 PCB TA = 25 °C TI4MAC THERMAL IMPEDANCE vs POWER DURATION 150 ZJA , ) APPLIED FOR TIME t EIA/JESD51-2 ENVIRONMENT EIA/JESD51-3 PCB TA = 25 °C 1 10 t - Power Duration - s 100 Power Innovations
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