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TS3DDR4000ZBAR Texas Instruments 12-Bits 1:2 High Speed DDR2/DDR3/DDR4 Switch/Multiplexer 48-NFBGA -40 to 85 visit Texas Instruments Buy
CAB4AZNRR Texas Instruments DDR4RCD01 JEDEC compliant DDR4 Register for RDIMM and LRDIMM operation up to DDR4-2400 253-NFBGA 0 to 0 visit Texas Instruments Buy
SN74SSQE32882ZALR Texas Instruments JEDEC SSTE32882 Compliant 28-Bit to 56-Bit Registered Buffer with Address-Parity Test 176-NFBGA 0 to 85 visit Texas Instruments
HPA00441ZALR Texas Instruments JEDEC SSTE32882 Compliant 28-Bit to 56-Bit Registered Buffer with Address-Parity Test 176-NFBGA 0 to 85 visit Texas Instruments
SN74SSQEA32882ZALR Texas Instruments JEDEC SSTE32882 Compliant 28-Bit to 56-Bit Registered Buffer with Address-Parity Test 176-NFBGA 0 to 85 visit Texas Instruments Buy
SN74SSQEB32882ZALR Texas Instruments JEDEC SSTE32882 Compliant 28-Bit to 56-Bit Registered Buffer with Address-Parity Test 176-NFBGA 0 to 85 visit Texas Instruments Buy

JEDEC DDR4 pcb layout

Catalog Datasheet MFG & Type PDF Document Tags

SC2597SETRC

Abstract: ® The SC2597 is designed to meet the latest JEDEC specification for low power DDR3 and DDR4, while also , effecting to the loop stability is parasitic inductance in PCB layout and output capacitor ESL. The gain , Model PCB Layout Input Capacitor The primary purpose of input capacitance is to provide the charge , ): 0.5V to 1.8V Bias Voltage (VDD): 2.35V to 3.6V Up to 3A sink or source from VTT for DDR through DDR4 , with industry leading specifications make SC2597 an attractive solution for DDR through DDR4
Semtech
Original
SC2597SETRC

DDR4 pcb layout guidelines

Abstract: high-performance, DDR2, DDR3, and low power DDR4 JEDEC VTT requirements. Advanced circuit techniques and high , is compliant with DDR2/3/QDR and low power DDR4 JEDEC memory termination requirements. The EV1320QI , Required JEDEC Compliant DDR2/3/QDR and Low Power DDR 4 Solution Enable Pin with Output Discharge to , '¢ VTT Bus Termination for DDR2, DDR3, Low Power DDR4, and QDR Memories Efficiency vs. Output Current , is not to be mechanically or electrically connected to the PCB. Refer to Figure 10 for details
Altera
Original
DDR4 pcb layout guidelines

DDR4 pcb layout guidelines

Abstract: DDR4 jedec present and future high-performance, DDR2, DDR3, and low power DDR4 JEDEC VTT requirements. Advanced , ±40mV accuracy and is compliant with DDR2/3/QDR and low power DDR4 JEDEC memory termination requirements , External Inductor Required JEDEC Compliant DDR2/3/QDR and Low Power DDR 4 Solution Enable Pin with Output , Termination for DDR2, DDR3, Low Power DDR4, and QDR Memories Efficiency vs. Output Current 98 96 94 , connected to the PCB. Refer to Figure 10 for details. NOTE B: White `dot' on top left is pin 1 indicator on
Enpirion
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DDR4 jedec EV1320 JEDEC DDR4 pcb layout EV1320QI-E DDR4 "application note"

QSFP28 I2C

Abstract: deliver over 500 MHz core fabric performance and 2666 Mbps DDR4 external memory interface performance , @ 667 MHz/1333 Mbps DDR4 SDRAM @ 1333 MHz/2666 Mbps DDR3 SDRAM @ 1067 MHz/2133 Mbps Hybrid Memory , chip-to-chip rates up to 28 Gbps and backplane rates up to 17.4 Gbps â'¢ Improved Memory Bandwidth with DDR4 Support: Arria 10 devices support DDR4 memory up to 1333 MHz/ 2666 Mbps and feature support for the , , combining ARM HPS with support for high speed memory devices such as DDR4, and Hybrid Memory Cube (HMC) as
Altera
Original
QSFP28 I2C AIB-01023

DDR4 pcb layout guidelines

Abstract: be soldered to PCB NOTE: There are specific keep-out areas underneath the EV1340 to consider w hen laying out a PCB for this device. Please see Figures 8, 10, and 11 for m ore layout details. Pin , on a Chip (PowerSoC) DC to DC converter in a 54 pin QFN that is optimized for DDR2, DDR3, DDR4 and , converter solution enhances productivity by offering greatly simplified board design, layout and , '¢ Applications â'¢ Bus Termination: DDR2, DDR3, DDR4 & QDRâ"¢ Memory General Low VIN Applications â
Altera
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EV1340QI

DDR3 pcb layout motherboard

Abstract: DDR3 pcb layout (PCB) layout. The TPS51200 is housed in a thermally-enhanced PowerPADTM package that has an exposed , (REFOUT) Built-in Soft Start, UVLO and OCL Thermal Shutdown Meets DDR, DDR2 JEDEC Specifications; Supports DDR3 and Low-Power DDR3/DDR4 VTT Applications SON-10 PowerPADTM Package · · Memory Termination Regulator for DDR, DDR2, DDR3, and Low Power DDR3/DDR4 Notebook/Desktop/Server Telecom/Datacom , function and all power requirements for DDR, DDR2, DDR3, and Low Power DDR3/DDR4 VTT bus termination. In
Texas Instruments
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TPS51200-Q1 DDR3 pcb layout motherboard DDR3 pcb layout DDR3 layout TI DDR4 DIMM SPD JEDEC DDR3 pcb layout guide ddr3 ram SLUS984

SLUS984A

Abstract: JEDEC Specifications; Supports DDR3 and Low-Power DDR3/DDR4 VTT Applications SON-10 PowerPADTM Package APPLICATIONS · · · Memory Termination Regulator for DDR, DDR2, DDR3, and Low Power DDR3/DDR4 Notebook/Desktop , printed circuit board (PCB) layout. The TPS51200 is housed in a thermally-enhanced PowerPADTM package that , supports a remote sensing function and all power requirements for DDR, DDR2, DDR3, and Low Power DDR3/DDR4 , tolerance requirement on VTT. Based on JEDEC VTT specifications for DDR and DDR2 (JEDEC standard: DDR JESD8
Texas Instruments
Original
SLUS984A

DDR4 pcb layout guidelines

Abstract: DDR3 pcb layout motherboard thermal performance of an LDO is greatly depends on the printed circuit board (PCB) layout. The TPS51200 , Start, UVLO and OCL · Thermal Shutdown · Meets DDR, DDR2 JEDEC Specifications; Supports DDR3 and Low-Power DDR3/DDR4 VTT Applications · SON-10 PowerPADTMPackage · 1 2 · · Memory Termination Regulator for DDR, DDR2, DDR3, and Low Power DDR3/DDR4 Notebook/Desktop/Server Telecom/Datacom , function and all power requirements for DDR, DDR2, DDR3, and Low Power DDR3/DDR4 VTT bus termination. In
Texas Instruments
Original
ddr3 pcb design guide TPS51200DRCT lpddr3 TPS51100 TPS51200DRCR SON10 SLUS812
Abstract: depends on the printed circuit board (PCB) layout. The TPS51200 is housed in a thermally-enhanced , Reference (REFOUT) â'¢ Built-in Soft Start, UVLO and OCL â'¢ Thermal Shutdown â'¢ Meets DDR, DDR2 JEDEC Specifications; Supports DDR3 and Low-Power DDR3/DDR4 VTT Applications â'¢ SON-10 PowerPADâ"¢Package â'¢ 1 2 â'¢ â'¢ Memory Termination Regulator for DDR, DDR2, DDR3, and Low Power DDR3/DDR4 , /DDR4 VTT bus termination. In addition, the TPS51200 provides an open-drain PGOOD signal to monitor Texas Instruments
Original
Abstract: depends on the printed circuit board (PCB) layout. The TPS51200 is housed in a thermally-enhanced , Reference (REFOUT) â'¢ Built-in Soft Start, UVLO and OCL â'¢ Thermal Shutdown â'¢ Meets DDR, DDR2 JEDEC Specifications; Supports DDR3 and Low-Power DDR3/DDR4 VTT Applications â'¢ SON-10 PowerPADâ"¢Package â'¢ 1 2 â'¢ â'¢ Memory Termination Regulator for DDR, DDR2, DDR3, and Low Power DDR3/DDR4 , /DDR4 VTT bus termination. In addition, the TPS51200 provides an open-drain PGOOD signal to monitor Texas Instruments
Original
Abstract: JEDEC Specifications; Supports DDR3 and Low-Power DDR3/DDR4 VTT Applications SON-10 PowerPADTM Package APPLICATIONS · · · Memory Termination Regulator for DDR, DDR2, DDR3, and Low Power DDR3/DDR4 Notebook/Desktop , printed circuit board (PCB) layout. The TPS51200 is housed in a thermally-enhanced PowerPADTM package that , supports a remote sensing function and all power requirements for DDR, DDR2, DDR3, and Low Power DDR3/DDR4 , tolerance requirement on VTT. Based on JEDEC VTT specifications for DDR and DDR2 (JEDEC standard: DDR JESD8 Texas Instruments
Original
Abstract: Shutdown Meets DDR, DDR2 JEDEC Specifications; Supports DDR3 and Low-Power DDR3/DDR4 VTT Applications , (PCB) layout. The TPS51200 is housed in a thermally-enhanced PowerPADâ"¢ package that has an exposed , Power DDR3/DDR4 Notebook/Desktop/Server Telecom/Datacom, GSM Base Station, LCD-TV/PDP-TV, Copier , , DDR3, and Low Power DDR3/DDR4 VTT bus termination. In addition, the TPS51200 provides an open-drain , the tolerance requirement on VTT. Based on JEDEC VTT specifications for DDR and DDR2 (JEDEC standard Texas Instruments
Original

DDR4 pcb layout guidelines

Abstract: TPS51200-EVM Shutdown · Meets DDR, DDR2 JEDEC Specifications; Supports DDR3 and Low-Power DDR3/DDR4 VTT Applications · , performance of an LDO is greatly depends on the printed circuit board (PCB) layout. The TPS51200 is housed in , FEATURES APPLICATIONS · · · Memory Termination Regulator for DDR, DDR2, DDR3, and Low Power DDR3/DDR4 , for DDR, DDR2, DDR3, and Low Power DDR3/DDR4 VTT bus termination. In addition, the TPS51200 provides , requirement on VTT. Based on JEDEC VTT specifications for DDR and DDR2 (JEDEC standard: DDR JESD8-9B May 2002
Texas Instruments
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TPS51200-EVM DDR4 spd JESD8-15a UDG-08034 UDG-08023 UDG-08032

DDR3 pcb layout guide

Abstract: DDR3 pcb layout thermal performance of an LDO is greatly depends on the printed circuit board (PCB) layout. The TPS51200 , Start, UVLO and OCL · Thermal Shutdown · Meets DDR, DDR2 JEDEC Specifications; Supports DDR3 and Low-Power DDR3/DDR4 VTT Applications · SON-10 PowerPADTMPackage · 1 2 · · Memory Termination Regulator for DDR, DDR2, DDR3, and Low Power DDR3/DDR4 Notebook/Desktop/Server Telecom/Datacom , function and all power requirements for DDR, DDR2, DDR3, and Low Power DDR3/DDR4 VTT bus termination. In
Texas Instruments
Original
Abstract: Shutdown Meets DDR, DDR2 JEDEC Specifications; Supports DDR3 and Low-Power DDR3/DDR4 VTT Applications , performance of an LDO depends on the printed circuit board (PCB) layout. The TPS51200 is housed in a , Power DDR3/DDR4 Notebook/Desktop/Server Telecom/Datacom, GSM Base Station, LCDTV/PDP-TV, Copier , , DDR3, and Low Power DDR3/DDR4 VTT bus termination. In addition, the TPS51200 provides an open-drain , imperative to understand the tolerance requirement on VTT. Based on JEDEC VTT specifications for DDR and Texas Instruments
Original
ISO/TS16949

DDR4 pcb layout guidelines

Abstract: TPS51200-Q1 JEDEC Specifications; Supports DDR3 and Low-Power DDR3/DDR4 VTT Applications SON-10 PowerPADTM Package APPLICATIONS · · · Memory Termination Regulator for DDR, DDR2, DDR3, and Low Power DDR3/DDR4 Notebook/Desktop , printed circuit board (PCB) layout. The TPS51200 is housed in a thermally-enhanced PowerPADTM package that , supports a remote sensing function and all power requirements for DDR, DDR2, DDR3, and Low Power DDR3/DDR4 , tolerance requirement on VTT. Based on JEDEC VTT specifications for DDR and DDR2 (JEDEC standard: DDR JESD8
Texas Instruments
Original
DDR3 layout guidelines

DDR4 pcb layout guidelines

Abstract: DDR3 pcb layout guide thermal performance of an LDO is greatly depends on the printed circuit board (PCB) layout. The TPS51200 , Start, UVLO and OCL · Thermal Shutdown · Meets DDR, DDR2 JEDEC Specifications; Supports DDR3 and Low-Power DDR3/DDR4 VTT Applications · SON-10 PowerPADTMPackage · 1 2 · · Memory Termination Regulator for DDR, DDR2, DDR3, and Low Power DDR3/DDR4 Notebook/Desktop/Server Telecom/Datacom , function and all power requirements for DDR, DDR2, DDR3, and Low Power DDR3/DDR4 VTT bus termination. In
Texas Instruments
Original
RFID Tracking Pad 770 DDR3 layout DDR3 "application note" DDR4 GRM21BR60J475KA11L

DDR3 layout

Abstract: DDR4 jedec printed circuit board (PCB) layout. The TPS51200 is housed in a thermally-enhanced PowerPADTM package that , Reference (REFOUT) Built-in Soft Start, UVLO and OCL Thermal Shutdown Meets DDR, DDR2 JEDEC Specifications; Supports DDR3 and Low-Power DDR3/DDR4 VTT Applications SON-10 PowerPADTM Package APPLICATIONS · · · Memory Termination Regulator for DDR, DDR2, DDR3, and Low Power DDR3/DDR4 Notebook/Desktop/Server Telecom , supports a remote sensing function and all power requirements for DDR, DDR2, DDR3, and Low Power DDR3/DDR4
Texas Instruments
Original
Abstract: depends on the printed circuit board (PCB) layout. The TPS51200 is housed in a thermally-enhanced , Reference (REFOUT) â'¢ Built-in Soft Start, UVLO and OCL â'¢ Thermal Shutdown â'¢ Meets DDR, DDR2 JEDEC Specifications; Supports DDR3 and Low-Power DDR3/DDR4 VTT Applications â'¢ SON-10 PowerPADâ"¢Package â'¢ 1 2 â'¢ â'¢ Memory Termination Regulator for DDR, DDR2, DDR3, and Low Power DDR3/DDR4 , /DDR4 VTT bus termination. In addition, the TPS51200 provides an open-drain PGOOD signal to monitor Texas Instruments
Original

DDR3 pcb layout guide

Abstract: voltage regulator mar 920 thermal performance of an LDO is greatly depends on the printed circuit board (PCB) layout. The TPS51200 , Start, UVLO and OCL · Thermal Shutdown · Meets DDR, DDR2 JEDEC Specifications; Supports DDR3 and Low-Power DDR3/DDR4 VTT Applications · SON-10 PowerPADTMPackage · 1 2 · · Memory Termination Regulator for DDR, DDR2, DDR3, and Low Power DDR3/DDR4 Notebook/Desktop/Server Telecom/Datacom , function and all power requirements for DDR, DDR2, DDR3, and Low Power DDR3/DDR4 VTT bus termination. In
Texas Instruments
Original
voltage regulator mar 920
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