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J101 Datasheet

Part Manufacturer Description PDF Type
J101 N/A Basic Transistor and Cross Reference Specification Scan
J101 N/A Shortform Transistor PDF Datasheet Scan
J101 N/A Shortform Datasheet & Cross References Data Scan
J101 N/A Semiconductor Master Cross Reference Guide Scan
J10103L Sumida ADSL Transformer< SMD Type: CEP Series> Original
J10104L Sumida ADSL Transformer< SMD Type: CEP Series> Original
J10107L Sumida ADSL Transformer< SMD Type: CEP Series> Original
J1011F01P Pulse Engineering PULSEJACKTM 1x1 Tab-UP RJ45 Original
J1011F01PNL Pulse Engineering CONN PULSEJACK 1PORT 10/100B-TX Original
J1011F21P Pulse Engineering PULSEJACKTM 1x1 Tab-UP RJ45 Original
J1011F21PNL Pulse Electronics Modular Connectors - Jacks With Magnetics, Connectors, Interconnects, CONN MAGJACK 1PORT 100 BASE-TX Original
J1012F01C Pulse Engineering Modular Connectors - Jacks With Magnetics, Connectors, Interconnects, CONN MAGJACK 1PORT 100 BASE-TX Original
J1012F01CNL Pulse Electronics Modular Connectors - Jacks With Magnetics, Connectors, Interconnects, CONN MAGJACK 1PORT 100 BASE-TX Original
J1012F21C Pulse Engineering Modular Connectors - Jacks With Magnetics, Connectors, Interconnects, CONN MAGJACK 1PORT 100 BASE-TX Original
J1012F21C Pulse Engineering CONN PULSEJACK 1PORT 10/100B-TX Original
J1012F21CNL Pulse Electronics Modular Connectors - Jacks With Magnetics, Connectors, Interconnects, CONN MAGJACK 1PORT 100 BASE-TX Original
J1012F21K Pulse Engineering Modular Connectors - Jacks With Magnetics, Connectors, Interconnects, CONN MAGJACK 1PORT 100 BASE-TX Original
J1012F21K Pulse Engineering Connector: Telephone/ Telecom Connector: F: 8: 2.54: RATHRU: 12: 1 Original
J1012F21KNL Pulse Electronics Modular Connectors - Jacks With Magnetics, Connectors, Interconnects, CONN MAGJACK 1PORT 100 BASE-TX Original
J1012F21L Pulse Engineering Modular Connectors - Jacks With Magnetics, Connectors, Interconnects, CONN MAGJACK 1PORT 100 BASE-TX Original
Showing first 20 results.

J101

Catalog Datasheet MFG & Type PDF Document Tags

TP-107-02

Abstract: KDS 16.000MHz Valid" Indicator. 13 RESET Connects to RESET of MC1320X and Pin 32 of J101. Allows the MCU to reset the MC1320X. 15 PTD5/CESI Connects to ATTN of MC1320X and Pin 34 of J101. , Daughter Card Description As shown in Figure 5-1 and Figure 8-2, connector J101 is the main interface to , , previous versions of the MC1320x Daughter Card may not have R104 inserted. NOTE J101 Pin 1 of the , interconnects for both the GB60 and M52235 Development boards. Table 5-1 lists the pin connections for J101 and
Freescale Semiconductor
Original
HCS08 TP-107-02 KDS 16.000MHz TP-107-02-5-T QG60 J102 AN3248 MC1320 RFD-A00 M68EVB908GB60

J101

Abstract: -27 EXT-SDOUT4 Sub J101-11 SYNC5 Sub J101-15 BCLK5 Sub J101-17 SDIN5 Sub J101-J19 SDOUT5 Clocks 1fs=8kHz , Sub J101-7 BCLK4 J2-25 EXT-SDIN4 J2-27 EXT-SDOUT4 Sub J101-11 SYNC5 Sub J101-15 BCLK5 Sub J101-17 , SYNC4 Sub J101-7 BCLK4 J2-25 EXT-SDIN4 J2-27 EXT-SDOUT4 Sub J101-11 SYNC5 Sub J101-15 BCLK5 Sub , SDOUT3 Sub J101-5 SYNC4 Sub J101-7 BCLK4 J2-25 EXT-SDIN4 J2-27 EXT-SDOUT4 Sub J101-11 SYNC5 Sub J101-15 BCLK5 Sub J101-17 SDIN5 Sub J101-J19 SDOUT5 Clocks 1fs=8kHz 64fs=512kHz I2S, 16bit data
Asahi Kasei Microdevices
Original
AKD7719B-A AK7719B AKD7719B-A-MAIN AKD7719B-A-SUB KM113200 AK7719B-CSP

Application Notes

Abstract: TFT LCD AVR (J101) connections. J101 pin LCD resistive touch signals J101-1 - J101-2 - J101-3 - J101-4 - J101-5 TFT_XL (X-direction, Left side) J101-6 TFT_XR (X-direction, Right side) J101-7 TFT_YD (Y-direction, Bottom [lower] side J101-8 TFT_YU (Y-direction, Upper side) J101-9 GND J101-10 - 5 8297A-AVR-04/10 4.3 The SPI/TE/Reset/backlight , . 4.2 The resistive touch pin-header (J101) This connector connects the resistive touch interface to
Atmel
Original
AVR1909 HX8347-A Application Notes TFT LCD AVR et024006dhu hx8347 lcd with led backlight 40 pin connector pinout edt lcd ET024006DHU AVR1913 AVR1921 AT90USB1287
Abstract: J101-General IO[36:39] D12 LED array connected to J100-General IO[20:23] D13 LED array connected to J101-General IO[40:43] D14 LED array connected to J101-General IO[44:47] 7 ORCA ORT/ORSO42G5 , GEN_FPGA_PIN36 PT15C C9 J101 1 2 3 GEN_FPGA_PIN37 PT16D A11 J101 4 5 6 GEN_FPGA_PIN38 PT15D D9 J101 7 8 9 GEN_FPGA_PIN39 PT19C B13 J101 10 11 12 GEN_FPGA_PIN40 PT20C B14 J101 13 14 15 8 ORCA ORT/ORSO42G5 High-Speed SERDES Board Userâ Lattice Semiconductor
Original
VDD33 VDD25 VDD18 VDD15 PAC-PWR1208

KDS 16.000MHz

Abstract: TP-107-02 Pin 32 of J101. Allows the MCU to reset the MC1320X. 15 PTD5/CESI Connects to ATTN of MC1320X and Pin 34 of J101. Allows the MCU to wake up the MC1320X from Doze or Hibernate. 17 , Description 5 Daughter Card Description As shown in Figure 5-1 and Figure 8-1, connector J101 is the , this release, previous versions of the MC1320x Daughter Card may not have R104 inserted. NOTE J101 , connections for J101 and Table 5-2 lists the pin connections for J102. Table 5-1. J101 Pin Connections Pin
Freescale Semiconductor
Original
MM3Z3V3T1G ZD00882 Yageo antenna GB60 R104 LDB212G4005

a8449

Abstract: a8451 processor. Correct routing of s_idsel for Slot J101. Factory default. To operate a controller on the , R100 L1 R93 J101 C84 C75 C55 C20 C7 C5 PCI Option Card Slot (PCI Device 4 , Connectors J1, J2, J101, and J102 are the local PCI option slots. The top slot (J101) is also capable of , switches can be found in Section 3. Figure 1-2. Switches R100 R93 J101 E8 J23 R99 , and enables operation of LED1. When installed, s_ad is IDSEL when J101 is a PCI Option slot
Intel
Original
a8449 a8451 C82 diode SCBE4 pci non-transparent bridge A8450 DEB55401

monograph 175

Abstract: J type thermocouple . Thermocouple Data Connection Information and Lead Color ININ+ RTDRTD+ (J101 (J101 (J101 (J101 Pin 1) Pin 2 , Information and Lead Color Sensor Type IN(J101 Pin 1) White IN+ (J101 Pin 2) Red w/jumper to J101 Pin 4 Red Red RTD(J101 Pin 3) N/C RTD+ (J101 Pin 4) Jumper to J101 Pin 2 U.S. ANSI 96.1 Standard Color Code Wire
Simpson Electric
Original
monograph 175 J type thermocouple rtd pt100 code example rtd pt100 4-20ma k type thermocouple 0 to 1000 degree 9-32VDC THJ105 THJ1015 THK105 THK1015 THJ035

Stanag-3909

Abstract: A d v a n c e d R e l e a s e FEATURES MODEL NO. 100D9109 500 - 2000 MHz Amplitude / Phase Tracking 0.7 dB Insertion Loss 80 dB Isolation MFD D38999/25NB35PN DC, CONNECTOR Combiner 6.50 CONNECTOR, TNC FEMALE 10 PLACES J101 J102 J102 50 â"¦ J103 50 â , J101 COLOR TILES 4 PLACES NAMEPLATE .72 3.750 2 PLS J110 28VDC J111/12 + - .245 , Ports J101 to J105 J106 to J110 OHMS nSec nSec µSec dBm dBm dBm dBm dBm LBS °C 50
-
Original
Stanag-3909 J111/5 J111/2 RS-422 J111/3 J111/13 J111/8

Unelco J101

Abstract: VK200-4B , Ceramic C5 - 1.0uF, 15 WV Tantalum C6 - 250pF, Unelco J101 C7- 25pF, Unelco J101 C9 - Arco 262 or , , Unelco C4 - 0.1uF, Ceramic C5 - 1.0uF, 15 WV Tantalum C6 - 250pF, Unelco J101 C7- 25pF, Unelco J101
Microsemi
Original
VK200-4B Unelco J101 50v L4 vrf150 vk200 VRF150 150MH

"mini-jack Connector"

Abstract: 2.1 to 5.1 channel home theater kit ) . 7 Loudspeaker Connectors (J101 . J106 , . J101 . . . J106 Pin Numbers , . 8 J101 . . . J106 Pin Description , Figure 1-2. J101 J102 J103 J104 J105 J106 PSU INTERFACE (J901) 2 CHANNEL POWER , Connectors (J101 . J106) Table 2-2. J901 Pin Description PIN NO. 1 PVDD 2 - 3 GND
Texas Instruments
Original
TAS5086-5142V6EVM TAS5086 TAS5142 2.1 to 5.1 channel home theater kit 5.1channel amplifier SLEA056 SLEU072

100D9109

Abstract: Stanag-3909 A d v a n c e d R e l e a s e FEATURES MODEL NO. 100D9109 500 - 2000 MHz Amplitude / Phase Tracking 0.7 dB Insertion Loss 80 dB Isolation MFD D38999/25NB35PN DC, CONNECTOR Combiner 6.50 CONNECTOR, TNC FEMALE 10 PLACES J101 J102 J103 J102 50 J103 50 , 1.00 BLUE J111 J108 J109 ORANGE YELLOW 2.00 J107 50 J105 J106 J101 , to Channel Channel to Channel All Ports J101 to J105 J106 to J110 OHMS nSec nSec µSec dBm
Daico Industries
Original
J111 stanag stanag 3909 J103 STANAG connector J103 transistor 3 pin J111/11 J111/1 MIL-STD704A RS-422/

IR E78996

Abstract: E78996 IR IRKJ91/08 IRKJ91/10 IRKJ91/12 IR K J101/14 IRKJ101/16 IR K J101/18 IR K J101/20 >FSM (7) 50 Hz (A) 60
-
OCR Scan
IRKE320-04 B40D120 E78996 IR E78996 E78996 IR E78996 Diode IRKE270-04 IRKE270-06 IRKE270-08 IRKE270-10 IRKE270-12 IRKE270-14

pci slot pinout

Abstract: A8411-01 J8 J101 SLOT 1 E8 OPTIONAL SLOT PCI option and PICMG slot J102 E7 OPTIONAL , page A-4. · J7 and J101 (slot 2 and slot 1) are local (secondary bus) PCI option slots. - J101 (slot , . Switches J7 L2 L1+ SLOT 2 E9 J8 J101 SLOT 1 E8 J102 E7 Initialization , , "Signal and Default Information". Figure 1-3. Jumper Resistors J7 L2 L1+ SLOT 2 E9 J101 , /Zero (0) L2 L1+ SLOT 2 J101 J8 SLOT 1 E8 OPTIONAL SLOT PCI option and PICMG
Intel
Original
pci slot pinout A8411-01 A8408 PRAD-4 A8412-01 j20 Schematic DE1B5501 DE1B55501
Abstract: AD6620 Eval Bd AD6640 J3 J100 J300A AD6620 GND +5.0V J301 J101 J301 AD6620 Evaluation Board Jumper Connections. J301: TCK-CK, TA/B-A/B J101: BT3-B3S, BT2-B2S, BT1-B1S, BT0-B0S, CK-CKA J101 , in the above diagram. 3. J101 jumper CK-CKA sets the delay for data between the AD6640 evaluation , CLK CLKB CLKX J101 J301 AD6620 Evaluation Board Jumper Connections. J301: ICK2-TK, TA/B-A/B J101: B3S-A/B, B2S-E2, B1S-E1, B0S-E0, CK-CKA J101 Notes: 1. Jumper is placed on J99 to power the output Analog Devices
Original
AD6600

CNI22-14

Abstract: CNI22-9-1 2.29 (58.29) MAX 48° 29' REF 0.59 (15.0) MAX DM CNI22-9-1 J102 1.18 (30.0) MAX J101 DM CNI22-4 9.042 REF (229.67) 6.562 (166.67) J101 FARSIDE 8.92 MAX (249.4) 0.375 , ' REF J101 FARSIDE 0.005 0.203 (5.16) ±0.001DIA CSK 100° x 0.385 (9.78) DIA 10 PL FWD 30
AIL Systems
Original
CNI22 CNI22-14 CNI22-1 F-111 CNI22-14-1 blade antenna DM 100 uhf antennas CNI22-15-1

5.1channel amplifier

Abstract: data circuit schematics satellite connector ) . 7 Loudspeaker Connectors (J101 . J106 , . J101 . . . J106 Pin Numbers , . 8 J101 . . . J106 Pin Description , J101 SPEAKER OUTPUTS 6 CHANNEL POWER STAGE TAS5186A TAS5086 3.3V Regulator CONTROL , (J101 . J106) Table 2-2. J901 Pin Description PIN NO. 1 2 3 4 NET-NAME AT SCHEMATICS PVDD - GND
Texas Instruments
Original
data circuit schematics satellite connector 5.1channel subwoofer amplifier TAS5086-5186V6EVM SLEU073

QSE66

Abstract: AG31 , 6, etc.). Table 2 describes signal / pin assignments for the J101 connector. Table 1: Signal / pin , A25 B31 D25 B30 A24 A29 Table 2 describes signal / pin assignments for the J101 connector. Table 2 , the right side (connector pin numbers 2, 4, 6, etc.). Table 2: Signal / pin Assignments for the J101 , for the J101 connector Connector pin # 3 5 7 9 11 13 Signal Name MATRIX_IO0 MATRIX_IO1
PLDApplications
Original
QSE66 AG31 QSE25 AD32 QSE60 QSE64 FX100

TAS5508-5142K7EVM

Abstract: J101 ) . 10 Loudspeaker Connectors (J101 . J107 , . 10 J101 . . . J107 Pin Numbers , . 10 J101 . . . J107 Pin Description , PSU INTERFACE (J900) J104 J103 J101 PSU INTERFACE (J901) Gate Drive Regulator 5V , Connectors (J101 . J107) CAUTION Both positive and negative speaker outputs are floating and may not be
Texas Instruments
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TAS5508-5142K7EVM TAS5508B J107 J900 J901 SLEU071
Abstract: ) ( J50 J104 ( ) J101 ) ) J10 ( J101 J102 J110 J105 J108 ( J11 J12 , TERMINALS J101 J102 J103 J104 LEAD FUNCTION Screen Calibration Signal + Signal - CLAMP Vishay Nobel
Original

PI3HDMI101

Abstract: HDMI SWITCH SCHEMATIC HDMI-HDMI Demo Board Rev.B b. Assuming that a Source is connected to HDMI connector J101, after a Sink is , pin of J102) to high level. HPD_A1 signal (HPD pin of J101) will be pulled up by +5V supplied by , 85 115 115 Table 6: Through Impedance Result at Connector J101 Page 14 of 19 AN211 , NA NA 200 pF pF pF Table 7: DDC/CEC Line Capacitance Result at Connector J101 Page 16 of , , C106, C107, C108 C109 C110, C111 D101, D102, D103 JP101, JP102, JP103 J101, J102 J103, J104
Pericom Semiconductor
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PI3HDMI101 HDMI SWITCH SCHEMATIC dvd player schematic diagram philips dVD player with usb port circuit diagram mini HDMI hdmi type d 1.4 pcb layout SW101 B0520LW MMBT3906 MMBT3904 AT24C02B
Abstract: Description 5 Daughter Card Description As shown in Figure 5-1 and Figure 8-1, connector J101 is the , this release, previous versions of the MC1320x Daughter Card may not have R104 inserted. NOTE J101 , connections for J101 and Table 5-2 lists the pin connections for J102. Table 5-1. J101 Pin Connections Pin , Table 5-1. J101 Pin Connections (continued) Pin Number Pin Name 19 IRQ 20 RESET 22 , Pin 32 of J101. Allows the MCU to reset the MC1320X. 15 PTD5/CESI Connects to ATTN of -
OCR Scan
2-121A1A 961001EAA1

nRF24Z1

Abstract: nRF24Z1-EVB ) . 7 Loudspeaker Connectors (J101 . J106 , . J101 . . . J106 Pin Numbers , . 8 J101 . . . J106 Pin Description , J101 SPEAKER OUTPUTS 6 CHANNEL POWER STAGE TAS5186A TAS5086 3.3V Regulator CONTROL , (J101 . J106) Table 2-2. J901 Pin Description PIN NO. 1 2 3 4 NET-NAME AT SCHEMATICS PVDD - GND
Nordic Semiconductor
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N-7075 nRF24Z1 nRF24Z1-EVB eeprom programmer CS5333 usb male connector pcb mounted nRF24Z1-EVKIT RF24Z1 RF24Z1-EVB RF24Z1-EVBOARD RF24Z1EVBOARD
Abstract: 2.29 (58.29) MAX 48° 29' REF 0.59 (15.0) MAX DM CNI22-9-1 J102 1.18 (30.0) MAX J101 DM CNI22-4 9.042 REF (229.67) 6.562 (166.67) J101 FARSIDE 8.92 MAX (249.4) 0.375 , ' REF J101 FARSIDE 0.005 0.203 (5.16) ±0.001DIA CSK 100° x 0.385 (9.78) DIA 10 PL FWD 30 -
OCR Scan
IG400J101H

scr FIR 3d

Abstract: scr C106 , 6, etc.). Table 2 describes signal / pin assignments for the J101 connector. Table 1: Signal / pin , A25 B31 D25 B30 A24 A29 Table 2 describes signal / pin assignments for the J101 connector. Table 2 , the right side (connector pin numbers 2, 4, 6, etc.). Table 2: Signal / pin Assignments for the J101 , for the J101 connector Connector pin # 3 5 7 9 11 13 Signal Name MATRIX_IO0 MATRIX_IO1
Analog Devices
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IEEE-1284 GS00494 scr FIR 3d scr C106 SCR c106 PIN CONFIGURATION scr FIR 3D 41 U307 74LVQ00 74LCX574 74LVQ32 330PF AD6620ST/PCB
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