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AM26LS32DMB Texas Instruments LINE RECEIVER visit Texas Instruments
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SN75182N-10 Texas Instruments DUAL LINE RECEIVER, PDIP14 visit Texas Instruments

In a receiver 50 to 500khz is received play back

Catalog Datasheet MFG & Type PDF Document Tags
Abstract: signals to interface to external DRAM. The MX802 is a low-power 5-volt CMOS LSI device. It is offered in , output. 10. Passband is reduced to (typically) 2700 Hz when a sample rate of 25 kbps or 50 kbps is used , MX802 may also be used without DRAM (as a â'stand alone" CVSD codec), in which case direct access is , condition to the microcontroller by going to logic â'0." This is a "wire-or ableâ' output, enabling the , Data: This is the C-BUS serial data input from the microcontroller. Data is loaded to this device in 8 -
OCR Scan
MX802J MX802LH PLCC-24 MX802LH8 PLCC-28 100S2
Abstract: . 9. RAS output. 10. Passband is reduced to (typically) 2700 Hz when a sample rate of 25 kb/s or 50 , the necessary address, control and refresh signals to interface to external DRAM. The MX802 is a , indicates an interrupt condition to the microcontroller by going to logic â'0.â' This is a â'wire-or , microcontroller. This pin is an open drain output. It therefore has a low impedance pulldown to logic â , microcontroller. Data is loaded to this device in 8-bit bytes, MSB (bit 7) first, and LSB (bit 0) last -
OCR Scan

CVSD encoder

Abstract: HM51256 Request generated (if enabled). If no 'next' command is waiting in the Play Command Buffer when a speech , pin indicates an interrupt condition to the µController, by going to a logic "0." This is a "wire-or , connected when a 256kbit DRAM is employed. Note: To simplify PCB layout, the DRAM address inputs A0 ­ A8 , the µC to the FX802 Store or Play Command Buffer. MSB `Data' is directed to and from DRAM by , to each "Command Complete" Interrupt Request. In either case, the Store or Play Command Complete
CML Microcircuits
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FX802J FX802LG CVSD encoder HM51256 HM511000-15 FX809 FX802LS

a21dc

Abstract: HM51256-15 generated (if enabled). If no 'next' command is waiting in the Play Command Buffer when a speech Play , " CVSD Codec), in which case direct access is provided to the CVSD Codec digital data and clock signals , Interface to external DRAM. The FX802 DVSR Codec is a low-power 5-volt CMOS LSI device. 0 Data S , the ^Controller, by going to a logic "0." This is a "wire-or able" output, enabling the connection of , "C-BUS," serial data input from the ^Controller. Data is loaded to this device in 8-bit bytes, MSB (B7
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OCR Scan
a21dc HM51256-15 at-32k DELTA MODULATION ENCODER AND DECODER In a receiver 50 to 500khz is received play back TMS4256-20 D00D721

vextra

Abstract: 20-PIN the connection loop length is in the range of 4000 feet to 10,000 feet and there happens to be a , maintaining the receiver function when there is no data transmission activity and can issue a signal to , . Common to all of the designs is a good power supply bypassing approach. This is shown in Figure 8. A , . Each receiver amplifier is a summing stage that sums the received signal and the attenuated , gain of the receiver is simply the inverting gain of the received signal path, RF1/RC and RF2/RD. In
Linear Technology
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LT1795 vextra 20-PIN LT1355 LT1795CFE LT1886

tms*1024

Abstract: HM51256-15 also be used without DRAM (as a "stand alone" CVSD Codec), in which case direct access is provided to , the system microcontroller. The MX802 may be used with a 5.0V power supply and is available in the , functions. This is the C-BUS serial data input from the microcontroller. Data is loaded to this device in , than 100. Negative Supply (GND) DRAM Data In/A0/Direct Access - This is connected to the DRAM data input and address line A0. With no DRAM used, this output is available in a Direct Access mode as the
MX-COM
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DBS800 tms*1024 TMS4C1024 Play station 2 C-BUS Microcontroller Interface DRAM 256 X 1, 18 PDIP

POWER COMMAND HM 1300

Abstract: RAS 0510 DRAM (as a "stand alone" CVSD Codec), in which case direct access is provided to the CVSD Codec digital , (if enabled). If no "next" command is waiting in the Play Command Buffer when a speech play command , C-BUS serial clock rate is limited to a maximum of: 125kHz if the VSR Codec is executing store and play , "stand alone" CVSD Codec), in which case direct access is provided to the CVSD Codec digital data and , may be used with a 5.0V power supply and is available in the following packages: 24-pin PLCC (MX802LH
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OCR Scan
POWER COMMAND HM 1300 RAS 0510

HM511000-15

Abstract: smd code marking CK Interrupt Request generated (if enabled). If no 'next' command is waiting in the Play Command Buffer when a , Codec), in which case direct access is provided to the CVSD Codec digital data and clock signals. All , signals to interface to external DRAM. The FX802 DVSR Codec is a low-power 5-volt CMOS LSI device and is , pin indicates an interrupt condition to the ^Controller, by going to a logic "0." This is a "wire-or , Data: The "C-BUS," serial data input from the ^Controller. Data is loaded to this device in 8-bit bytes
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OCR Scan
smd code marking CK 15x45 QDD0171 TMS4256 D/802/2

STR t 6153

Abstract: LBGD Corporation" and "Winbond", respectively. Continuity There is no change to this datasheet as a result of , 's Advanced PC (APC) Division joined Winbond Electronics Corporation on May 5th 2005. As a result, in this , of Winbond products could result or lead to a situation wherein personal injury, death or severe , commonly used ISA, EISA and MicroChannel® peripherals in a single chip. It includes a Floppy Disk , signals that enable game port control, and a configuration register set. In addition, support for power
National Semiconductor
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STR t 6153 LBGD OR-2185 nec upd765 application note PC87338/PC97338 D-82256

smd 45E

Abstract: POSITION DECODER ENCODER interface to external DRAM. The FX802 DVSR Codec is a low-power 5-volt CMOS LSI device and is available in , Request generated (if enabled). If no 'next' command is waiting in the Play Command Buffer when a speech , Codec), in which case direct access is provided to the CVSD Codec digitai data and clock signals. Ali , going to a logic "0." This is a "wire-or able" output, enabling the connection of up to 8 peripherals to , Data is loaded to this device in 8-bit bytes, MSB (B7) first, and LSB (B0) last, synchronized to the
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OCR Scan
smd 45E POSITION DECODER ENCODER

HM51256-15

Abstract: rate is limited to a maximum of: 125kHz if the VSR Codec is executing Store and Play commands. 250kHz , Play Counter direction may be set to run backwards as well as forwards. This can be used in a , is a low-power 5-volt CMOS LSI device and is available in 24-pin/lead SMD, 28-pin DIL and 28-lead SMD , ^Controller, by going to a logic "0." This is a "wire-or able" output, enabling the connection of up to 8 , the ^Controller. Data is loaded to this device in 8-bit bytes, MSB (B7) first, and LSB (BO) last
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IT8661F

Abstract: IT8661RF subject to ITE's Standard Terms and Conditions, a copy of which is included in the back of this document , Acknowledge. This signal goes low to indicate that the printer has already received a character and is ready , PC97/98 (PC99 ready) system requirements. A programmable IRQ sharing function is supported to comply , circuitry to reduce power consumption. Once a logical device is disabled, its related inputs are gate , designed circuit to reduce damage or backdrive current when a printer or another parallel port device is
Integrated Technology Express
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IT8661F IT8661RF PC99 PC intel 945 MOTHERBOARD CIRCUIT diagram

W83757F

Abstract: w83777 . A 4.7K resistor is recommend in order to pullup the pin at power on reset to disable the FDC , function is enabled, and the pin will have a different definition. Refer to the EN3MODE bit in CR9. WD , IOCHRDY 5 OD MR 6 I In EPP Mode, this pin is the IO Channel Ready output to extend the , controller is executing a DMA transfer. In ECP mode, this pin is the parallel port DMA Acknowledge input , active low indicates that a ring signal is being received by the modem or data set. I Serial Input
Winbond Electronics
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W83787IF W83787F W83757F w83777 W83757 w83757af

apc back-ups 500 rs diagram

Abstract: STR W 6856 parallel port when a printer connected to it powers up or is operated at high voltages Output buffers that , to the ISA data bus s Clock source options: - Source is a 32.768 KHz crystal - an internal frequency , PC87307/PC97307 (VUL) are functionally identical parts that offer a single-chip solution to the most , ) and standard PC-AT address decoding for on-chip functions. The Plug and Play (PnP) support in the device conforms to the "Plug and Play ISA Specification" Version 1.0a, May 5, 1994. The Infrared (IR
National Semiconductor
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apc back-ups 500 rs diagram STR W 6856 apc back-ups 500 diagram str 5717 TRACE INVERTER MODEL 2524 apc back-ups 500 rs RECS80 PC97307-IBW/EB PC97307-ICE/EB NSC96 PC97307-ICK/VUL PC97307-IBW/VUL

VT82C686B motherboard

Abstract: VT82C598 bus. Special circuitry is built in to allow concurrent operation without causing dead lock even in a , functionality to make a complete Microsoft PC99-compliant PCI/ISA system. In addition to complete ISA extension , Independent transmit/receiver FIFOs Modem Control Plug and play with 96 base IO address and 12 IRQ options , leakage control · Plug and Play Controller - PCI interrupts steerable to any interrupt channel - , Super-I/O Integrated Peripheral Controller) is a high integration, high performance, power-efficient, and
VIA Technologies
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VT82C686B VT82C686B motherboard VT82C598 VT82C693 vt8501 RX2C MO-151

VT82C686B motherboard

Abstract: VT82C694X bus. Special circuitry is built in to allow concurrent operation without causing dead lock even in a , functionality to make a complete Microsoft PC99-compliant PCI/ISA system. In addition to complete ISA extension , leakage control · Plug and Play Controller - PCI interrupts steerable to any interrupt channel - , Super-I/O Integrated Peripheral Controller) is a high integration, high performance, power-efficient, and , between PCI and IDE devices. In addition to standard PIO and DMA mode operation, the VT82C686B also
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VT82C694X hand movement based fan speed control VT82C694X vt82c686b VT82C42 VT8601 PIR SENSOR IS MOTION SENSOR

M494b

Abstract: command each memory word is read out to its corresponding counter and D/A in sequence. DISPLAY, KEYBOARD , and con tinues to flash until a programme number is selected or any other command is given. If in , logic is implemented so that by tieing the relevant pin to Vss a band can be skipped in regions of no , TO 510KHz CHEAP CERAMIC RESON ATOR V dd = 5V ± 5%. Vpp = 25V ± 1V DESCRIPTION The M494 is a , memory. Separate NV memory is also integrated to provide the memory for four analog controls. A seven
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OCR Scan
M494b 510KH 89DSM494-21 89DSM494-22 89DSM494-23
Abstract: and nor­ malise comm and each m em ory word is read out to its corresponding counter and D/A in , /O line to a nP and as an output line to the P to signal that the M494 is in the Off state. In order , . In 1 * the g segm ent only flashes at 5Hz and con­ tinues to flash until a programm e number is , . This is equivalent to 2 received RC com ­ mands). For the main keyboard matrix (a-g x D0-D4), if the , period of 110ms : a) The program counter is set to program 1. b) The outputs are disabled as defined in -
OCR Scan
M2872

magnetic head FDD

Abstract: PD1 1284 integrator is used to keep track of the speed changes in the input data stream. At the start of a , surrounding bits. Note that if the DMA controller is programmed to function in verify mode a pseudo read , Mbps) Protocol Two DMA Channel for Transmitter and Receiver 32-Byte FIFO is Supported in the TX/RX Terminal - · · 8-Byte Status FIFO Is Supported to Store Received Frame Status (Such as Overrun , addition to the function enhancement, FDC87W21 is pin-topin compatible to FDC87W22. UART includes a 16
Standard MicroSystems
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magnetic head FDD PD1 1284 CR16 RECS-80 Nec Infrared protocol decoder 360K/720K/1 44M/2

VT82C686A

Abstract: VT8601 bus. Special circuitry is built in to allow concurrent operation without causing dead lock even in a , ) Fixed defaults in register tables for Func 1 Rx40, 41, 43, 45, 50 Added note to F0 Rx41[3] & Rx45 , bridge functionality to make a complete Microsoft PC99-compliant PCI/ISA system. In addition to complete , # pin descriptions & Func 4 Rx42[4] Added SCIOUT# to GPIO11 (pin U8), fixed typos in CHAS pin description Fixed typos in Serial Port 2 register descriptions, changed to new logo format Changed FDC "OD"
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VT82C686A VIA Apollo mvp4 via VT82C686 via apollo via VT82C686 data sheet Str 5754 O-151
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