ISP1562 LQFP100 ISP1562BE 24C01 - Datasheet Archive

 

Hi-Speed Universal Serial Bus PCI Host Controller Rev. 02 - 1 March 2007 Product data sheet 1. General description The ISP1562 is

 

ISP1562 ISP1562 Hi-Speed Universal Serial Bus PCI Host Controller Rev. 02 - 1 March 2007 Product data sheet 1. General description The ISP1562 ISP1562 is a Peripheral Component Interconnect (PCI)-based, single-chip Universal Serial Bus (USB) Host Controller. It integrates two Original USB Open Host Controller Interface (OHCI) cores, one Hi-Speed USB Enhanced Host Controller Interface (EHCI) core, and two transceivers that are compliant with Hi-Speed USB and Original USB. The functional parts of the ISP1562 ISP1562 are fully compliant with Universal Serial Bus Specification Rev. 2.0, Open Host Controller Interface Specification for USB Rev. 1.0a, Enhanced Host Controller Interface Specification for Universal Serial Bus Rev. 1.0, PCI Local Bus Specification Rev. 2.2, and PCI Bus Power Management Interface Specification Rev. 1.1. Integrated high performance USB transceivers allow the ISP1562 ISP1562 to handle all Hi-Speed USB transfer speed modes: high-speed (480 Mbit/s), full-speed (12 Mbit/s) and low-speed (1.5 Mbit/s). The ISP1562 ISP1562 provides two downstream ports, allowing simultaneous connection of USB devices at different speeds. The ISP1562 ISP1562 is fully compatible with various operating system drivers, such as Microsoft Windows standard OHCI and EHCI drivers that are present in Windows XP, Windows 2000 and Red Hat Linux. The ISP1562 ISP1562 directly interfaces to any 32-bit, 33 MHz PCI bus. Its PCI pins can source 3.3 V. The PCI interface fully complies with PCI Local Bus Specification Rev. 2.2. The ISP1562 ISP1562 is ideally suited for use in Hi-Speed USB mobile applications and embedded solutions. The ISP1562 ISP1562 uses a 12 MHz crystal. 2. Features I Complies with Universal Serial Bus Specification Rev. 2.0 I Supports data transfer at high-speed (480 Mbit/s), full-speed (12 Mbit/s) and low-speed (1.5 Mbit/s) I Two Original USB OHCI cores comply with Open Host Controller Interface Specification for USB Rev. 1.0a I One Hi-Speed USB EHCI core complies with Enhanced Host Controller Interface Specification for Universal Serial Bus Rev. 1.0 I Supports PCI 32-bit, 33 MHz interface compliant with PCI Local Bus Specification Rev. 2.2, with support for D3cold standby and wake-up modes; all I/O pins are 3.3 V standard I Compliant with PCI Bus Power Management Interface Specification Rev. 1.1 for all hosts (EHCI and OHCI), and supports all power states: D0, D1, D2, D3hot and D3cold ISP1562 ISP1562 NXP Semiconductors HS USB PCI Host Controller I CLKRUN support for mobile applications, such as internal notebook design I Configurable subsystem ID and subsystem Vendor ID through external EEPROM I Digital and analog power separation for better ElectroMagnetic Interference (EMI) and ElectroStatic Discharge (ESD) protection I Supports hot Plug and Play and remote wake-up of peripherals I Supports individual power switching and individual overcurrent protection for downstream ports I Supports partial dynamic port-routing capability for downstream ports that allows sharing of the same physical downstream ports between the Original USB Host Controller and the Hi-Speed USB Host Controller I Uses 12 MHz crystal oscillator to reduce system cost and EMI emissions I Supports dual power supply: PCI Vaux(3V3) and VCC I Operates at +3.3 V power supply input I Low power consumption I Full industrial operating temperature range from -40 °C to +85 °C I Full-scan design with high fault coverage (93 % to 95 %) ensures high quality I Available in LQFP100 LQFP100 package 3. Applications I I I I I I Digital consumer appliances Notebook PCI add-on card PC motherboard Set-Top Box (STB) Web appliances 4. Ordering information Table 1. Ordering information Type number Package Name ISP1562BE ISP1562BE Description Version LQFP100 LQFP100 plastic low profile quad flat package; 100 leads; body 14 × 14 × 1.4 mm SOT407-1 ISP1562 ISP1562_2 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 02 - 1 March 2007 2 of 93 xxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx x xxxxxxxxxxxxxx xxxxxxxxxx xxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxx xxxxxxxxxxxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxx x x 32 AD[31:0] C/BE#[3:0] 96 99 97 77, 98, 100 7 10, 12 to 15, 20 to 22, 26 to 31, 33, 34, 50 to 54, 56, 57, 59, 62, 63, 65 to 70 PCI CORE VOLTAGE REGULATOR (Vaux) 23, 35, 48, 60 REQ# GNT# Rev. 02 - 1 March 2007 32-bit, 33 MHz PCI bus IDSEL INTA# FRAME# DEVSEL# IRDY# CLKRUN# PAR PERR# SERR# TRDY# STOP# RST# VCC(I/O) VI(VREG3V3) PCI MASTER 9 3 2, 73 ISP1562 ISP1562 Vaux(1V8) core 24 PCI SLAVE 4 36 39 CONFIGURATION SPACE 37 CONFIGURATION FUNCTION 0 OHCI (FUNCTION 0) OHCI (FUNCTION 1) EHCI (FUNCTION 2) RAM RAM RAM 42 47 44 CONFIGURATION FUNCTION 1 38 1, 17, 46, 61, 72, 80, 82, 84, 89, 91 PORT ROUTER CORE RESET_N 41 5 ATX1 VOLTAGE REGULATOR VCC CORE ORIGINAL USB ATX ATX2 ORIGINAL USB ATX Hi-SPEED USB ATX 6, 19, 32, 49, 64, 76, 94, 95 Hi-SPEED USB ATX 74 75 XOSC PLL 86, 93 78 79 83 85 87 DM1 DP1 OC2_N 88 90 92 004aaa507 VDDA_AUX OC1_N PWE1_N Fig 1. Block diagram GNDA POR 16 18, 43, 58 RREF CONFIGURATION FUNCTION 2 45 11, 25, 40, 55, 71 81 DM2 PWE2_N DP2 GNDD ISP1562 ISP1562 3 of 93 © NXP B.V. 2007. All rights reserved. XTAL2 AUX1V8 8 VCC(I/O) DETECT XTAL1 VI(VAUX3V3) HS USB PCI Host Controller REG1V8 VCC(I/O)_AUX GLOBAL CONTROL NXP Semiconductors PME# PCICLK SDA 5. Block diagram ISP1562 ISP1562_2 Product data sheet SCL ISP1562 ISP1562 NXP Semiconductors HS USB PCI Host Controller 6. Pinning information 77 VCC(I/O)_AUX 76 GNDD 78 OC1_N 79 PWE1_N 80 GNDA 81 RREF 82 GNDA 83 DM1 84 GNDA 85 DP1 86 VDDA_AUX 87 OC2_N 88 PWE2_N 89 GNDA 90 DM2 91 GNDA 92 DP2 93 VDDA_AUX 94 GNDD 95 GNDD 96 SCL 97 SDA 98 VCC(I/O)_AUX 99 PME# 100 VCC(I/O)_AUX 6.1 Pinning GNDA 1 75 XTAL2 AUX1V8 2 74 XTAL1 VI(VAUX3V3) 3 73 AUX1V8 INTA# 4 72 GNDA RST# 5 71 VCC(I/O) GNDD 6 70 AD[0] PCICLK 7 69 AD[1] GNT# 8 68 AD[2] REQ# 9 67 AD[3] AD[31] 10 66 AD[4] VCC(I/O) 11 65 AD[5] AD[30] 12 64 GNDD ISP1562BE ISP1562BE AD[29] 13 63 AD[6] AD[28] 14 62 AD[7] AD[27] 15 61 GNDA VI(VREG3V3) 16 60 C/BE#[0] GNDA 17 59 AD[8] REG1V8 18 58 REG1V8 GNDD 19 57 AD[9] AD[26] 20 56 AD[10] AD[25] 21 55 VCC(I/O) AD[24] 22 54 AD[11] AD[15] 50 GNDD 49 C/BE#[1] 48 PAR 47 GNDA 46 SERR# 45 PERR# 44 REG1V8 43 CLKRUN# 42 STOP# 41 VCC(I/O) 40 DEVSEL# 39 TRDY# 38 IRDY# 37 FRAME# 36 C/BE#[2] 35 AD[16] 34 AD[17] 33 GNDD 32 AD[18] 31 AD[19] 30 51 AD[14] AD[20] 29 VCC(I/O) 25 AD[21] 28 52 AD[13] AD[22] 27 53 AD[12] IDSEL 24 AD[23] 26 C/BE#[3] 23 004aaa508 Fig 2. Pin configuration ISP1562 ISP1562_2 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 02 - 1 March 2007 4 of 93 ISP1562 ISP1562 NXP Semiconductors HS USB PCI Host Controller 6.2 Pin description Table 2. Pin description Symbol[1] Pin Type Description GNDA 1 - analog ground AUX1V8 2 - 1.8 V auxiliary output voltage; only for voltage conditioning; cannot be used to supply power to external components; connected to 100 nF and 20 µF capacitors VI(VAUX3V3) 3 - 3.3 V auxiliary input voltage; add a 100 nF decoupling capacitor INTA# 4 O PCI interrupt PCI pad; 3.3 V signaling; open-drain RST# 5 I PCI reset; used to bring PCI-specific registers, sequencers and signals to a consistent state 3.3 V input pad; push-pull; CMOS GNDD 6 - digital ground PCICLK 7 I PCI system clock; see Table 118 PCI pad; 3.3 V signaling GNT# 8 I/O PCI grant; indicates to the agent that access to the bus is granted REQ# 9 I/O PCI request; indicates to the arbitrator that the agent wants to use the bus AD[31] 10 I/O bit 31 of multiplexed PCI address and data PCI pad; 3.3 V signaling PCI pad; 3.3 V signaling PCI pad; 3.3 V signaling VCC(I/O) 11 - 3.3 V supply voltage; used to power pads; add a 100 nF decoupling capacitor AD[30] 12 I/O bit 30 of multiplexed PCI address and data AD[29] 13 I/O bit 29 of multiplexed PCI address and data PCI pad; 3.3 V signaling PCI pad; 3.3 V signaling AD[28] 14 I/O bit 28 of multiplexed PCI address and data PCI pad; 3.3 V signaling AD[27] 15 I/O bit 27 of multiplexed PCI address and data PCI pad; 3.3 V signaling VI(VREG3V3) 16 - 3.3 V regulator input voltage; add a 100 nF decoupling capacitor GNDA 17 - analog ground REG1V8 18 - 1.8 V regulator output voltage; only for voltage conditioning; cannot be used to supply power to external components; connected to a 100 nF capacitor and a 4.7 µF-to-10 µF capacitor GNDD 19 - digital ground AD[26] 20 I/O bit 26 of multiplexed PCI address and data PCI pad; 3.3 V signaling AD[25] 21 I/O bit 25 of multiplexed PCI address and data PCI pad; 3.3 V signaling AD[24] 22 I/O bit 24 of multiplexed PCI address and data PCI pad; 3.3 V signaling ISP1562 ISP1562_2 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 02 - 1 March 2007 5 of 93 ISP1562 ISP1562 NXP Semiconductors HS USB PCI Host Controller Table 2. Pin description .continued Symbol[1] Pin Type Description C/BE#[3] 23 I/O byte 3 of multiplexed PCI bus command and byte enable PCI pad; 3.3 V signaling IDSEL 24 I PCI initialization device select; used as a chip select during configuration read and write transactions PCI pad; 3.3 V signaling VCC(I/O) 25 - 3.3 V supply voltage; used to power pads; add a 100 nF decoupling capacitor AD[23] 26 I/O bit 23 of multiplexed PCI address and data AD[22] 27 I/O bit 22 of multiplexed PCI address and data PCI pad; 3.3 V signaling PCI pad; 3.3 V signaling AD[21] 28 I/O bit 21 of multiplexed PCI address and data PCI pad; 3.3 V signaling AD[20] 29 I/O bit 20 of multiplexed PCI address and data PCI pad; 3.3 V signaling AD[19] 30 I/O bit 19 of multiplexed PCI address and data AD[18] 31 I/O bit 18 of multiplexed PCI address and data PCI pad; 3.3 V signaling PCI pad; 3.3 V signaling GNDD 32 - digital ground AD[17] 33 I/O bit 17 of multiplexed PCI address and data PCI pad; 3.3 V signaling AD[16] 34 I/O bit 16 of multiplexed PCI address and data PCI pad; 3.3 V signaling C/BE#[2] 35 I/O byte 2 of multiplexed PCI bus command and byte enable PCI pad; 3.3 V signaling FRAME# 36 I/O PCI cycle frame; driven by the master to indicate the beginning and duration of an access PCI pad; 3.3 V signaling IRDY# 37 I/O PCI initiator ready; indicates the ability of the initiating agent to complete the current data phase of a transaction PCI pad; 3.3 V signaling TRDY# 38 I/O PCI target ready; indicates the ability of the target agent to complete the current data phase of a transaction PCI pad; 3.3 V signaling DEVSEL# 39 I/O PCI device select; indicates if any device is selected on the bus VCC(I/O) 40 - 3.3 V supply voltage; used to power pads; add a 100 nF decoupling capacitor STOP# 41 I/O PCI stop; indicates that the current target is requesting the master to stop the current transaction PCI pad; 3.3 V signaling PCI pad; 3.3 V signaling CLKRUN# 42 I/O PCI CLKRUN signal; pull-down to ground through a 10 k resistor PCI pad; 3.3 V signaling; open-drain ISP1562 ISP1562_2 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 02 - 1 March 2007 6 of 93 ISP1562 ISP1562 NXP Semiconductors HS USB PCI Host Controller Table 2. Pin description .continued Symbol[1] Pin Type Description REG1V8 43 - 1.8 V regulator output voltage; only for voltage conditioning; cannot be used to supply power to external components; add a 100 nF decoupling capacitor PERR# 44 I/O PCI parity error; used to report data parity errors during all PCI transactions, except a special cycle PCI pad; 3.3 V signaling SERR# 45 O PCI system error; used to report address parity errors and data parity errors on the Special Cycle command, or any other system error in which the result will be catastrophic GNDA 46 - analog ground PAR 47 I/O PCI parity C/BE#[1] 48 I/O byte 1 of multiplexed PCI bus command and byte enable PCI pad; 3.3 V signaling; open-drain PCI pad; 3.3 V signaling PCI pad; 3.3 V signaling GNDD 49 - digital ground AD[15] 50 I/O bit 15 of multiplexed PCI address and data PCI pad; 3.3 V signaling AD[14] 51 I/O bit 14 of multiplexed PCI address and data PCI pad; 3.3 V signaling AD[13] 52 I/O bit 13 of multiplexed PCI address and data PCI pad; 3.3 V signaling AD[12] 53 I/O bit 12 of multiplexed PCI address and data AD[11] 54 I/O bit 11 of multiplexed PCI address and data PCI pad; 3.3 V signaling PCI pad; 3.3 V signaling VCC(I/O) 55 - 3.3 V supply voltage; used to power pads; add a 100 nF decoupling capacitor AD[10] 56 I/O bit 10 of multiplexed PCI address and data AD[9] 57 I/O bit 9 of multiplexed PCI address and data PCI pad; 3.3 V signaling PCI pad; 3.3 V signaling REG1V8 58 - 1.8 V regulator output voltage; only for voltage conditioning; cannot be used to supply power to external components; add a 100 nF decoupling capacitor AD[8] 59 I/O bit 8 of multiplexed PCI address and data PCI pad; 3.3 V signaling C/BE#[0] 60 I/O byte 0 of multiplexed PCI bus command and byte enable GNDA 61 - analog ground AD[7] 62 I/O bit 7 of multiplexed PCI address and data AD[6] 63 I/O bit 6 of multiplexed PCI address and data PCI pad; 3.3 V signaling PCI pad; 3.3 V signaling PCI pad; 3.3 V signaling ISP1562 ISP1562_2 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 02 - 1 March 2007 7 of 93 ISP1562 ISP1562 NXP Semiconductors HS USB PCI Host Controller Table 2. Pin description .continued Symbol[1] Pin Type Description GNDD 64 - digital ground AD[5] 65 I/O bit 5 of multiplexed PCI address and data AD[4] 66 I/O bit 4 of multiplexed PCI address and data PCI pad; 3.3 V signaling PCI pad; 3.3 V signaling AD[3] 67 I/O bit 3 of multiplexed PCI address and data PCI pad; 3.3 V signaling AD[2] 68 I/O bit 2 of multiplexed PCI address and data PCI pad; 3.3 V signaling AD[1] 69 I/O bit 1 of multiplexed PCI address and data AD[0] 70 I/O bit 0 of multiplexed PCI address and data PCI pad; 3.3 V signaling PCI pad; 3.3 V signaling VCC(I/O) 71 - 3.3 V supply voltage; used to power pads; add a 100 nF decoupling capacitor GNDA 72 - analog ground AUX1V8 73 - 1.8 V auxiliary output voltage; only for voltage conditioning; cannot be used to supply power to external components; add a 100 nF decoupling capacitor XTAL1 74 AI crystal oscillator input; this can also be a 12 MHz clock input XTAL2 75 AO crystal oscillator output (12 MHz); leave open when clock is used GNDD 76 - digital ground VCC(I/O)_AUX 77 - 3.3 V auxiliary supply voltage; used to power pads; add a 100 nF decoupling capacitor OC1_N I overcurrent sense input for the USB downstream port 1 (digital) 78 3.3 V input pad; push-pull; CMOS PWE1_N 79 O power enable for the USB downstream port 1 GNDA 80 - analog ground RREF 81 AI/O analog connection for the external resistor (12 k ± 1 %) GNDA 82 - analog ground DM1 83 AI/O D-; analog connection for the USB downstream port 1; pull-down to ground through a 15 k resistor GNDA 84 - analog ground DP1 85 AI/O D+; analog connection for the USB downstream port 1; pull-down to ground through a 15 k resistor VDDA_AUX 86 - auxiliary analog supply voltage; add a 100 nF decoupling capacitor OC2_N 87 I overcurrent sense input for the USB downstream port 2 (digital) PWE2_N 88 O power enable for the USB downstream port 2 3.3 V output pad; 3 ns slew rate control; CMOS; open-drain 3.3 V input pad; push-pull; CMOS 3.3 V output pad; 3 ns slew rate control; CMOS; open-drain GNDA 89 - analog ground ISP1562 ISP1562_2 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 02 - 1 March 2007 8 of 93 ISP1562 ISP1562 NXP Semiconductors HS USB PCI Host Controller Table 2. Pin description .continued Symbol[1] Pin Type Description DM2 90 AI/O D-; analog connection for the USB downstream port 2; pull-down to ground through a 15 k resistor GNDA 91 - analog ground DP2 92 AI/O D+; analog connection for the USB downstream port 2; pull-down to ground through a 15 k resistor VDDA_AUX 93 - auxiliary analog supply voltage; add a 100 nF decoupling capacitor GNDD 94 - digital ground GNDD 95 - digital ground SCL 96 I/O I2C-bus clock; pull-up to 3.3 V through a 10 k resistor[2] I2C-bus pad; clock signal SDA 97 I/O I2C-bus data; pull-up to 3.3 V through a 10 k resistor[2] I2C-bus pad; data signal VCC(I/O)_AUX 98 - 3.3 V auxiliary supply voltage; used to power pads; add a 100 nF decoupling capacitor PME# O PCI Power Management Event; used by a device to request a change in the device or system power state - 3.3 V auxiliary supply voltage; used to power pads; add a 100 nF decoupling capacitor 99 PCI pad; 3.3 V signaling; open-drain VCC(I/O)_AUX 100 [1] Symbol names ending with # represent active LOW signals for PCI pins, for example: NAME#. Symbol names ending with underscore N represent active LOW signals for USB pins, for example: NAME_N. [2] Connect to ground if I2C-bus is not used. ISP1562 ISP1562_2 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 02 - 1 March 2007 9 of 93 ISP1562 ISP1562 NXP Semiconductors HS USB PCI Host Controller 7. Functional description 7.1 OHCI Host Controller An OHCI Host Controller per port transfers data to devices at the Original USB defined bit rate of 12 Mbit/s or 1.5 Mbit/s. 7.2 EHCI Host Controller The EHCI Host Controller transfers data to a Hi-Speed USB compliant device at the Hi-Speed USB defined bit rate of 480 Mbit/s. When the EHCI Host Controller has the ownership of a port, OHCI Host Controllers are not allowed to modify the port register. All additional port bit definitions required for the enhanced Host Controller are not visible to the OHCI Host Controller. 7.3 Dynamic port-routing logic The port-routing feature allows sharing of the same physical downstream ports between the Original USB Host Controller and the Hi-Speed USB Host Controller. This requirement of Enhanced Host Controller Interface Specification for Universal Serial Bus Rev. 1.0 provides ports that are multiplexed with the ports of the OHCI. The EHCI is responsible for the port-routing switching mechanism. Two register bits are used for ownership switching. During power-on and system reset, the default ownership of all downstream ports is the OHCI. The enhanced Host Controller Driver (HCD) controls the ownership during normal functionality. 7.4 Hi-Speed USB analog transceivers The Hi-Speed USB analog transceivers directly interface to the USB cables through integrated termination resistors. These transceivers can transmit and receive serial data at all data rates: high-speed (480 Mbit/s), full-speed (12 Mbit/s) and low-speed (1.5 Mbit/s). 7.5 Power management The ISP1562 ISP1562 provides an advanced power management capability interface that is compliant with PCI Bus Power Management Interface Specification Rev. 1.1. Power is controlled and managed by the interaction between drivers and PCI registers. For a detailed description on power management, see Section 10. 7.6 Phase-Locked Loop (PLL) A 12 MHz-to-30 MHz and 48 MHz clock multiplier PLL is integrated on-chip. This allows the use of a low-cost 12 MHz crystal, which also minimizes EMI. No external components are required for the PLL to operate. ISP1562 ISP1562_2 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 02 - 1 March 2007 10 of 93 ISP1562 ISP1562 NXP Semiconductors HS USB PCI Host Controller 7.7 Power-On Reset (POR) Figure 3 shows a possible curve of VCC(I/O) with dips at t2 to t3 and t4 to t5. At t0, POR will start with 1. At t1, the detector passes through the trip level. Another delay will be added before POR drops to 0 to ensure that the length of the generated detector pulse, POR, is large enough to reset asynchronous flip-flops. If the dip is too short (t4 to t5 < 11 µs), POR will not react and will stay LOW. VCC(I/O) VPOR(trip) t0 t1 t2 t3 t4 t5 POR 004aaa664 VPOR(trip) is typically 1.2 V. Fig 3. Power-on reset 7.8 Power supply Figure 4 shows the ISP1562 ISP1562 power supply connection. ISP1562 ISP1562_2 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 02 - 1 March 2007 11 of 93 ISP1562 ISP1562 NXP Semiconductors HS USB PCI Host Controller ISP1562 ISP1562 16 VI(VREG3V3) PCI 3.3 V 100 nF 11, 25, 40, 55, 71 VCC(I/O) PCI 3.3 V 100 nF VI(VAUX3V3) PCI Vaux(3V3)(1) 3 100 nF VCC(I/O)_AUX 77, 98, 100 PCI Vaux(3V3)(1) 100 nF VDDA_AUX PCI Vaux(3V3)(1) 86, 93 100 nF AUX1V8 2 20 µF(2) 100 nF AUX1V8 73 100 nF 18 REG1V8 4.7 µF(2) 43, 58 100 nF REG1V8 100 nF 1, 6, 17, 19, 32, 46, 49, 61, 64, 72, 76, 80, 82, 84, 89, 91, 94, 95 GND 004aaa665 (1) If Vaux(3V3) is not present on PCI, the pin should be connected to PCI 3.3 V. (2) This electrolytic or tantalum capacitor must be of LOW ESR type (0.2 to 2 ). Fig 4. Power supply connection 8. PCI 8.1 PCI interface The PCI interface has three functions. The first function (#0) and the second function (#1) are for OHCI Host Controllers, and the third function (#2) is for the EHCI Host Controller. All functions support both master and target accesses, and share the same PCI interrupt signal INTA#. These functions provide memory-mapped, addressable operational registers as required in Open Host Controller Interface Specification for USB Rev. 1.0a and Enhanced Host Controller Interface Specification for Universal Serial Bus Rev. 1.0. ISP1562 ISP1562_2 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 02 - 1 March 2007 12 of 93 ISP1562 ISP1562 NXP Semiconductors HS USB PCI Host Controller Each function has its own configuration space. The PCI enumerator must allocate the memory address space for each of these functions. Power management is implemented in each PCI function and all power states are provided. This allows the system to achieve low power consumption by switching off the functions that are not required. 8.1.1 PCI configuration space PCI Local Bus Specification Rev. 2.2 requires that each of the three PCI functions of the ISP1562 ISP1562 provides its own PCI configuration registers, which can vary in size. In addition to the basic PCI configuration header registers, these functions implement capability registers to support power management. The registers of each of these functions are accessed by the respective driver. Section 8.2 provides a detailed description of various PCI configuration registers. 8.1.2 PCI initiator and target A PCI initiator initiates PCI transactions to the PCI bus. A PCI target responds to PCI transactions as a slave. In the ISP1562 ISP1562, two Open Host Controllers and the enhanced Host Controller function as both initiators or targets of PCI transactions issued by the host CPU. All USB Host Controllers have their own operational registers that can be accessed by the system driver software. Drivers use these registers to configure the Host Controller hardware system, issue commands to it, and monitor the status of the current hardware operation. The Host Controller plays the role of a PCI target. All operational registers of the Host Controllers are the PCI transaction targets of the CPU. Normal USB transfers require the Host Controller to access system memory fields, which are allocated by USB HCDs and PCI drivers. The Host Controller hardware interacts with the HCD by accessing these buffers. The Host Controller works as an initiator in this case and becomes a PCI master. 8.2 PCI configuration registers OHCI USB Host Controllers and the EHCI USB Host Controller contain two sets of software-accessible hardware registers: PCI configuration registers and memory-mapped Host Controller registers. A set of configuration registers is implemented for each of the three PCI functions of the ISP1562 ISP1562, see Table 3. Remark: In addition to the normal PCI header, from offset index 00h to 3Fh, implementation-specific registers are defined to support power management and function-specific features. Table 3. PCI configuration space registers of OHCI1, OHCI2 and EHCI Address Bits 31 to 24 Bits 23 to 16 Bits 15 to 8 Reset value[1] Bits 7 to 0 Func0 OHCI1 Func1 OHCI2 Func2 EHCI PCI configuration header registers 00h DID[15:0] VID[15:0] 1561 1131h 1561 1131h 1562 1131h 04h STATUS[15:0] CMD[15:0] 0210 0000h 0210 0000h 0210 0000h 0C03 1011h 0C03 1011h 0C03 2011h 08h CC[23:0] REVID[7:0] ISP1562 ISP1562_2 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 02 - 1 March 2007 13 of 93 ISP1562 ISP1562 NXP Semiconductors HS USB PCI Host Controller Table 3. PCI configuration space registers of OHCI1, OHCI2 and EHCI .continued Address Bits 31 to 24 Bits 23 to 16 Bits 15 to 8 Reset value[1] Bits 7 to 0 Func0 OHCI1 Func1 OHCI2 0080 0000h 0080 0000h 0000 0000h 0000 0000h 0000 0000h reserved reserved 0080 0000h BAR0[31:0] 0Ch Func2 EHCI 0000 0000h 0000 0000h 0000 0000h 1561 1131h 1561 1131h 1562 1131h 0000 0000h 0000 0000h 0000 0000h HT[7:0] 10h LT[7:0] CLS[7:0] 14h 18h 1Ch 20h 24h 28h 2Ch SID[15:0] 30h SVID[15:0] reserved 34h reserved 38h CP[7:0] 3Ch MAX_LAT [7:0] 40h MIN_GNT [7:0] reserved 0000 00DCh 0000 00DCh 0000 00DCh 0000 0000h reserved 0000 0000h 0000 0000h IP[7:0] IL[7:0] 2A01 0100h 2A01 0100h 1002 0100h RETRY_ TIMEOUT TRDY_ TIMEOUT 0000 8000h 0000 8000h 0000 8000h Enhanced Host Controller-specific PCI registers 60h PORTWAKECAP[15:0] FLADJ[7:0] SBRN[7:0] - - 0007 2020h NEXT_ITEM_ CAP_ID[7:0] PTR[7:0] D282 0001h D282 0001h FE82 0001h PMCSR[15:0] 0000 XX00h[2] 0000 XX00h[2] 0000 XX00h[2] Power management registers DCh E0h PMC[15:0] DATA[7:0] PMCSR_BSE [7:0] [1] Reset values that are highlighted (for example, 0) indicate read and write accesses; and reset values that are not highlighted (for example, 0) indicate read-only. [2] See Section 8.2.3.4. The HCD does not usually interact with the PCI configuration space. The configuration space is used only by the PCI enumerator to identify the USB Host Controller and assign appropriate system resources by reading the Vendor ID (VID) and the Device ID (DID). 8.2.1 PCI configuration header registers The enhanced Host Controller implements normal PCI header register values, except the values for the memory-mapping base address register, serial bus number and device ID. 8.2.1.1 Vendor ID register This read-only register identifies the manufacturer of the device. PCI Special Interest Group (PCI-SIG) assigns valid vendor identifiers to ensure the uniqueness of the identifier. The bit description is shown in Table 4. ISP1562 ISP1562_2 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 02 - 1 March 2007 14 of 93 ISP1562 ISP1562 NXP Semiconductors HS USB PCI Host Controller Table 4. VID - Vendor ID register (address 00h) bit description Legend: * reset value Bit Symbol Access Value Description 15 to 0 VID[15:0] R Vendor ID: This read-only register value is assigned to NXP Semiconductors by PCI-SIG as 1131h. 8.2.1.2 1131h* Device ID register This is a 2-byte read-only register that identifies a particular device. The identifier is allocated by NXP Semiconductors. Table 5 shows the bit description of the register. Table 5. DID - Device ID register (address 02h) bit description Legend: * reset value Bit Symbol 15 to 0 [1] DID[15:0] Access Value Description R X*[1] Device ID: This register value is defined by NXP Semiconductors to identify the Hi-Speed USB Host Controller IC product. For the ISP1562 ISP1562, NXP Semiconductors has defined OHCI functions as 1561h, and the EHCI function as 1562h. X is 1561h for OHCI1 and OHCI2; X is 1562h for EHCI. 8.2.1.3 Command register This is a 2-byte register that provides coarse control over the ability of a device to generate and respond to PCI cycles. The bit allocation of the Command register is given in Table 6. When logic 0 is written to this register, the device is logically disconnected from the PCI bus for all accesses, except configuration accesses. All devices are required to support this base level of functionality. Individual bits in the Command register may or may not support this base level of functionality. Table 6. CMD - Command register (address 04h) bit allocation Bit 15 14 13 12 11 10 Symbol Reset 9 8 FBBE reserved[1] SERRE 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 SCTRL PER VGAPS MWIE SC BM MS IOS Access Bit Symbol Reset 0 0 0 0 0 0 0 0 Access R R/W R R/W R R/W R/W R/W [1] The reserved bits should always be written with the reset value. ISP1562 ISP1562_2 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 02 - 1 March 2007 15 of 93 ISP1562 ISP1562 NXP Semiconductors HS USB PCI Host Controller Table 7. CMD - Command register (address 04h) bit description Bit Symbol Description 15 to 10 reserved - 9 FBBE Fast Back-to-Back Enable: This bit controls whether a master can do fast back-to-back transactions to various devices. The initialization software must set this bit if all targets are fast back-to-back capable. 0 - Fast back-to-back transactions are only allowed to the same agent (value after RST#). 1 - The master is allowed to generate fast back-to-back transactions to different agents. 8 SERRE SERR# Enable: This bit is an enable bit for the SERR# driver. All devices that have an SERR# pin must implement this bit. Address parity errors are reported only if this bit and the PER bit are logic 1. 0 - Disable the SERR# driver. 1 - Enable the SERR# driver. 7 SCTRL Stepping Control: This bit controls whether a device does address and data stepping. Devices that never do stepping must clear this bit. Devices that always do stepping must set this bit. Devices that can do either, must make this bit read and write, and initialize it to logic 1 after RST#. 6 PER Parity Error Response: This bit controls the response of a device to parity errors. When the bit is set, the device must take its normal action when a parity error is detected. When the bit is logic 0, the device sets DPE (bit 15 in the Status register) when an error is detected, but does not assert PERR# and continues normal operation. The state of this bit after RST# is logic 0. Devices that check parity must implement this bit. Devices are required to generate parity, even if parity checking is disabled. 5 VGAPS VGA Palette Snoop: This bit controls how VGA compatible and graphics devices handle accesses to VGA palette registers. 0 - The device must treat palette write accesses like all other accesses. 1 - Palette snooping is enabled, that is, the device does not respond to palette register writes and snoops data. VGA compatible devices must implement this bit. 4 MWIE Memory Write and Invalidate Enable: This is an enable bit for using the Memory Write and Invalidate command. 0 - Memory writes must be used instead. State after RST# is logic 0. 1 - Masters may generate the command. This bit must be implemented by master devices that can generate the Memory Write and Invalidate command. 3 SC Special Cycles: Controls the action of a device on special cycle operations. 0 - Causes the device to ignore all special cycle operations. State after RST# is logic 0. 1 - Allows the device to monitor special cycle operations. 2 BM Bus Master: Controls the ability of a device to act as a master on the PCI bus. 0 - Disables the device from generating PCI accesses. State after RST# is logic 0. 1 - Allows the device to behave as a bus master. 1 MS Memory Space: Controls the response of a device to memory space accesses. 0 - Disables the device response. State after RST# is logic 0. 1 - Allows the device to respond to memory space accesses. 0 IOS IO Space: Controls the response of a device to I/O space accesses. 0 - Disables the device response. State after RST# is logic 0. 1 - Allows the device to respond to I/O space accesses. ISP1562 ISP1562_2 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 02 - 1 March 2007 16 of 93 ISP1562 ISP1562 NXP Semiconductors HS USB PCI Host Controller 8.2.1.4 Status register The Status register is a 2-byte read-only register used to record status information on PCI bus-related events. For bit allocation, see Table 8. Table 8. STATUS - Status register (address 06h) bit allocation Bit 15 14 13 12 11 DPE SSE RMA RTA STA Reset 0 0 0 0 0 0 1 0 Access R R R R R R R R Bit 7 6 5 4 3 2 1 0 FBBC reserved 66MC CL Reset 0 0 0 1 0 0 0 0 Access R R R R R R R R Symbol Symbol Table 9. 10 9 DEVSELT[1:0] 8 MDPE reserved STATUS - Status register (address 06h) bit description Bit Symbol Description 15 DPE Detected Parity Error: This bit must be set by the device whenever it detects a parity error, even if the parity error handling is disabled. 14 SSE Signaled System Error: This bit must be set whenever the device asserts SERR#. Devices that never assert SERR# do not need to implement this bit. 13 RMA Received Master Abort: This bit must be set by a master device whenever its transaction, except for special cycle, is terminated with master abort. All master devices must implement this bit. 12 RTA Received Target Abort: This bit must be set by a master device whenever its transaction is terminated with target abort. All master devices must implement this bit. 11 STA Signaled Target Abort: This bit must be set by a target device whenever it terminates a transaction with target abort. Devices that never signal target abort do not need to implement this bit. 10 to 9 DEVSELT [1:0] DEVSEL Timing: These bits encode the timing of DEVSEL#. There are three allowable timing to assert DEVSEL#: 00b - Fast 01b - Medium 10b - Slow 11b - Reserved These bits are read-only and must indicate the slowest time that a device asserts DEVSEL# for any bus command, except Configuration Read and Configuration Write. 8 MDPE Master Data Parity Error: This bit is implemented by bus masters. It is set when the following three conditions are met: · · · The bus agent asserted PERR# itself, on a read; or observed PERR# asserted, on a write. The agent setting the bit acted as the bus master for the operation in which error occurred. PER (bit 6 in the Command register) is set. 7 FBBC Fast Back-to-Back Capable: This read-only bit indicates whether the target is capable of accepting fast back-to-back transactions when the transactions are not to the same agent. This bit can be set to logic 1, if the device can accept these transactions; and must be set to logic 0 otherwise. 6 reserved - ISP1562 ISP1562_2 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 02 - 1 March 2007 17 of 93 ISP1562 ISP1562 NXP Semiconductors HS USB PCI Host Controller Table 9. STATUS - Status register (address 06h) bit description .continued Bit Symbol Description 5 66MC 66 MHz Capable: This read-only bit indicates whether this device is capable of running at 66 MHz. 0 - 33 MHz 1 - 66 MHz 4 CL Capabilities List: This read-only bit indicates whether this device implements the pointer for a new capabilities linked list at offset 34h. 0 - No new capabilities linked list is available. 1 - The value read at offset 34h is a pointer in configuration space to a linked list of new capabilities. 3 to 0 reserved - 8.2.1.5 Revision ID register This 1-byte read-only register indicates a device-specific revision identifier. The value is chosen by the vendor. This field is a vendor-defined extension of the device ID. The Revision ID register bit description is given in Table 10. Table 10. REVID - Revision ID register (address 08h) bit description Legend: * reset value Bit Symbol Access 7 to 0 REVID[7:0] R 8.2.1.6 Value Description 11h* Revision ID: This byte specifies the design revision number of functions. Class Code register Class Code is a 24-bit read-only register used to identify the generic function of the device, and in some cases, a specific register-level programming interface. Table 11 shows the bit allocation of the register. The Class Code register is divided into three byte-size fields. The upper byte is a base class code that broadly classifies the type of function the device performs. The middle byte is a sub-class code that identifies more specifically the function of the device. The lower byte identifies a specific register-level programming interface, if any, so that device-independent software can interact with the device. Table 11. CC - Class Code register (address 09h) bit allocation Bit 23 22 21 20 Symbol 19 18 17 16 BCC[7:0] Reset 0Ch Access R R R R R R R R Bit 15 14 13 12 11 10 9 8 Symbol SCC[7:0] Reset 03h Access R R R R R R R R Bit 7 6 5 4 3 2 1 0 R R R R Symbol RLPI[7:0] X[1] Reset Access [1] R R R R X is 10h for OHCI1 and OHCI2; X is 20h for EHCI. ISP1562 ISP1562_2 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 02 - 1 March 2007 18 of 93 ISP1562 ISP1562 NXP Semiconductors HS USB PCI Host Controller Table 12. Bit CC - Class Code register (address 09h) bit description Symbol Description 23 to 16 BCC[7:0] Base Class Code: 0Ch is the base class code assigned to this byte. It implies a serial bus controller. 15 to 8 SCC[7:0] Sub-Class Code: 03h is the sub-class code assigned to this byte. It implies the USB Host Controller. 7 to 0 RLPI[7:0] Register-Level Programming Interface: 10h is the programming interface code assigned to OHCI, which is USB 1.1 specification compliant. 20h is the programming interface code assigned to EHCI, which is USB 2.0 specification compliant. 8.2.1.7 CacheLine Size register The CacheLine Size register is a read and write single-byte register that specifies the system CacheLine size in units of DWORDs. This register must be implemented by master devices that can generate the Memory Write and Invalidate command. The value in this register is also used by master devices to determine whether to use Read, Read Line or Read Multiple command to access the memory. Slave devices that want to allow memory bursting using CacheLine-wrap addressing mode must implement this register to know when a burst sequence wraps to the beginning of the CacheLine. This field must be initialized to logic 0 on activation of RST#. Table 13 shows the bit description of the CacheLine Size register. Table 13. CLS - CacheLine Size register (address 0Ch) bit description Legend: * reset value Bit Symbol Access Value Description 7 to 0 CLS[7:0] R/W 00h* CacheLine Size: This byte identifies the system CacheLine size. 8.2.1.8 Latency Timer register This register specifies, in units of PCI bus clocks, the value of the Latency Timer for the PCI bus master. Table 14 shows the bit description of the Latency Timer register. Table 14. LT - Latency Timer register (address 0Dh) bit description Legend: * reset value Bit Symbol Access Value Description 7 to 0 LT[7:0] R/W 00h* Latency Timer: This byte identifies the latency timer. 8.2.1.9 Header Type register The Header Type register identifies the layout of the second part of the predefined header, beginning at byte 10h in configuration space. It also identifies whether the device contains multiple functions. For bit allocation, see Table 15. Table 15. HT - Header Type register (address 0Eh) bit allocation Bit Symbol 7 6 5 4 MFD 3 2 1 0 HT[6:0] Reset 1 0 0 0 0 0 0 0 Access R R R R R R R R ISP1562 ISP1562_2 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 02 - 1 March 2007 19 of 93 ISP1562 ISP1562 NXP Semiconductors HS USB PCI Host Controller Table 16. HT - Header Type register (address 0Eh) bit description Bit Symbol Description 7 MFD Multi-Function Device: This bit identifies a multifunction device. 0 - The device has single function. 1 - The device has multiple functions. 6 to 0 HT[6:0] Header Type: These bits identify the layout of the part of the predefined header, beginning at byte 10h in configuration space. 8.2.1.10 Base Address register 0 Power-up software must build a consistent address map before booting the machine to an operating system. This means it must determine how much memory is in the system, and how much address space the I/O controllers in the system require. After determining this information, power-up software can map the I/O controllers into reasonable locations and proceed with system boot. To do this mapping in a device-independent manner, base registers for this mapping are placed in the predefined header portion of configuration space. Bit 0 in all Base Address registers is read-only and used to determine whether the register maps into memory or I/O space. Base Address registers that map to memory space must return logic 0 in bit 0. Base Address registers that map to I/O space must return logic 1 in bit 0. The bit description of the BAR0 register is given in Table 17. Table 17. BAR0 - Base Address register 0 (address 10h) bit description Legend: * reset value Bit Symbol Access Value Description 31 to 0 BAR0[31:0] R/W 0000 0000h* Base Address to Memory-Mapped Host Controller Register Space: The memory size required by OHCI and EHCI are 4 kB and 256 bytes, respectively. Therefore, BAR0[31:12] is assigned to the two OHCI ports, and BAR0[31:8] is assigned to the EHCI port. 8.2.1.11 Subsystem Vendor ID register The Subsystem Vendor ID register is used to uniquely identify the expansion board or subsystem where the PCI device resides. This register allows expansion board vendors to distinguish their boards, even though the boards may have the same vendor ID and device ID. Subsystem vendor IDs are assigned by PCI-SIG to maintain uniqueness. The bit description of the Subsystem Vendor ID register is given in Table 18. Table 18. SVID - Subsystem Vendor ID register (address 2Ch) bit description Legend: * reset value Bit Symbol 15 to 0 SVID[15:0] R 8.2.1.12 Access Value Description 1131h* Subsystem Vendor ID: 1131h is the subsystem Vendor ID assigned to NXP Semiconductors. Subsystem ID register Subsystem ID values are vendor specific. The bit description of the Subsystem ID register is given in Table 19. ISP1562 ISP1562_2 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 02 - 1 March 2007 20 of 93 ISP1562 ISP1562 NXP Semiconductors HS USB PCI Host Controller Table 19. SID - Subsystem ID register (address 2Eh) bit description Legend: * reset value Bit Symbol 15 to 0 [1] Access Description R SID[15:0] Value X*[1] Subsystem ID: For the ISP1562 ISP1562, NXP Semiconductors has defined OHCI functions as 1561h, and the EHCI function as 1562h. X is 1561h for OHCI1 and OHCI2; X is 1562h for EHCI. 8.2.1.13 Capabilities Pointer register This register is used to point to a linked list of new capabilities implemented by the device. This register is only valid if CL (bit 4 in the Status register) is set. If implemented, bit 1 and bit 0 are reserved and must be set to 00b. Software must mask these bits off before using this register as a pointer in configuration space to the first entry of a linked list of new capabilities. The bit description of the register is given in Table 20. Table 20. CP - Capabilities Pointer register (address 34h) bit description Legend: * reset value Bit Symbol Access Value Description 7 to 0 CP[7:0] R DCh* Capabilities Pointer: EHCI efficiently manages power using this register. This Power Management register is allocated at offset DCh. Only one Host Controller is needed to manage power in the ISP1562 ISP1562. 8.2.1.14 Interrupt Line register This is a 1-byte register used to communicate interrupt line routing information. This register must be implemented by any device or device function that uses an interrupt pin. The interrupt allocation is done by the BIOS. The POST software needs to write the routing information to this register because it initializes and configures the system. The value in this register specifies which input of the system interrupt controller(s) the interrupt pin of the device is connected. This value is used by device drivers and operating systems to determine priority and vector information. Values in this register are system architecture specific. The bit description of the register is given in Table 21. Table 21. IL - Interrupt Line register (address 3Ch) bit description Legend: * reset value Bit Symbol Access Value Description 7 to 0 IL[7:0] R/W 00h* Interrupt Line: Indicates which IRQ is used to report interrupt from the ISP1562 ISP1562. 8.2.1.15 Interrupt Pin register This 1-byte register is use to specify which interrupt pin the device or device function uses. Devices or functions that do not use the interrupt pin must set this register to logic 0. The bit description is given in Table 22. Table 22. IP - Interrupt Pin register (address 3Dh) bit description Legend: * reset value Bit Symbol Access Value Description 7 to 0 IP[7:0] R 01h* Interrupt Pin: INTA# is the default interrupt pin used by the ISP1562 ISP1562. ISP1562 ISP1562_2 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 02 - 1 March 2007 21 of 93 ISP1562 ISP1562 NXP Semiconductors HS USB PCI Host Controller 8.2.1.16 MIN_GNT and MAX_LAT registers The Minimum Grant (MIN_GNT) and Maximum Latency (MAX_LAT) registers are used to specify the desired settings of the device for latency timer values. For both registers, the value specifies a period of time in units of 250 ns. Logic 0 indicates that the device has no major requirements for setting latency timers. The MIN_GNT register bit description is given in Table 23. Table 23. MIN_GNT - Minimum Grant register (address 3Eh) bit description Legend: * reset value Bit Symbol 7 to 0 [1] Access MIN_GNT[7:0] R Value Description X*[1] MIN_GNT: It is used to specify how long a burst period the device needs, assuming a clock rate of 33 MHz. X is 01h for OHCI1 and OHCI2; X is 02h for EHCI. The MAX_LAT register bit description is given in Table 24. Table 24. MAX_LAT - Maximum Latency register (address 3Fh) bit description Legend: * reset value Bit Symbol 7 to 0 [1] MAX_LAT[7:0] Access Value Description R X*[1] MAX_LAT: It is used to specify how often the device needs to gain access to the PCI bus. X is 2Ah for OHCI1 and OHCI2; X is 10h for EHCI. 8.2.1.17 TRDY _TIMEOUT - TRDY Timeout register This is a read and write register at address 40h. The default and recommended value is 00h, TRDY time-out disabled. This value can, however, be modified. It is an implementation-specific register, and not a standard PCI configuration register. The TRDY timer is 13 bits: the lower 5 bits are fixed as logic 0, and the upper 8 bits are determined by the TRDY Timeout register value. The time-out is calculated by multiplying the 13-bit timer with the PCICLK cycle time. This register determines the maximum TRDY delay, without asserting the UE (Unrecoverable Error) bit. If TRDY is longer than the delay determined by this register value, then the UE bit will be set. 8.2.1.18 RETRY_TIMEOUT - Retry Timeout register The default value of this read and write register is 80h, and is located at address 41h. This value can, however, be modified. Programming this register as 00h means that retry time-out is disabled. This is an implementation-specific register, and not a standard PCI configuration register. The time-out is determined by multiplying the register value with the PCICLK cycle time. This register determines the maximum number of PCI retires before the UE bit is set. If the number of retries is longer than the delay determined by this register value, then the UE bit will be set. ISP1562 ISP1562_2 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 02 - 1 March 2007 22 of 93 ISP1562 ISP1562 NXP Semiconductors HS USB PCI Host Controller 8.2.2 Enhanced Host Controller-specific PCI registers In addition to the PCI configuration header registers, EHCI needs some additional PCI configuration space registers to indicate the serial bus release number, downstream port wake-up event capability, and adjust the USB bus frame length for Start-of-Frame (SOF). The EHCI-specific PCI registers are given in Table 25. Table 25. EHCI-specific PCI registers Offset 60h Serial Bus Release Number (SBRN) 61h Frame Length Adjustment (FLADJ) 62h to 63h 8.2.2.1 Register Port Wake Capability (PORTWAKECAP) SBRN register The Serial Bus Release Number (SBRN) register is a 1-byte register, and the bit description is given in Table 26. This register contains the release number of the USB specification with which this USB Host Controller module is compliant. Table 26. SBRN - Serial Bus Release Number register (address 60h) bit description Legend: * reset value Bit Symbol Access Value Description 7 to 0 SBRN[7:0] R 20h* Serial Bus Specification Release Number: This register value is to identify Universal Serial Bus Specification Rev. 2.0. All other combinations are reserved. 8.2.2.2 FLADJ register This feature is used to adjust any offset from the clock source that generates the clock that drives the SOF counter. When a new value is written to these six bits, the length of the frame is adjusted. The bit allocation of the Frame Length Adjustment (FLADJ) register is given in Table 27. Table 27. FLADJ - Frame Length Adjustment register (address 61h) bit allocation Bit 7 6 5 4 3 0 0 1 0 R/W R/W R/W R/W Symbol Reset Access [1] 2 1 0 0 0 0 0 R/W R/W R/W R/W reserved[1] FLADJ[5:0] The reserved bits should always be written with the reset value. Table 28. FLADJ - Frame Length Adjustment register (address 61h) bit description Bit Symbol Description 7 to 6 reserved - 5 to 0 FLADJ[5:0] Frame Length Timing Value: Each decimal value change to this register corresponds to 16 high-speed bit times. The SOF cycle time, number of SOF counter clock periods to generate a SOF microframe length, is equal to 59488 + value in this field. The default value is decimal 32 (20h), which gives a SOF cycle time of 60000; see Table 29. ISP1562 ISP1562_2 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 02 - 1 March 2007 23 of 93 ISP1562 ISP1562 NXP Semiconductors HS USB PCI Host Controller Table 29. FLADJ value as a function of SOF cycle time FLADJ value 0 (00h) 59488 1 (01h) 59504 2 (02h) 59520 : : 31 (1Fh) 59984 32 (20h) 60000 : : 62 (3Eh) 60480 63 (3Fh) 8.2.2.3 SOF cycle time (480 MHz) 60496 PORTWAKECAP register Port Wake Capability (PORTWAKECAP) is a 2-byte register used to establish a policy about which ports are for wake events; see Table 30. Bit positions 15 to 1 in the mask correspond to a physical port implemented on the current EHCI controller. Logic 1 in a bit position indicates that a device connected below the port can be enabled as a wake-up device and the port may be enabled for disconnect or connect, or overcurrent events as wake-up events. This is an information only mask register. The bits in this register do not affect the actual operation of the EHCI Host Controller. The system-specific policy can be established by BIOS initializing this register to a system-specific value. The system software uses the information in this register when enabling devices and ports for remote wake-up. Table 30. PORTWAKECAP - Port Wake Capability register (address 62h) bit description Legend: * reset value Bit Symbol 15 to 0 PORTWAKE CAP[15:0] Access Value Description R/W 0007h* Port Wake-Up Capability Mask: EHCI does not implement this feature. 8.2.3 Power management registers Table 31. Power Management registers Offset Value read from address 34h + 0h Capability Identifier (CAP_ID) Value read from address 34h + 1h Next Item Pointer (NEXT_ITEM_PTR) Value read from address 34h + 2h Power Management Capabilities (PMC) Value read from address 34h + 4h Power Management Control/Status (PMCSR) Value read from address 34h + 6h Power Management Control/Status PCI-to-PCI Bridge Support Extensions (PMCSR_BSE) Value read from address 34h + 7h 8.2.3.1 Register Data CAP_ID register The Capability Identifier (CAP_ID) register when read by the system software as 01h indicates that the data structure currently being pointed to is the PCI power management data structure. Each function of a PCI device may have only one item in its capability list with CAP_ID set to 01h. The bit description of the register is given in Table 32. ISP1562 ISP1562_2 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 02 - 1 March 2007 24 of 93 ISP1562 ISP1562 NXP Semiconductors HS USB PCI Host Controller Table 32. CAP_ID - Capability Identifier register bit description Address: Value read from address 34h + 0h Legend: * reset value Bit Symbol Access Value Description 7 to 0 CAP_ID[7:0] R 01h* ID: This field when 01h identifies the linked list item as being PCI Power Management registers. 8.2.3.2 NEXT_ITEM_PTR register The Next Item Pointer (NEXT_ITEM_PTR) register describes the location of the next item in the function's capability list. The value given is an offset into the function's PCI configuration space. If the function does not implement any other capabilities defined by the PCI-SIG for inclusion in the capabilities list, or if power management is the last item in the list, then this register must be set to 00h. See Table 33. Table 33. NEXT_ITEM_PTR - Next Item Pointer register bit description Address: Value read from address 34h + 1h Legend: * reset value Bit Symbol Access Value Description 7 to 0 NEXT_ITEM_ PTR[7:0] R 00h* Next Item Pointer: This field provides an offset into the function's PCI configuration space, pointing to the location of the next item in the function's capability list. If there are no additional items in the capabilities list, this register is set to 00h. 8.2.3.3 PMC register The Power Management Capabilities (PMC) register is a 2-byte register, and the bit allocation is given in Table 34. This register provides information on the capabilities of the function related to power management. Table 34. PMC - Power Management Capabilities register bit allocation Address: Value read from address 34h + 2h Bit 15 14 Symbol 13 12 11 1 X[1] 9 8 D2_S PME_S[4:0] 10 D1_S AUX_C X[1] 1 0 Reset 1 1 X[1] Access R R R R R R R R Bit 7 6 5 4 3 2 1 0 DSI reserved PMI Symbol AUX_C[1:0] VER[2:0] Reset 1 0 0 0 0 0 1 0 Access R R R R R R R R [1] X is 0 for OHCI1 and OHCI2; X is 1 for EHCI. ISP1562 ISP1562_2 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 02 - 1 March 2007 25 of 93 ISP1562 ISP1562 NXP Semiconductors HS USB PCI Host Controller Table 35. PMC - Power Management Capabilities register bit description Address: Value read from address 34h + 2h Bit Symbol Description 15 to 11 PME_S [4:0] PME Support: These bits indicate the power states in which the function may assert PME#. Logic 0 for any bit indicates that the function is not capable of asserting the PME# signal while in that power state. PME_S[0] - PME# can be asserted from D0 PME_S[1] - PME# can be asserted from D1 PME_S[2] - PME# can be asserted from D2 PME_S[3] - PME# can be asserted from D3hot PME_S[4] - PME# can be asserted from D3cold 10 D2_S D2_Support: If this bit is logic 1, this function supports the D2 power management state. Functions that do not support D2 must always return logic 0 for this bit. 9 D1_S D1_Support: If this bit is logic 1, this function supports the D1 power management state. Functions that do not support D1 must always return logic 0 for this bit. 8 to 6 AUX_C [2:0] Auxiliary Current: This three-bit field reports the Vaux(3V3) auxiliary current requirements for the PCI function. If the Data register is implemented by this function: · · A read from this field needs to return a value of 000b. The Data register takes precedence over this field for Vaux(3V3) current requirement reporting. If the PME# generation from D3cold is not supported by the function (PMC[15] = 0), this field must return a value of 000b when read. For functions that support PME# from D3cold and do not implement the Data register, bit assignments corresponding to the maximum current required for Vaux(3V3) are: 111b - 375 mA 110b - 320 mA 101b - 270 mA 100b - 220 mA 011b - 160 mA 010b - 100 mA 001b - 55 mA 000b - 0 (self-powered) 5 DSI Device Specific Initialization: This bit indicates whether special initialization of this function is required, beyond the standard PCI configuration header, before the generic class device driver can use it. This bit is not used by some operating systems. For example, Microsoft Windows and Windows NT do not use this bit to determine whether to use D3. Instead, it is determined using the capabilities of the driver. Logic 1 indicates that the function requires a device-specific initialization sequence, following transition to D0 uninitialized state. 4 reserved - 3 PMI PME Clock: 0 - Indicates that no PCI clock is required for the function to generate PME#. 1 - Indicates that the function relies on the presence of the PCI clock for the PME# operation. Functions that do not support the PME# generation in any state must return logic 0 for this field. 2 to 0 VER[2:0] Version: A value of 010b indicates that this function complies with PCI Bus Power Management Interface Specification Rev. 1.1. ISP1562 ISP1562_2 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 02 - 1 March 2007 26 of 93 ISP1562 ISP1562 NXP Semiconductors HS USB PCI Host Controller 8.2.3.4 PMCSR register The Power Management Control/Status (PMCSR) register is a 2-byte register used to manage the power management state of the PCI function, as well as to allow and monitor Power Management Events (PMEs). The bit allocation of the register is given in Table 36. Table 36. PMCSR - Power Management Control/Status register bit allocation Address: Value read from address 34h + 4h Bit 15 Symbol 14 PMES 13 12 11 DS[1:0] 10 9 8 D_S[3:0] PMEE Reset X[1] 0 0 0 0 0 0 X[1] Access R/W R R R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 Bit reserved[2] Symbol Reset PS[1:0] 0 0 0 0 0 0 0 R/W Access 0 R/W R/W R/W R/W R/W R/W R/W [1] Sticky bit, if the function supports PME# from D3cold, then X is indeterminate at the time of initial operating system boot; X is 0 if the function does not support PME# from D3cold. [2] The reserved bits should always be written with the reset value. Table 37. PMCSR - Power Management Control/Status register bit description Address: Value read from address 34h + 4h Bit Symbol Description 15 PMES PME Status: This bit is set when the function normally asserts the PME# signal independent of the state of the PMEE bit. Writing logic 1 to this bit clears it and causes the function to stop asserting PME#, if enabled. Writing logic 0 has no effect. This bit defaults to logic 0, if the function does not support the PME# generation from D3cold. If the function supports the PME# generation from D3cold, then this bit is sticky and must be explicitly cleared by the operating system each time the operating system is initially loaded. 14 to 13 DS[1:0] Data Scale: This two-bit read-only field indicates the scaling factor when interpreting the value of the Data register. The value and meaning of this field vary, depending on which data value is selected by the D_S field. This field is a required component of the Data register (offset 7) and must be implemented, if the Data register is implemented. If the Data register is not implemented, this field must return 00b when PMCSR is read. 12 to 9 D_S [3:0] Data Select: This four-bit field selects the data that is reported through the Data register and the D_S field. This field is a required component of the Data register (offset 7) and must be implemented, if the Data register is implemented. If the Data register is not implemented, this field must return 00b when PMCSR is read. 8 PMEE PME Enabled: Logic 1 allows the function to assert PME#. When it is logic 0, PME# assertion is disabled. This bit defaults to logic 0, if the function does not support the PME# generation from D3cold. If the function supports PME# from D3cold, then this bit is sticky and must be explicitly cleared by the operating system each time the operating system is initially loaded. 7 to 2 reserved - ISP1562 ISP1562_2 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 02 - 1 March 2007 27 of 93 ISP1562 ISP1562 NXP Semiconductors HS USB PCI Host Controller Table 37. PMCSR - Power Management Control/Status register bit description .continued Address: Value read from address 34h + 4h Bit Symbol Description 1 to 0 PS[1:0] Power State: This two-bit field is used to determine the current power state of the EHCI function and to set the function into a new power state. The definition of the field values is given as: 00b - D0 01b - D1 10b - D2 11b - D3hot If the software attempts to write an unsupported, optional state to this field, the write operation must complete normally on the bus; however, data is discarded and no status change occurs. 8.2.3.5 PMCSR_BSE register The PMCSR PCI-to-PCI Bridge Support Extensions (PMCSR_BSE) register supports PCI bridge-specific functionality and is required for all PCI-to-PCI bridges. The bit allocation of this register is given in Table 38. Table 38. PMCSR_BSE - PMCSR PCI-to-PCI Bridge Support Extensions register bit allocation Address: Value read from address 34h + 6h Bit Symbol 7 6 5 4 3 2 1 0 BPCC_EN B2_B3# Reset 0 0 0 0 0 reserved 0 0 0 Access R R R R R R R R Table 39. PMCSR_BSE - PMCSR PCI-to-PCI Bridge Support Extensions register bit description Address: Value read from address 34h + 6h Bit Symbol Description 7 BPCC_EN Bus Power/Clock Control Enable: 1 - Indicates that the bus power or clock control mechanism as defined in Table 40 is enabled. 0 - Indicates that the bus or power control policies as defined in Table 40 are disabled. When the bus power or clock control mechanism is disabled, the bridge's PMCSR Power State (PS) field cannot be used by the system software to control the power or clock of the bridge's secondary bus. 6 B2_B3# B2/B3 support for D3hot: The state of this bit determines the action that is to occur as a direct result of programming the function to D3hot. 1 - Indicates that when the bridge function is programmed to D3hot, its secondary bus's PCI clock will be stopped (B2). 0 - Indicates that when the bridge function is programmed to D3hot, its secondary bus will have its power removed (B3). This bit is only meaningful if bit 7 (BPCC_EN) is logic 1. 5 to 0 reserved Table 40. PCI bus power and clock control Originating device's Secondary bus bridge PM state PM state Resultant actions by bridge (either direct or indirect) D0 B0 none D1 B1 none ISP1562 ISP1562_2 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 02 - 1 March 2007 28 of 93 ISP1562 ISP1562 NXP Semiconductors HS USB PCI Host Controller Table 40. PCI bus power and clock control .continued Originating device's Secondary bus bridge PM state PM state D2 B2 clock stopped on secondary bus D3hot B2, B3 clock stopped and PCI VCC removed from secondary bus (B3 only); for definition of B2_B3#, see Table 39. D3cold 8.2.3.6 Resultant actions by bridge (either direct or indirect) B3 none Data register The Data register is an optional, 1-byte register that provides a mechanism for the function to report state dependent operating data, such as power consumed or heat dissipated. Table 41 shows the bit description of the register. Table 41. DATA - Data register bit description Address: Value read from address 34h + 7h Legend: * reset value Bit Symbol Access Value Description 7 to 0 DATA[7:0] R 00h* DATA: This register is used to report the state dependent data requested by the D_S field of the PMCSR register. The value of this register is scaled by the value reported by the DS field of the PMCSR register. ISP1562 ISP1562_2 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 02 - 1 March 2007 29 of 93 ISP1562 ISP1562 NXP Semiconductors HS USB PCI Host Controller 9. I2C-bus interface A simple I2C-bus interface is provided in the ISP1562 ISP1562 to read customized vendor ID, product ID and some other configuration bits from an external EEPROM. The I2C-bus interface is for bidirectional communication between ICs using two serial bus wires: SDA (data) and SCL (clock). Both lines are driven by open-drain circuits and must be connected to the positive supply voltage through pull-up resistors when in use; otherwise, they must be connected to ground. 9.1 Protocol The I2C-bus protocol defines the following conditions: · · · · Bus free: both SDA and SCL are HIGH START: a HIGH-to-LOW transition on SDA, while SCL is HIGH STOP: a LOW-to-HIGH transition on SDA, while SCL is HIGH Data valid: after a START condition, data on SDA is stable during the HIGH period of SCL; data on SDA may only change while SCL is LOW Each device on the I2C-bus has a unique slave address, which the master uses to select a device for access. The master starts a data transfer using a START condition and ends it by generating a STOP condition. Transfers can only be initiated when the bus is free. The receiver must acknowledge each byte by using a LOW level on SDA during the ninth clock pulse on SCL. For detailed information, refer to The I2C-bus Specification Version 2.1. 9.2 Hardware connections The ISP1562 ISP1562 can be connected to an external EEPROM through the I2C-bus interface. The hardware connections are shown in Figure 5. Vaux(3V3) Vaux(3V3) RP SCL A0 SDA SCL SDA RP A1 I2C-bus 24C01 24C01 ISP1562 ISP1562 USB HOST A2 EEPROM or equivalent 004aaa509 Fig 5. EEPROM connection diagram ISP1562 ISP1562_2 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 02 - 1 March 2007 30 of 93 ISP1562 ISP1562 NXP Semiconductors HS USB PCI Host Controller The slave address that the ISP1562 ISP1562 uses to access the EEPROM is 101 0000b. Page mode addressing is not supported. Therefore, pins A0, A1 and A2 of the EEPROM must be connected to ground (logic 0). 9.3 Information loading from EEPROM Figure 6 shows the content of the EEPROM memory. If the EEPROM is not present, the default values of device ID, vendor ID, subsystem VID and subsystem DID assigned to NXP Semiconductors by PCI-SIG will be loaded. For default values, see Table 3. address 0 subsystem vendor ID (L) 1 subsystem vendor ID (H) 2 subsystem device ID (L) - OHCI 3 subsystem device ID (H) - OHCI 4 subsystem device ID (L) - EHCI 5 subsystem device ID (H) - EHCI 6 reserved - FFh 7 signature 15h - loads subsystem vendor ID, device ID 1Ah - loads default values defined by NXP Semiconductors 004aaa930 L = LOW; H = HIGH. Fig 6. Information loading from EEPROM 10. Power management 10.1 PCI bus power states The PCI bus can be characterized by one of the four power management states: B0, B1, B2 and B3. B0 state (PCI clock = 33 MHz, PCI bus power = on) - This corresponds to the bus being fully operational. B1 state (PCI clock = intermittent clock operation mode, PCI bus power = on) - When a PCI bus is in B1, PCI VCC is still applied to all devices on the bus. No bus transactions, however, are allowed to take place on the bus. The B1 state indicates a perpetual idle state on the PCI bus. B2 state (PCI clock = stop, PCI bus power = on) - PCI VCC is still applied on the bus, but the clock is stopped and held in the LOW state. B3 state (PCI clock = stop, PCI bus power = off) - PCI VCC is removed from all devices on the PCI bus segment. ISP1562 ISP1562_2 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 02 - 1 March 2007 31 of 93 ISP1562 ISP1562 NXP Semiconductors HS USB PCI Host Controller 10.2 USB bus states Reset state - When the USB bus is in the reset state, the USB system is stopped. Operational state - When the USB bus is in the active state, the USB system is operating normally. Suspend state - When the USB bus is in the suspend state, the USB system is stopped. Resume state - When the USB bus is in the resume state, the USB system is operating normally. 11. USB Host Controller registers Each Host Controller contains a set of on-chip operational registers that are mapped to uncached memory of the system addressable space. This memory space must begin on a DWORD (32-bit) boundary. The size of the allocated space is defined by the initial value in the Base Address register 0. HCDs must interact with these registers to implement USB functionality. After the PCI enumeration driver finishes the PCI device configuration, the new base address of these memory-mapped operational registers is defined in BAR0. The HCD can access these registers by using the address of base address value + offset. Table 42 contains a list of Host Controller registers. Table 42. USB Host Controller registers Address OHCI register Reset value[1] EHCI register Func0 OHCI1 Func1 OHCI2 Reset value[1] Func2 EHCI 00h HcRevision 0000 0010h 0000 0010h CAPLENGTH/HCIVERSION 0100 0020h 04h HcControl 0000 0000h 0000 0000h HCSPARAMS 0000 2192h 08h HcCommandStatus 0000 0000h 0000 0000h HCCPARAMS 0000 0012h 0Ch HcInterruptStatus 0000 0000h 0000 0000h HCSP-PORTROUTE1[31:0] 0000 0010h 10h HcInterruptEnable 0000 0000h 0000 0000h HCSP-PORTROUTE2[59:32] 0000 0000h 14h HcInterruptDisable 0000 0000h 0000 0000h reserved - 18h HcHCCA 0000 0000h 0000 0000h reserved - 1Ch HcPeriodCurrentED 0000 0000h 0000 0000h reserved - 20h HcControlHeadED 0000 0000h 0000 0000h USBCMD 0008 0000h 24h HcControlCurrentED 0000 0000h 0000 0000h USBSTS 0000 1000h 28h HcBulkHeadED 0000 0000h 0000 0000h USBINTR 0000 0000h 2Ch HcBulkCurrentED 0000 0000h 0000 0000h FRINDEX 0000 0000h 30h HcDoneHead 0000 0000h 0000 0000h reserved - 34h HcFmInterval 0000 2EDFh 0000 2EDFh PERIODICLISTBASE 0000 0000h 38h HcFmRemaining 0000 0000h 0000 0000h ASYNCLISTADDR 0000 0000h 3Ch HcFmNumber 0000 0000h 0000 0000h reserved - 40h HcPeriodicStart 0000 0000h 0000 0000h reserved - 44h HcLSThreshold 0000 0628h 0000 0628h reserved - 48h HcRhDescriptorA FF00 0901h FF00 0901h reserved - ISP1562 ISP1562_2 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 02 - 1 March 2007 32 of 93 ISP1562 ISP1562 NXP Semiconductors HS USB PCI Host Controller Table 42. USB Host Controller registers .continued Address OHCI register Reset value[1] Reset value[1] EHCI register Func0 OHCI1 Func1 OHCI2 Func2 EHCI 4Ch 0002 0000h 0002 0000h reserved - 50h HcRhStatus 0000 0000h 0000 0000h reserved - 54h HcRhPortStatus[1] 0000 0000h 0000 0000h reserved - 58h HcRhPortStatus[2] - - reserved - 5Ch reserved - - reserved - 60h reserved - - CONFIGFLAG 0000 0000h 64h reserved - - PORTSC1 0000 0000h 68h reserved - - PORTSC2 0000 0000h 6Ch reserved - - reserved - 70h [1] HcRhDescriptorB reserved - - reserved - Reset values that are highlighted, for example, 0, are the ISP1562 ISP1562 implementation-specific reset values; and reset values that are not highlighted, for example, 0, are compliant with OHCI and EHCI specifications. For the OHCI Host Controller, there are only operational registers for the USB operation. For the enhanced Host Controller, there are two types of registers: one set of read-only capability registers and one set of read and write operational registers. 11.1 OHCI USB Host Controller operational registers OHCI HCDs must communicate with these registers to implement USB data transfers. Based on their functions, these registers are classified into four partitions: · · · · Control and status Memory pointer Frame counter Root hub 11.1.1 HcRevision register Table 43. HcRevision - Host Controller Revision register bit allocation Address: Content of the base address register + 00h Bit 31 30 29 28 Symbol Reset 27 26 25 24 0 0 0 0 reserved 0 0 0 0 Access R R R R R R R R Bit 23 22 21 20 19 18 17 16 0 0 0 0 Symbol Reset reserved 0 0 0 0 Access R R R R R R R R Bit 15 14 13 12 11 10 9 8 Symbol reserved Reset 0 0 0 0 0 0 0 0 Access R R R R R R R R ISP1562 ISP1562_2 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 02 - 1 March 2007 33 of 93 ISP1562 ISP1562 NXP Semiconductors HS USB PCI Host Controller Bit 7 6 5 4 3 2 1 0 Reset 0 0 0 1 0 0 0 0 Access R R R R R R R R Symbol REV[7:0] Table 44. HcRevision - Host Controller Revision register bit description Address: Content of the base address register + 00h Bit Symbol Description 31 to 8 reserved - 7 to 0 REV[7:0] Revision: This read-only field contains the BCD representation of the version of the HCI specification that is implemented by this Host Controller. For example, a value of 11h corresponds to version 1.1. All Host Controller implementations that are compliant with this specification must have a value of 10h. 11.1.2 HcControl register This register defines the operating modes for the Host Controller. All the fields in this register, except for HCFS and RWC, are modified only by the HCD. The bit allocation is given in Table 45. Table 45. HcControl - Host Controller Control register bit allocation Address: Content of the base address register + 04h Bit 31 30 29 28 Reset 26 25 24 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W 23 Bit 0 R/W Access 22 21 20 19 18 17 16 reserved[1] Symbol Reset 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W 15 Bit 0 R/W Access 14 13 12 11 Reset 10 9 8 RWE reserved[1] Symbol RWC IR 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 7 Access 6 1 0 Bit Symbol 5 4 3 2 BLE HCFS[1:0] Reset CLE IE PLE CBSR[1:0] 0 0 0 0 0 0 0 0 R/W Access [1] 27 reserved[1] Symbol R/W R/W R/W R/W R/W R/W R/W The reserved bits should always be written with the reset value. Table 46. HcControl - Host Controller Control register bit description Address: Content of the base address register + 04h Bit Symbol Description 31 to 11 reserved - 10 RWE Remote Wake-up Enable: This bit is used by the HCD to enable or disable the remote wake-up feature on detecting upstream resume signaling. When this bit and RD (bit 3) in the HcInterruptStatus register are set, a remote wake-up is signaled to the host system. Setting this bit has no impact on the generation of hardware interrupt. ISP1562 ISP1562_2 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 02 - 1 March 2007 34 of 93 ISP1562 ISP1562 NXP Semiconductors HS USB PCI Host Controller Table 46. HcControl - Host Controller Control register bit description .continued Address: Content of the base address register + 04h Bit Symbol Description 9 RWC Remote Wake-up Connected: This bit indicates whether the Host Controller supports remote wake-up signaling. If remote wake-up is supported and used by the system, it is the responsibility of the system firmware to set this bit during POST. The Host Controller clears the bit on a hardware reset but does not alter it on a software reset. Remote wake-up signaling of the host system is host-bus-specific and is not described in this specification. 8 IR Interrupt Routing: This bit determines the routing of interrupts generated by events registered in HcInterruptStatus. If clear, all interrupts are routed to the normal host bus interrupt mechanism. If set, interrupts are routed to the system management interrupt. The HCD clears this bit on a hardware reset, but it does not alter this bit on a software reset. The HCD uses this bit as a tag to indicate the ownership of the Host Controller. 7 to 6 HCFS [1:0] Host Controller Functional State for USB: 00b - USBRESET 01b - USBRESUME 10b - USBOPERATIONAL 11b - USBSUSPEND A transition to USBOPERATIONAL from another state causes SOF generation to begin 1 ms later. The HCD may determine whether the Host Controller has begun sending SOFs by reading SF (bit 2) in HcInterruptStatus. This field may be changed by the Host Controller only when in the USBSUSPEND state. The Host Controller may move from the USBSUSPEND state to the USBRESUME state after detecting the resume signaling from a downstream port. The Host Controller enters USBSUSPEND after a software reset; it enters USBRESET after a hardware reset. The latter also resets the root hub and asserts subsequent reset signaling to downstream ports. 5 BLE Bulk List Enable: This bit is set to enable the processing of the bulk list in the next frame. If cleared by the HCD, processing of the bulk list does not occur after the next SOF. The Host Controller checks this bit whenever it wants to process the list. When disabled, the HCD may modify the list. If HcBulkCurrentED is pointing to an Endpoint Descriptor (ED) to be removed, the HCD must advance the pointer by updating HcBulkCurrentED before re-enabling processing of the list. 4 CLE Control List Enable: This bit is set to enable the processing of the control list in the next frame. If cleared by the HCD, processing of the control list does not occur after the next SOF. The Host Controller must check this bit whenever it wants to process the list. When disabled, the HCD may modify the list. If HcControlCurrentED is pointing to an ED to be removed, the HCD must advance the pointer by updating HcControlCurrentED before re-enabling processing of the list. 3 IE Isochronous Enable: This bit is used by the HCD to enable or disable processing of isochronous EDs. While processing the periodic list in a frame, the Host Controller checks the status of this bit when it finds an isochronous ED (that is, the Format bit of ED is logic 1; for details, refer to Open Host Controller Interface Specification for USB Rev. 1.0a). If set (enabled), the Host Controller continues processing the EDs. If cleared (disabled), the Host Controller halts processing of the periodic list, which now contains only isochronous EDs, and begins processing the bulk or control lists. Setting this bit is guaranteed to take effect in the next frame and not the current frame. 2 PLE Periodic List Enable: This bit is set to enable the processing of the periodic list in the next frame. If cleared by the HCD, processing of the periodic list does not occur after the next SOF. The Host Controller must check this bit before it starts processing the list. ISP1562 ISP1562_2 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 02 - 1 March 2007 35 of 93 ISP1562 ISP1562 NXP Semiconductors HS USB PCI Host Controller Table 46. HcControl - Host Controller Control register bit description .continued Address: Content of the base address register + 04h Bit Symbol Description 1 to 0 CBSR [1:0] Control Bulk Service Ratio: This specifies the service ratio of control EDs over bulk EDs. Before processing any of the nonperiodic lists, the Host Controller must compare the ratio specified with its internal count on how many nonempty control EDs are processed, in determining whether to continue serving another control ED or switching to bulk EDs. The internal count must be retained when crossing the frame boundary. After a reset, the HCD is responsible to restore this value. 00b - 1 : 1 01b - 2 : 1 10b - 3 : 1 11b - 4 : 1 11.1.3 HcCommandStatus register This register is used by the Host Controller to receive commands issued by the HCD. It also reflects the current status of the Host Controller. To the HCD, it appears as a `write to set' register. The Host Controller must ensure that bits written as logic 1 become set in the register while bits written as logic 0 remain unchanged in the register. The HCD may issue multiple distinct commands to the Host Controller without concern for corrupting previously issued commands. The HCD has normal read access to all bits. The SOC[1:0] field (bits 17 and 16 in the HcCommandStatus register) indicates the number of frames with which the Host Controller has detected the scheduling overrun error. This occurs when the periodic list does not complete before EOF. When a scheduling overrun error is detected, the Host Controller increments the counter and sets SO (bit 0 in the HcInterruptStatus register). Table 47 shows the bit allocation of the HcCommandStatus register. Table 47. HcCommandStatus - Host Controller Command Status register bit allocation Address: Content of the base address register + 08h Bit 31 30 29 28 Symbol Reset 26 25 24 Bit 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 23 Access 22 21 20 19 18 17 16 reserved[1] Symbol Reset SOC[1:0] Bit 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 15 Access 14 13 12 11 10 9 8 reserved[1] Symbol Reset Bit 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 7 Access 6 5 4 3 2 1 0 reserved[1] OCR BLF CLF HCR 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Symbol Reset Access [1] 27 reserved[1] The reserved bits should always be written with the reset value. ISP1562 ISP1562_2 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 02 - 1 March 2007 36 of 93 ISP1562 ISP1562 NXP Semiconductors HS USB PCI Host Controller Table 48. HcCommandStatus - Host Controller Command Status register bit description Address: Content of the base address register + 08h Bit Symbol Description 31 to 18 reserved - 17 to 16 SOC[1:0] Scheduling Overrun Count: The bit is incremented on each scheduling overrun error. It is initialized to 00b and wraps around at 11b. It must be incremented when a scheduling overrun is detected, even if SO (bit 0 in HcInterruptStatus) is already set. This is used by the HCD to monitor any persistent scheduling problems. 15 to 4 reserved - 3 OCR Ownership Change Request: This bit is set by an OS HCD to request a change of control of the Host Controller. When set, the Host Controller must set OC (bit 30 in HcInterruptStatus). After the changeover, this bit is cleared and remains so until the next request from the OS HCD. 2 BLF Bulk List Filled: This bit is used to indicate whether there are any Transfer Descriptors (TDs) on the bulk list. It is set by the HCD whenever it adds a TD to an ED in the bulk list. When the Host Controller begins to process the head of the bulk list, it checks Bulk-Filled (BF). If BLF is logic 0, the Host Controller does not need to process the bulk list. If BLF is logic 1, the Host Controller must start processing the bulk list and set BF to logic 0. If the Host Controller finds a TD on the list, then the Host Controller must set BLF to logic 1, causing the bulk list processing to continue. If no TD is found on the bulk list, and if the HCD does not set BLF, then BLF is still logic 0 when the Host Controller completes processing the bulk list and the bulk list processing stops. 1 CLF Control List Filled: This bit is used to indicate whether there are any TDs on the control list. It is set by the HCD whenever it adds a TD to an ED in the control list. When the Host Controller begins to process the head of the control list, it checks CLF. If CLF is logic 0, the Host Controller does not need to process the control list. If Control-Filled (CF) is logic 1, the Host Controller needs to start processing the control list and set CLF to logic 0. If the Host Controller finds a TD on the list, then the Host Controller must set CLF to logic 1, causing the control list processing to continue. If no TD is found on the control list, and if the HCD does not set CLF, then CLF is still logic 0 when the Host Controller completes processing the control list and the control list processing stops. 0 HCR Host Controller Reset: This bit is set by the HCD to initiate a software reset of the Host Controller. Regardless of the functional state of the Host Controller, it moves to the USBSUSPEND state in which most of the operational registers are reset, except those stated otherwise; for example, IR (bit 8) in the HcControl register, and no host bus accesses are allowed. This bit is cleared by the Host Controller on completing the reset operation. The reset operation must be completed within 10 µs. This bit, when set, must not cause a reset to the root hub and no subsequent reset signaling must be asserted to its downstream ports. 11.1.4 HcInterruptStatus register This is a 4-byte register that provides the status of the events that cause hardware interrupts. The bit allocation of the register is given in Table 49. When an event occurs, the Host Controller sets the corresponding bit in this register. When a bit becomes set, a hardware interrupt is generated, if the interrupt is enabled in the HcInterruptEnable register (see Table 51) and the MIE (Master Interrupt Enable) bit is set. The HCD may clear specific bits in this register by writing logic 1 to the bit positions to be cleared. The HCD may not set any of these bits. The Host Controller does not clear the bit. Table 49. HcInterruptStatus - Host Controller Interrupt Status register bit allocation Address: Content of the base address register + 0Ch Bit Symbol 31 reserved[1] Reset Access 30 29 28 26 25 24 reserved[1] OC 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W ISP1562 ISP1562_2 Product data sheet 27 © NXP B.V. 2007. All rights reserved. Rev. 02 - 1 March 2007 37 of 93 ISP1562 ISP1562 NXP Semiconductors HS USB PCI Host Controller Bit 23 22 21 20 Symbol Reset 18 17 16 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 15 Access 14 13 12 11 10 9 8 Bit reserved[1] Symbol Reset 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 reserved[1] RHSC FNO UE RD SF WDH SO 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Access Bit Symbol Reset Access [1] 19 reserved[1] The reserved bits should always be written with the reset value. Table 50. HcInterruptStatus - Host Controller Interrupt Status register bit description Address: Content of the base address register + 0Ch Bit Symbol Description 31 reserved - 30 OC Ownership Change: This bit is set by the Host Controller when HCD sets OCR (bit 3) in the HcCommandStatus register. This event, when unmasked, will always immediately generate a System Management Interrupt (SMI). This bit is forced to logic 0 when the SMI# pin is not implemented. 29 to 7 reserved - 6 RHSC Root Hub Status Change: This bit is set when the content of HcRhStatus or the content of any of HcRhPortStatus[NumberofDownstreamPort] has changed. 5 FNO Frame Number Overflow: This bit is set when the Most Significant Bit (MSB) of HcFmNumber (bit 15) changes value, or after the HccaFrameNumber is updated. 4 UE Unrecoverable Error: This bit is set when the Host Controller detects a system error not related to USB. The Host Controller must not proceed with any processing nor signaling before the system error is corrected. The HCD clears this bit after the Host Controller is reset. 3 RD Resume Detected: This bit is set when the Host Controller detects that a device on the USB is asserting resume signaling. This bit is set by the transition from no resume signaling to resume signaling. This bit is not set when the HCD sets the USBRESUME state. 2 SF Start-of-Frame: At the start of each frame, this bit is set by the Host Controller and an SOF token is generated at the same time. 1 WDH Write-back Done Head: This bit is immediately set after the Host Controller has written HcDoneHead to HccaDoneHead. Further, updates of HccaDoneHead occur only after this bit is cleared. The HCD must only clear this bit after it has saved the content of HccaDoneHead. 0 SO Scheduling Overrun: This bit is set when USB schedules for current frame overruns and after the update of HccaFrameNumber. A scheduling overrun increments the SOC[1:0] field (bits 17 to 16 of HcCommandStatus). 11.1.5 HcInterruptEnable register Each enable bit in the HcInterruptEnable register corresponds to an associated interrupt bit in the HcInterruptStatus register. The HcInterruptEnable register is used to control which events generate a hardware interrupt. A hardware interrupt is requested on the host bus if the following conditions occur: ISP1562 ISP1562_2 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 02 - 1 March 2007 38 of 93 ISP1562 ISP1562 NXP Semiconductors HS USB PCI Host Controller · A bit is set in the HcInterruptStatus register. · The corresponding bit in the HcInterruptEnable register is set. · The MIE (Master Interrupt Enable) bit is set. Writing logic 1 to a bit in this register sets the corresponding bit, whereas writing logic 0 to a bit in this register leaves the corresponding bit unchanged. On a read, the current value of this register is returned. The bit allocation is given in Table 51. Table 51. HcInterruptEnable - Host Controller Interrupt Enable register bit allocation Address: Content of the base address register + 10h Bit 31 30 MIE OC 0 0 0 0 R/W R/W R/W 23 Symbol 22 21 Reset Access Bit 29 28 26 25 24 0 0 0 0 R/W R/W R/W R/W R/W 20 19 18 17 16 reserved[1] reserved[1] Symbol Reset 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 15 Access 14 13 12 11 10 9 8 Bit reserved[1] Symbol Reset 0 0 0 0 0 0 0 0 R/W Access R/W R/W R/W R/W R/W R/W R/W Bit 7 6 5 4 3 2 1 0 reserved[1] RHSC FNO UE RD SF WDH SO 0 0 0 0 0 0 0 0 R/W Symbol R/W R/W R/W R/W R/W R/W R/W Reset Access [1] 27 The reserved bits should always be written with the reset value. Table 52. HcInterruptEnable - Host Controller Interrupt Enable register bit description Address: Content of the base address register + 10h Bit Symbol Description 31 MIE Master Interrupt Enable: 0 - Ignore 1 - Enables interrupt generation by events specified in other bits of this register. 30 OC Ownership Change: 0 - Ignore 1 - Enables interrupt generation because of ownership change. 29 to 7 reserved - ISP1562 ISP1562_2 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 02 - 1 March 2007 39 of 93 ISP1562 ISP1562 NXP Semiconductors HS USB PCI Host Controller Table 52. HcInterruptEnable - Host Controller Interrupt Enable register bit description .continued Address: Content of the base address register + 10h Bit Symbol Description 6 RHSC Root Hub Status Change: 0 - Ignore 1 - Enables interrupt generation because of root hub status change. 5 FNO Frame Number Overflow: 0 - Ignore 1 - Enables interrupt generation because of frame number overflow. 4 UE Unrecoverable Error: 0 - Ignore 1 - Enables interrupt generation because of unrecoverable error. 3 RD Resume Detect: 0 - Ignore 1 - Enables interrupt generation because of resume detect. 2 SF Start-of-Frame: 0 - Ignore 1 - Enables interrupt generation because of Start-of-Frame. 1 WDH HcDoneHead Write-back: 0 - Ignore 1 - Enables interrupt generation because of HcDoneHead write-back. 0 SO Scheduling Overrun: 0 - Ignore 1 - Enables interrupt generation because of scheduling overrun. 11.1.6 HcInterruptDisable register Each disable bit in the HcInterruptDisable register corresponds to an associated interrupt bit in the HcInterruptStatus register. The HcInterruptDisable register is coupled with the HcInterruptEnable register. Therefore, writing logic 1 to a bit in this register clears the corresponding bit in the HcInterruptEnable register, whereas writing logic 0 to a bit in this register leaves the corresponding bit in the HcInterruptEnable register unchanged. On a read, the current value of the HcInterruptEnable register is returned. The register contains 4 bytes, and the bit allocation is given in Table 53. Table 53. HcInterruptDisable - Host Controller Interrupt Disable register bit allocation Address: Content of the base address register + 14h Bit Symbol Reset Access Bit 31 30 MIE OC 29 28 0 0 0 0 R/W R/W R/W 23 22 21 26 25 24 0 0 0 0 R/W R/W R/W R/W R/W 20 19 18 17 16 reserved[1] reserved[1] Symbol Reset Access 27 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W ISP1562 ISP1562_2 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 02 - 1 March 2007 40 of 93 ISP1562 ISP1562 NXP Semiconductors HS USB PCI Host Controller Bit 15 14 13 12 Symbol Reset 10 9 8 0 0 0