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ISL6551 ISL6550 AN1002 UC3875 1-888-INTERSIL MIC4422 MIC4421 ISL550 ISL6651 - Datasheet Archive

200W, 470kHz, Telecom Power Supply Using ISL6551 ISL6551 FullBridge Controller and ISL6550 ISL6550 Supervisor and Monitor ® Application Note AN1002 AN1002 August 2002 Author: Chun Cheung Abstract This application note highlights design considerations for a 200W, 470kHz, telecom power supply using Intersil's ISL6551 ISL6551 ZVS Full-Bridge Controller and ISL6550 ISL6550 Supervisor And Monitor. The zero-voltage switching technique of the ISL6551 ISL6551 is presented in detail. A step-by-step design procedure for a 48V-to-3.3V@60A with 88% efficiency converter based on these two chips, incorporating both ZVS full bridge and current doubler topologies, is described. A few tips for design and debugging are then listed. Finally, experimental results with discussion gives users a deeper understanding of the performance of the reference design and the advantages of the ISL6550 ISL6550 and ISL6551 ISL6551. Introduction In medium to high power applications with extreme efficiency requirements, the full-bridge topology is probably the best choice. Besides great transformer utilization with this topology, higher efficiency and lower EMI levels are the major benefits if utilizing circuit parasitics, which include output capacitance of the bridge FETs, primary capacitance of the transformer, and leakage inductance, to achieve zerovoltage transitions (ZVT). In the conventional full bridge converter, these advantages cannot be realized without employing a significant amount of soft-switching/resonant circuitry which adds cost and circuit board real estate. Intersil's ISL6551 ISL6551 full-bridge controller implements a unique control algorithm, rather than the traditional phase-shifted control technique introduced by TI's UC3875 UC3875, to achieve ZVS with few components. In addition, the ISL6551 ISL6551 integrates additional sophisticated features such as Leading Edge Blanking, Latching Shutdown Input, Enable Input, Current Share Support, Fast Short-Circuit Shutdown, Synchronous Drive Signals, and Power Good Indication that the UC3875 UC3875 does not provide. The ISL6551 ISL6551 enables a complete and sophisticated power supply solution and can save board space and engineering effort as well as cost. This application note provides detailed design considerations of a 200W telecom power supply reference design employing both Intersil's ISL6551 ISL6551 full-bridge controller and ISL6550 ISL6550 Supervisor and Monitor while taking advantage of both ZVS full-bridge and current doubler topologies, as shown in Figure 1. An alternative secondary rectification technique for push-pull and bridge converters is introduced by Laszlo Balogh in his paper [2]. This technique offers potential benefits of better distributed power dissipation in densely packed power supplies and in medium to high power and/or high output current applications [2]. This converter is designed to meet the specification of an industry-standard half brick. Most of the converter circuits are placed in the central 2.50"x2.45" area and limited within 0.5" height, and all other unnecessary components such as test point connectors and I/O connectors are placed beyond this area. To easily modify the evaluation board for a broader base of applications, additional circuits are designed in and 1 magnetics components are not integrated with the PCB. This expands the area of the evaluation board when compared to a standard half-brick design. This DC/DC converter accepts a wide range input of 36V to 75V and generates a DACadjustable wide range output of 2.64V to 3.63V with 31.918mV step. An ultra high efficiency of 88% at 3.312V with a fully loaded 60A output has been achieved. + QA + Vp Vin Lo QC T + QB Q1 Co Vs - Vo Q2 QD FIGURE 1. FULL BRIDGE + CURRENT DOUBLER TOPOLOGIES This application note first introduces the unique ZVS technique of the ISL6551 ISL6551. The Supervisor and Monitor ISL6550 ISL6550 chip is then briefly introduced. Thereafter, a stepby-step design procedure for the reference design is followed, including power train component selection, component power dissipation calculations, magnetics design parameter calculations, and control loop design. A few tips for design and debugging are listed. Finally, experimental results of the evaluation board are discussed. Term Definitions, Block Diagram, Schematics, Layout, Bill of Materials, References, and Preliminary Specifications of the Reference Design are included at the end of this paper. Intersil ZVS Full Bridge Controller: ISL6551 ISL6551 The diagonal bridge switches are turned on together in a conventional full bridge converter which alternatively places the input voltage, VIN, across the primary of the transformer for a period of Ton, as shown in Figure 2. The limiting factor of achieving optimum efficiency in this circuit is the hard switching nature of the operation, which causes significant CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2002. All Rights Reserved Application Note 1002 are driven at a fixed 50% duty cycle and the two lower switches (QB & QD) are PWM-controlled on the trailing edge while the leading edge employs resonant delay. Figure 4 shows the drive signals of four bridge FETs and three options for synchronous rectification. The basic control principle of the ISL6551 ISL6551 is different from that of the UC3875 UC3875's phase-shift control which varies the phase between two 50% duty cycle control signals [1], requiring additional circuitry to derive the synchronous control signals and therefore adding cost. switching losses in high frequency, high input voltage, and /or high current applications. The switching losses can be reduced by employing snubbers, or quasi- or fully resonant, soft-switching circuits [1]. A D C ON FIGURE 2. CONVENTIONAL FULL BRIDGE PWM WAVEFORMS 28 VDD 18 ON/OFF In the ISL6551 ISL6551, rather than driving both of the diagonal full bridge switches together, the two upper switches (QA & QC) BANDGAP REFERENCE BGREF SHUTDOWN UVLO LATCH SOFT START 8 PKILIM 11 CSS ON VP 16 LATSD The ISL6551 ISL6551 is a ZVS full bridge controller that Intersil has designed for medium to high power AC/DC and DC/DC applications with ultra high efficiency requirements. The ISL6551 ISL6551 includes many integrated features for a more complete and sophisticated telecom or off-line power supply solution. The internal architecture of the IC is shown in Figure 4. Detailed ZVS operation of the ISL6551 ISL6551 will be presented by describing switching actions of the power train at each time interval in the following sections. Refer to the device datasheet for the operation of the integrated features. B 7 SHUTDOWN 27 VDDP1 24 UPPER1 23 UPPER2 26 VDDP2 LOWER1 DRIVER 22 LOWER1 LOWER2 DRIVER 21 LOWER2 UPPER1 DRIVER R_LEB 9 R_RESDLY 4 ISENSE 6 R_RA 5 CT 2 RD 3 RESODLY UPPER2 DRIVER LEB EAO 14 RAMP ADJUST CLOCK GENERATOR PWM LOGIC ERROR AMP EAI 13 EANI 12 CURRENT SHARE DC OK 25 PGND 20 SYNC1 NOTE: Pin numbers in the diagram refer to the SOIC package. 19 SYNC2 CS_COMP VSS 15 SHARE 10 1 17 DCOK Circuits Referenced to VSS External Single Point Connection Required FIGURE 3. ISL6551 ISL6551 INTERNAL STRUCTURE 2 Circuits Referenced to PGND Application Note 1002 CLOCK UP1 QA UP2 QC QB LOW1 QD LOW2 VP Q1 SYNC1 1 Q2 SYNC2 LOW1' Q1 2 LOW2' Q2 SYNC2 Q1 3 SYNC1 Q2 T0 T1 T2 T3 T4 T0-T1=LOWER RIGHT-LEG POWER TRANSFER PERIOD T1-T2=UPPER LEFT-TO-RIGHT FREEWHEELING PERIOD T2-T3=Q1-TO-Q2 DEADTIME (FREEWHEELING) T3-T4=LOWER LEFT-LEG RESONANT PERIOD T5 T6 T7 T8=T0 T4-T5=LOWER LEFT-LEG POWER TRANSFER PERIOD T5-T6=UPPER RIGHT-TO-LEFT FREEWHEELING PERIOD T6-T7=Q2-TO-Q1 DEADTIME (FREEWHEELING) T7-T8=LOWER RIGHT-LEG RESONANT PERIOD In the above Figure, T0 through T8 are exaggerated only for demonstration purposes. There are three possible synchronous rectification drive schemes: 1. Existing Synchronous Drive Signals (Sync1 & Sync2) + Non-inverting High Current Drivers (such as MIC4422 MIC4422)- The Synchronous Fets (Q1 & Q2) are turned off together at the dead time and turned on alternatively every clock period; 2. Lower Drive Signals + Proper Delay + Inverting High Current Drivers (such as MIC4421 MIC4421)- The corresponding synchronous FET is turned off whenever a voltage is across the secondary winding; 3. Existing Synchronous Drive Signals + Inverting High Current Drivers- The synchronous FETs are turned on together at the dead time and turned on alternately every clock period. FIGURE 4. DRIVE SIGNALS TIMING DIAGRAM 3 Application Note 1002 Vin -N 0 - Vin N Io -, Fsw 2 VS / Lo Vo ) (Vs- ILO1 Vo/Lo Vo/Lo ILO2 ) -Vo (Vs /Lo )/ L o 2V o (Vs- 2Vo/L Io -, Fsw 2 o Io, Fclock ILO Vo (Vs- IS WORST CASE )/Lo Io -2 Vo/Lo 0 Lo Vo)/ (Vs-2 Io -2 2Vo/Lo Io IQ1 WORST CASE (Vs-2 IQ2 Io 2Vo/Lo Lo Vo)/ WORST CASE IMAG Vin/ -V i n g Lma / Lm ag ag n/Lm o+Vi )/NL o (Vs-V IP WORST CASE Vo/NLo Imag -2 Imag -2 Io-2N 0 Io 2N -SYNC1 Q1 1 SYNC2 Q2 LOW1' Q1 2 LOW2' Q2 SYNC2 Q1 3 SYNC1 T0-RESDLY Q2 T1 T0 T2 T3 T4 T0-T1=LOWER RIGHT-LEG POWER TRANSFER PERIOD T1-T2=UPPER LEFT-TO-RIGHT FREEWHEELING PERIOD T2-T3=Q1-TO-Q2 DEADTIME (FREEWHEELING) T3-T4=LOWER LEFT-LEG RESONANT PERIOD T5 T6 T7 T8=T0 T4-T5=LOWER LEFT-LEG POWER TRANSFER PERIOD T5-T6=UPPER RIGHT-TO-LEFT FREEWHEELING PERIOD T6-T7=Q2-TO-Q1 DEADTIME (FREEWHEELING) T7-T8=LOWER RIGHT-LEG RESONANT PERIOD In the above figure, T0 through T8 are exaggerated only for demonstration purposes. The slope of each waveform is in an approximation. For a more accurate representation, losses should be included. The worst case happens at only Q1 or Q2 carrying the load current during the freewheeling period. The current distribution through Q1 and Q2 is different in these three drive schemes. Case 2 is the best option since both of its synchronous FETs are turned on during the freewheeling period. Note that VS is in the case of no primary leakage inductance, otherwise, delay would be induced, as illustrated in the experimental results. FIGURE 5. CURRENT WAVEFORMS 4 Application Note 1002 T0 ->T1, QA-to-QD Power Transfer (Active) Period [Figure 6] transformer and the output capacitance CC of QC are discharged to from VIN to zero voltage (~diode drop). QA = QD = ON, QB = QC= OFF QA= ON, QD = OFF, QB = QC = OFF + QA DA QC CA QA DA CC - Vp Vin + DC Lk QC + CC - Cp Vp Vin Lk - DB T QD DD CB QB CD - Vs + Cp T QB DC CA - Vo + DB D1 Co Lo2 DD CD - Lo1 Q1 QD CB Vs Vo + Lo1 Q1 D1 Co Lo2 Q2 Q2 D2 D2 SYNCHRONOUS FETS Q1 Q2 OFF SYNC DRIVE ON OFF ON OFF INV_LOW DRIVE ON ON ON OFF INV_SYNC DRIVE ON OFF SYNCHRONOUS FETS Q1 Q2 SYNC DRIVE ON INV_LOW DRIVE INV_SYNC DRIVE FIGURE 6. QA-TO-QD POWER TRANSFER PERIOD When QD is turned on, QA has been already turned on in the previous period, the resonant delay. In this transfer (active) period, the full input voltage (VIN) is across the primary of the transformer, and VIN/N is across the secondary of the transformer once the primary current catches the reflected output current. The primary current first flows from QD to QA due to the prior resonant current and then reverses in direction until the current reaches zero and starts ramping up at a rate determined by VIN, the magnetizing inductance, and the output inductance. Simultaneously, Q2 should stay off for eliminating shootthrough currents, and Q1 is turned on to reduce conduction losses; the current through the Lo2 is positive ramp, and the current through the Lo1 is negative ramp. The ON-time of QD is a function of VIN, Vo, the transformer turns ratio N, and the output load Io. QD is turned off when the peak of the modified current ramp signal hits the error voltage, and the freewheeling period then begins. T1 -> T2, QA-to-QC Clamped Freewheeling (Passive) Period [Figure 7] Once QD is turned off by trailing edge pulse width modulation, the primary current continues flowing into the output capacitance (Coss) CD of QD, which will be charged up from the switch Rds(on) Drop to VIN - Diode Drop. Simultaneously, the primary capacitance (Cp) of the 5 FIGURE 7. QA-TO-QC CLAMPED FREEWHEELING PERIOD This transition is accomplished using the energy stored in the leakage inductance of the transformer, the magnetizing inductance, the reflected output inductance, and any external commutating inductance. After the transition, the primary current flows in the same direction and the real freewheeling period begins. One end of the transformer is shorted to VIN by the channel of QA, and the other end is clamped to VIN by the body diode of QC, which is the only path that the primary current can go through. The losses due to the body diode conduction at the freewheeling period could be significant if the primary current (the lumped sum of the magnetizing current and the reflected secondary winding freewheeling current), is relatively high. These conduction losses can be minimized by employing the maximum allowable turns ratio of the main transformer, i.e, the maximum allowable duty cycle in the design. In some applications, shunting upper switches with Schottky diodes might be another possible way to reduce the conduction losses. For a wide range input application, if a pre-regulator is implemented, then a fixed, high duty cycle (~100%) post full-bridge regulator can be achieved and the freewheeling time is minimized. The power dissipation of the upper FETs can be therefore reduced significantly. Three different synchronous rectification drive schemes can be implemented with the ISL6551 ISL6551 as shown in Figures 4 and 5. The INV_LOW DRIVE scheme is the one that would provide an additional path for the secondary freewheeling Application Note 1002 current since both Q1 and Q2 are turned on during the freewheeling time, which could reduce the conduction losses and the reflected output current in the primary. The amount of the load current split into Q1 and Q2 depends on the voltage drop across the secondary winding, the Rds(on) of Q1 & Q2, and/or the body diode drop of Q1 & Q2. The optimum performance of the converter happens when the load current is split into both turned-on Q1 and Q2 evenly. In reality, the body diode drop at one of upper FETs, the leakage inductance, and the shorted primary winding force one of the synchronous FETs to carry the majority of the output current while the other conducts a minority of the load. T3 -> T4, Lower Left-Leg (QB) Resonant Period [Figure 9] QA = OFF, QC = ON, QB = QD = OFF + QA DA QC DC CA CC - Vp Vin Lk + Cp T QB - DB QD DD CB CD - T2 -> T3, Q1-to-Q2 Dead Time Period [Figure 8] Vs Vo + Lo1 Co Q1 D1 Lo2 Q2 QA= ON, QD = OFF, QB = QC = OFF D2 + QA DA QC DC CA CC Vin Lk SYNCHRONOUS FETS Cp OFF ON OFF ON INV_SYNC DRIVE + Q2 SYNC DRIVE Vp Q1 INV_LOW DRIVE - OFF ON T QB - DB QD DD CB CD - Vs FIGURE 9. LOWER LEFT-LEG RESONANT PERIOD Vo + Lo1 Co Q1 D1 Lo2 Q2 D2 SYNCHRONOUS FETS Q1 Q2 SYNC DRIVE OFF OFF INV_LOW DRIVE ON ON INV_SYNC DRIVE ON ON FIGURE 8. Q1-TO-Q2 DEAD TIME PERIOD The dead time is used to prevent simultaneous conduction of QC and QD, which would cause shoot-through currents. The dead time is still part of the freewheeling period. The drive control signals for the power switches therefore do not change states while the drive signals of the synchronous FETs change levels. In the SYNC DRIVE scheme, both Q1 and Q2 now are turned off and the load current freewheels through the body diodes of both FETs. This introduces high conduction losses in high output current applications. Shunting both synchronous FETs with schottky diodes can reduce the losses. In the INV_SYNC DRIVE scheme, both Q1 and Q2 are turned on, therefore, schottky diodes are not required, so are not in the INV_LOW DRIVE scheme. 6 The dead time period is followed by the lower left-leg resonant period. It begins with QA turned off and QC turned on. At the beginning of this transition, the input voltage is applied first across the commutating inductance (leakage and any external inductances), i.e, the real primary stays zero until the current through these inductors changes in direction in the next time interval. This can be seen in the voltage waveforms across the primary winding and the secondary winding, discussed in the EXPERIMENTAL RESULTS section on pages 24-25. The direction of the current through the primary winding remains the same as that in the previous time interval. The current flows into the transformer primary capacitance (Cp) and the output capacitance (Coss) CA of QA, which will be charged up from zero voltage (~Rds(on) Drop) to VIN. Simultaneously, the output capacitance CB of QB is discharged to from VINRds(on) Drop to zero voltage (~diode drop). This transition is accomplished with the energy stored in the primary inductance (including leakage inductance, magnetizing inductance, and any external inductance). It takes a longer time to complete this transition than the one reaching the freewheeling period since the energy stored in the resonant inductances decreases due to the conduction losses of the power switches and the primary current is decaying in the freewheeling period. Once QB is clamped to zero voltage by its own body diode, QB is turned on at zero voltage (ZVS transition). Another power transfer period is followed by the other diagonal power switches (QC-to-QB). The rest of the Application Note 1002 discussion (Figures 10 to 13) is just the repetition of another half cycle. T4 -> T5, QC-to-QB Power Transfer Period [Figure 10] QB = QC = ON, QA = QD = OFF + QA DA QC DC CA CC - Vp Vin Lk + Cp discharged from VIN to zero voltage (~diode drop). This transition is accomplished using the energy stored in the leakage inductance of the transformer, the magnetizing inductance, the reflected output inductance, and any external commutating inductance. After the transition, the primary current flows in the same direction and the real freewheeling period begins. One end of the transformer is shorted to VIN by the channel of QC, and the other end is clamped to VIN by the body diode of QA, which is the only path that the primary current can go through. Refer to the T1->T2 period for more detailed discussion. T QB - DB QB = OFF, QC = ON, QA = QD = OFF QD DD CB CD - Vs + Vo + QA Lo1 DA QC DC CA Q1 D1 CC Co Lo2 - Vp Vin Q2 Lk + Cp D2 T QB - SYNCHRONOUS FETS Q1 OFF ON INV_LOW DRIVE OFF OFF DD ON CD Vo ON INV_SYNC DRIVE QD CB Q2 SYNC DRIVE DB - Vs Q1 + Lo1 D1 Co Lo2 Q2 D2 FIGURE 10. QC-TO-QB POWER TRANSFER PERIOD When QB is turned on, QC has been already turned on in the previous period, the resonant delay. In this transfer (active) period, the full input voltage (VIN) is across the primary of the transformer, and VIN/N is across the secondary of the transformer once the primary current catches the reflected output active current. The primary current first flows from QB to QC due to the prior resonant current and then reverses in direction until the current reaches zero and starts ramping up at a rate determined by VIN, the magnetizing inductance, and the output inductance. Simultaneously, Q1 should stay off for eliminating shootthrough currents, and Q2 is turned on to reduce conduction losses; the current through the Lo1 is a positive ramp, and the current through Lo2 is a negative ramp. The ON-time of QB is a function of VIN, Vo, the transformer turns ratio N, and the output load Io. QB is turned off when the peak of the modified current ramp signal hits the error voltage, and another freewheeling period then begins. T5 ->T6, QC-to-QA Clamped Freewheeling Period (Passive) [Figure 11] Once QB is turned off, the primary current continues flowing into the output capacitance (Coss) CB of QB, which will be charged up from the switch Rds(on) Drop to VIN + Diode Drop. Simultaneously, the primary capacitance (Cp) of the transformer and the output capacitance CA of QA are 7 SYNCHRONOUS FETS Q1 Q2 SYNC DRIVE OFF ON INV_LOW DRIVE ON ON INV_SYNC DRIVE OFF ON FIGURE 11. QC-TO-QA CLAMPED FREEWHEELING PERIOD T6 -> T7, Q2-to-Q1 Dead Time Period [Figure 12] The dead time is used to prevent simultaneous conduction of QA and QB, which would cause shoot-through currents. The dead time period is still part of the freewheeling period, the drive control signals for the power switches therefore do not change states while the drive signals of the synchronous FETs change levels. In the SYNC DRIVE scheme, both Q1 and Q2 now are turned off, the load current free wheels through the body diodes of both FETs, which introduces high conduction losses in high output current applications. Shunting both synchronous FETs with schottky diodes can reduce the losses. In the INV_SYNC DRIVE scheme, both Q1 and Q2 are turned on, therefore, schottky diodes are not required, so are not in the INV_LOW DRIVE scheme. Application Note 1002 QB = OFF, QC = ON, QA = QD = OFF QC = OFF, QA = ON, QB = QD = OFF + + QA DA QC DC CA QA DA CC - Vp Vin Lk QC + CC - Cp Vp Vin Lk - DB T QD DD CB QB CD - Vs + Cp T QB DC CA - Vo + DB QD DD CB CD - Lo1 Vs Vo + Lo1 Co Q1 D1 Co Lo2 Q1 D1 Lo2 Q2 Q2 D2 D2 SYNCHRONOUS FETS Q1 Q2 SYNC DRIVE OFF ON INV_LOW DRIVE ON ON INV_SYNC DRIVE ON ON FIGURE 12. DEAD TIME PERIOD T7 -> T8=To, Lower Right-Leg (QD) Resonant Period [Figure 13] The previous dead time period is followed by the lower rightleg resonant period. It begins with QC turned off and QA turned on. At the beginning of this transition, the input voltage is applied first across the commutating inductance (leakage and any external inductances), i.e, the real primary stays zero until the current through these inductors changes in direction in the next time interval. This can be seen in the voltage waveforms across the primary winding and the secondary winding, discussed in the EXPERIMENTAL RESULTS section on page 24-25. The direction of the current through the primary winding remains the same as that in the previous time interval. The current flows into the transformer primary capacitance (Cp) and the output capacitance (Coss) CC of QC, which will be charged up from zero voltage (~Rds(on) Drop) to VIN. Simultaneously, the output capacitance CD of QD is discharged to from VINRds(on) Drop to zero voltage (~diode drop). This transition is accomplished with the energy stored in the primary inductance (including leakage inductance, magnetizing inductance, and any external inductance). It takes a longer time to complete this transition than the one reaching the freewheeling period since the energy stored in the resonant inductance decreases due to the conduction losses of the power switches and the primary current is decaying in the freewheeling period. Once QD is clamped to zero voltage by its own body diode, QD is turned on at zero voltage (ZVS transition). At this point a full operating cycle is completed. 8 SYNCHRONOUS FETS Q1 Q2 SYNC DRIVE ON OFF INV_LOW DRIVE ON OFF INV_SYNC DRIVE ON OFF FIGURE 13. LOWER RIGHT-LEG RESONANT PERIOD Intersil Supervisor and Monitor: ISL6550 ISL6550 The ISL6550 ISL6550 is a precision flexible, VID-code-controlled reference and voltage monitor for high-end microprocessor and memory power supplies. It monitors various input signals, and supervises the systems with its outputs. The ISL6550 ISL6550 saves board space, design time, and system cost. The internal structure of the ISL550 ISL550 is shown in Figure 14. The reference design is implemented with the MLFPpackaged ISL6550 ISL6550, C version. Refer to the device datasheet for operating details. In the reference design, the ISL6550 ISL6550 monitors the output voltage and supervises the ISL6551 ISL6551 full bridge controller. · The spare operational amplifier of the ISL6550 ISL6550 is used as a differential amplifier and its output (VOPOUT) is sent to the inverting input (EAI) of the error amplifier of the ISL6551 ISL6551. Note that the VOPOUT is limited to 5V. · The under-voltage delay (UVDLY) prevents false triggering of the START output during startup, and the ISL6550 ISL6550 START output is fed to the ON/OFF input of the ISL6551 ISL6551. In output over-voltage (+8.33%) and undervoltage (-8.33%) conditions, the START is triggered and latches shutdown the ISL6551 ISL6551 controller. When the VCC of ISL6550 ISL6550 is below the turn-on/off threshold, the START is held low and disables the ISL6651 ISL6651 controller. · The output reference BDAC, which is fed to the noninverting input (EANI) of the error amplifier of the ISL6551 ISL6551, is programmed by the 5-bit VIDs and the resistor network that connects to DACHI and DACLO. Note that a 50k total resistance of the network is recommended and the overall Application Note 1002 output error should include VREF5 error and external resistor divider error as well as the internal buffer offset. In the reference design, the output voltage can be programmed from 2.64V to 3.63V with 31.918mV step and +/-3% statics error over full operating conditions. to +/-40% about the BDAC voltage. In the reference design, the over/under voltage window is set at +/-8.33%. · PEN is connected to a mechanical switch to turn on/off the converter manually. It is also controlled by the circuitries that monitor the input voltage level and the thermal condition of the converter. · The output voltage is sensed by the OVUVSEN, and the OV-UV windows is centered around the BDAC voltage and can be programmed with the OVUVTH pin from +/-5% · PGOOD provides an indication if the output voltage is within over/under voltage limits (+/-8.33%). VREF5 VCC 5 1 Buffered 5V REF Opamp VOPM 3 VOPP 2 VOPOUT 4 5V + 17 START LOGIC BLOCK see 2A, 2B, 2C below 10uA to 5V PEN PEN: H = Enable; L = Disable 16 UVLOCKOUT (POR) OVUVSEN 19 POR: H = VDD too low; L = VDD OK OV OV: H = Over-Voltage; L = OK OVUVTH 8 THRESHOLD PROGRAM UV UV/OV hysteresis See Note below 18 PGOOD UV: H = Under-Voltage; L = OK UVD: H = UV Delay timed out; L = no time-out R1 DACHI 9 VID4 11 UVDELAY 20 UVDLY (each VID pin) 10uA to 5V VID3 12 VID2 13 7 BDAC VID1 14 R2 VID0 15 R4 DACLO 10 6 GND R3 2A 2B PEN POR Q Note: UV/OV hysteresis = 10% Note: UV/OV hysteresis = 40% PEN POR OV UVD 2C PEN POR Q Note: UV/OV hysteresis = 10% PEN POR POR R R Q Q: H = Fault; L = No Fault OV UV UVD PEN S UV UVD PEN FAULT LATCH PEN POR Q UV NOTE: S input dominates Q S FAULT LATCH PEN POR OV UV NOTE: No latch in 2B POR OV UV NOTE: S input dominates Q NOTE: Pin numbers in the diagram refer to the SOIC package. FIGURE 14. ISL6550 ISL6550 INTERNAL STRUCTURE 9 Q Q: H = Fault; L = No Fault OV R5 Application Note 1002 Converter Design This section presents a step-by-step design procedure for a 48V-to-3.3V, 200W, 470kHz with 88% efficiency converter using both ISL6551 ISL6551 and ISL6550 ISL6550 for telecom applications (i.e VIN=36V-to-75V). The converter is designed with secondary-referenced, peak current-mode control, and both ZVS full bridge and current doubler topologies. For simplicity, all calculations in this section neglect the transitions shown in Figure 5. The worst case current waveforms are used even in the INV_LOW DRIVE scheme, unless otherwise stated. Select Synchronous DRIVE Scheme The INV_LOW DRIVE scheme for synchronous rectification is employed in the reference design. This scheme induces less conduction losses in the synchronous FETs than both INV_SYNC and SYNC DRIVE schemes, which can be explained with a few equations (EQ. 1- 6). The terms used in all equations are defined later in the paper, unless otherwise stated in the text. Io 2 = ( IQ1 + IQ2 ) 2 = IQ1 2 + IQ2 2 + 2 · IQ1 · IQ2 (EQ. 1) IQ1 2 + IQ2 2 IQ1 2 + IQ2 2 + 2 · IQ1 · IQ2 (EQ. 2) The power dissipation is the same in the active (transfer) period but different in the freewheeling period for the three drive schemes. In both INV_SYNC and SYNC DRIVE schemes, only one synchronous FET is turned on carrying all the load current during the freewheeling period. The conduction losses of each leg in the freewheeling period can be approximated with EQ. 3: 1D Psynfetfr = Io 2 · - · Rdsonsyn 2 (EQ. 3) In the INV_LOW DRIVE scheme, both synchronous FETs are turned on and each one carries a portion of the load current during the freewheeling period. The power dissipation of each leg in this period is reduced to EQ. 4: 1D Psynfetfr = ( IQ1 2 + IQ2 2 ) · - · Rdsonsyn 2 (EQ. 4) Comparing EQ. 3 to EQ. 4, we note that the INV_LOW scheme induces less power dissipation in the synchronous FETs by an amount of EQ. 5: Psynfetfr = 2 · IQ1 · IQ2 · ( 1 D ) · Rdsonsyn (EQ. 5) In addition, the INV_LOW scheme also helps cut down the conduction losses in the primary FETs since the primary has less reflected secondary current, which decreases with the difference between IQ1 and IQ2, as shown in EQ. 6: 10 Is IQ1 IQ2 Ip - = -N 2N (EQ. 6) Although the INV_LOW scheme is a better choice from the power dissipation standpoint, the user should pay special attention to the impact of having on overlap between both synchronous FETs during the freewheeling period in current share, light load, start up, and turn-off operations. Some discussions are presented in the EXPERIMENTAL RESULTS section. Select Switching Frequency and Define Maximum Available Duty Cycle Several things are considered when selecting an appropriate switching frequency for a particular application. The size of the converter (limited by sizes of magnetics components), the overall losses of magnetics components, the switching losses of power MOSFETs, the desired efficiency, the transient response, and the maximum achievable duty cycle are all considerations. An iterative process is required, monitoring changes of the above parameters, to obtain an optimum switching frequency for a particular application. Users can use equations presented in this paper to design a MathCAD worksheet, which will help obtain a rough idea of the range of optimum frequencies for their applications. Note that the higher the switching frequency is, the higher the loop bandwidth (typical 1/10 or higher of the switching frequency) can be realized, but the lower the maximum duty cycle is available. In the initial design of the evaluation board, these parameters are pre-selected: Fsw=250kHz=Fclock/2, tDEAD=200ns, and tRESDLY=100ns. The maximum available duty cycle then can be calculated using EQ. 7 (Dmaxav=85%). The duty cycle defined in this application note is the ratio of the ON-time interval of a lower FET to one clock period. t DEAD t RESDLY Dmaxav = 1 - Fclock (EQ. 7) Define Turns Ratio The primary-to-secondary turns ratio of the main transformer should be chosen as high as possible without exceeding the maximum available duty cycle (Dmaxav=0.85) at the minimum line (Vinmin=36V, or the input UV setpoint) and the rated load (Io=60A) situation. The higher the turns ratio is, the less the load current is reflected to the primary side, and the less the power losses are induced by the primary MOSFETs. The maximum allowable turns ratio can be calculated with EQ. 8 (Nmax=3.79). 2 · ( Vomax + Vmisc + Vsynfet ) · N Dmaxav = - Vinmin Rdsonpri · Io Vsynfet · N - N (EQ. 8) Application Note 1002 where Vsynfet = Io x Rdsonsyn/2 is the channel drop of the synchronous FETs at half of the load (assuming that the output load is split evenly into both synchronous FETs during the freewheeling period), Vomax is the maximum output voltage (3.63V), and Vmisc is the sum of the miscellaneous voltage drops including contact resistance, winding resistance, PCB copper resistance. The initial guess of Vmisc is 0.3V for having a safe margin. If the load (Io) conducts through only one synchronous FET during the freewheeling period, then EQ. 8 can be simplified to EQ. 9 (Nmax=3.77): 2 · ( Vomax + Vmisc + 2 · V synfet ) · N Dmaxav = -Io Vinmin Rdsonpri · -N (EQ. 9) With the assumptions of Rdsonpri=25 x1.2m (Tj=500C) and Rdsonsyn=1.125x1.13m (Tj=500C), EQ. 9 produces Nmax=3.77. Since the size and height of the converter are limited to that of a telecom half brick, a planar transformer with a low number of turns on both the primary and secondary sides is required. Therefore, 7/2 and 11/3 turns ratio are preferred choices. A transformer with 7 primary turns and 2 secondary turns has been used in the reference design due to the availability of magnetic cores in stock. In fact, a transformer with 11/3 turns ratio is generally recommended. Output Filter Design (Current Doubler) The output L-C filter is normally defined based on requirements of the output ripple voltage (70mV) and the transient response (dVtr=150mV). In general, if the requirement of the transient response is met, then the output ripple voltage will be within the limit. As a rule of thumb, the overall ripple current (dIo) should be no more than 20% of the rated load, and the output inductor value (for each one) can be defined by EQ. 10: 2 · ( Vo + 2 · V synfet ) · ( 1 D ) Lo = -dIo · Fclock The minimum required output capacitance (Co) can be estimated by EQ. 13 when limiting the output ripple voltage contributed by output capacitance to be no more than dVCo. dIo 1 Co = - · -dV Co 8 · Fclock (EQ. 13) In addition to meeting the requirements of ESR and Co, the output capacitors should be able to absorb the output RMS current, as defined in EQ. 14. dIo Iorms = -12 (EQ. 14) The output voltage ripple can be conservatively approximated by EQ. 15. The first two terms (dVESR and dVESL) contributed by the equivalent series resistance (ESR) and the equivalent series inductance (ESL) of the output capacitors are the dominant ones and are normally accurate enough to estimate the ripple voltage. The last term (dVCo) contributed by the output capacitance (Co) is normally much smaller and can be neglected since the peak of the dVCo happens at the ripple current across zero and does not align with the peak of dVESR, as shown in Figure 15. The positive and negative peaks of the overall ripple voltage (sum of all three components) relative to the DC level is not symmetric (caused by dVCo and dVESL) unless the converter operates at 50% duty cycle. This asymmetry between positive and negative peaks is not a big concern in most applications since both dVCo and dVESLare generally very small compared to the ESR portion. Note that the DC level remains constant. Refer to [6] for more details. ESL 1 dIo Voripple dIo · ESR + - Vs + - · -Lo Co 8 · Fclock (EQ. 15) + 0 dVESR (EQ. 10) dVESL 0 + - The ripple current (dI) through each inductor can be calculated with EQ. 11: ( Vo + 2 · V synfet ) · ( 2 D ) dI = -Lo · Fclock dVCo (EQ. 11) - FIGURE 15. OUTPUT RIPPLE VOLTAGE COMPONENTS The requirement of the transient response is the major factor of defining the maximum overall ESR of the output capacitors in EQ. 12. Note that this converter is designed to meet 150mV transients (dip/overshoot) for a 25% rated load step (ESR < 10m). dVtr ESR < -Istep 0 (EQ. 12) The ESL of a capacitor is not usually listed in databooks. It can be practically approximated with EQ. 16: 1 1 ESL = - · -Co ( 2 · Fres ) 2 (EQ. 16) where Fres is the resonant frequency that produces the lowest impedance of the capacitor. At the very edge of the transient, the equivalent ESL of all output capacitors induces a spike, as defined in EQ. 17 for a 11 Application Note 1002 given dI/dt, that adds on the top of the existing voltage undershoot/overshoot due to the ESR and capacitance. dI V ESL = ESL · -dt (EQ. 17) Vo f(Istep) to load transients. This could cause a significantly large undershoot/overshoot at the output. In the reference design, the loop bandwidth (fc) is lower than the zero [1/(2*ESR*Co)] of the output capacitors, which have low ESL transient component due to low dI/dt(1A/us), therefore, the required output capacitance can be roughly approximated with EQ. 21 [7]. Istep Co -2 · f c · dVtr V CAP V ESL 1 fc -2 · ESR · Co (EQ. 21) Several lower-profile TAIYO YUDEN 100u, 6.3V capacitors (JMK212F107MM JMK212F107MM) have been used in the evaluation board to meet the electrical requirements of the above discussion and the height constraint of the converter. Istep FIGURE 16. TYPICAL TRANSIENT RESPONSE WAVEFORM Thus, the overall output voltage undershoot/overshoot due to load transients can be summarized in EQ. 18, in which the last term can be normally dropped out if the very edge of the transient is the dominant peak, as shown in Figure 16. dVtr f ( Istep ) + V ESL + V CAP (EQ. 18) where 1 + ( 2 · f c · Co · ESR ) 2 f ( Istep ) = Istep -2 · f c · Co for 1 fc -2 · ESR · Co Istep f ( Istep ) -2 · f c · Co for 1 fc -2 · ESR · Co V CAP = V HUMP for step-up transients V CAP = V SAG for step-down transients The last term in EQ. 18 is a direct consequence of the amount of output capacitance. After the initial spike, all the excessive charge is dumped into the output capacitors on step-down transients causing a temporary hump at the output, and the output capacitors deliver extra charge to meet the load demand on step-up transients causing a temporary sag before the output inductors catch the load. The approximate response time intervals for removal and application of a transient load are defined by dTn and dTp, respectively. where (EQ. 22) Io dI Iindrms = - + -2 12 (EQ. 23) Calculations for Synchronous FETs (Q1 & Q2) Some fundamental formulas that are used to calculate RMS values of triangular and trapezoid waveforms and to derive most equations in this paper are defined below. Ib I 1d Irms1 = Ic Ia d CASE 1 I 2 Ic 2 + -12 Ib I Ic Ia CASE 2 d 0 (EQ. 19) Irms2 = Istep dTn = Lo -2Vo Istep · dTp V SAG = -2 · Co where Electrical design parameters of the output inductors are summarized in EQs. 11, 22, & 23, which specify the ripple current, the peak current, and the RMS current of each inductor. Io + dI Iindpeak = -2 f ( Istep ) Istep · ESR Istep · dTn V HUMP = -2 · Co Besides ESL, ESR, and capacitance of the output capacitors, other system parasitics such as board resistance and inductance should be included in the load transient analysis [6], which will not be discussed in this paper. Ib (EQ. 20) CASE 3 Irms3 = In low-profile, high current density, and high frequency applications, the required output capacitance defined in EQ. 13 might not be enough to deliver or absorb energy due I Ia 0 d Istep dTp = Lo -Vs 2Vo 12 Ic 2 + I 2 · d - 12 Id I 2 Ic 2 · ( d d 2 ) + - · d 12 In the power transfer period, one synchronous FET is turned off, and the other one is turned on conducting all the load Application Note 1002 Ib I Ia CASE 4 1d 0 Irms4 = Ic Ic 2 + I 2 · ( 1 d ) - 12 Ic = Ia + Ib -2 WHERE Id = Ic · d I = Ib Ia current. The peak current through the FET is defined by the load current plus half of the output ripple current in EQ. 24. In this period, the RMS current through each FET can be calculated with EQ. 25 using Case 2 formula. Note that the duty cycle (D) is defined as the ratio of the ON-time interval of a lower FET over one clock period (twice of the switching period), which explains the 1/2 factor in the equation. dIo Isynpeak = Io + -2 Isynrmstr = Io 2 + dIo 2 · D - - 12 2 1D Io 2 + dIo 2 · - 2 12 Isysrmstr 2 + Isysrmsfr 2 Psynfet = Isynrms 2 · Rdsonsyn An additional term "Isyndeadavg x Vdsyn" should be added to EQ. 28 if the SYNC DRIVE scheme is implemented. Isynrmsfr however would be slightly smaller. The maximum voltage across the synchronous FET can be approximated with EQ. 31, adding 30% margin for the ringing on the rising edge. (EQ. 27) (EQ. 28) (EQ. 29) where p is the percentage of load current through one of the synchronous FETs. A guess of p can made by looking at the primary freewheeling current, as shown in the EXPERIMENTAL RESULTS section. For the other two drive schemes, FDIST is one. In the SYNC DRIVE scheme, both synchronous FETs are turned off during the dead time period. The freewheeling 13 The synchronous FETs should be selected such that the VDS rating and power rating of the MOSFETs are greater than Vsynmax and Psynfet, respectively. Four 30V Siliconix Si4842DY Si4842DY MOSFETs are used for each leg. Note that any switching losses, which will be discussed later, should be included in the calculation to define the maximum power dissipation. (EQ. 26) In addition, the distribution factor (FDIST) for IQ1 and IQ2 currents during the freewheeling period for the INV_LOW DRIVE scheme can be included in EQ. 26 for an accurate calculation: ( 1 p )2 + p2 (EQ. 31) (EQ. 25) As shown in EQs. 25 and 26, the higher the ripple current is, i.e., the lower the output inductances are, the higher the RMS currents are, and the higher the conduction losses of the synchronous FETs are. F DIST = (EQ. 30) Vinmax Vsynmax = - ( 1 + 0.3 ) N Thus, the overall RMS current through one synchronous FET can be defined in EQ. 27, while the conduction losses of each synchronous FET can be calculated with EQ. 28. Isynrms = t DEAD dIo ( t DEAD + t RESDLY 0.5T ( 1 D ) ) Isyndeadavg = - Io + - 4·T (1 D) · T (EQ. 24) In the worst case, all the load current flows through one of the synchronous FETs during the freewheeling period (including the resonant and dead periods for simplicity), the RMS current through the FET can be estimated by EQ. 26. Isynrmsfr = current flows through the body diodes of the FETs, and any external schottky diodes. In the worst case, the freewheeling current flows through only one leg, and the average current for the dead time can be estimated by EQ. 30, where tDEAD is the dead time and tRESDLY is the resonant time. Calculations for Primary Switches (QA, QB, QC, & QD) The peak current through the primary winding happens at the end of the active period, as defined in EQ. 32 Io + dI Imag Ipripeak = - + -2N 2 (EQ. 32) ( Vin 2 · I p · Rdsonpri ) · D Imag = -Lmag · Fclock (EQ. 33) EQ. 33 defines the peak-to-peak magnetizing current. The RMS current through the power switches in the active period can be estimated by EQ. 34, which also defines the overall RMS current through a lower FET. Iprirmstr = where Io - 2 + dIp 2 · D - - 2N 12 2 (EQ. 34) dI dIp = - + Imag N If there is a time delay Td to turn on the lower FET after its output capacitance is completely discharged, i.e, the resonant delay is set longer than is necessary, then the current will flow through the body diode of the lower FET, which has an average value defined in EQ. 35. Io Imag dI ( D + Td / T ) Td Ipriavgres = - + - + - · - 2N 2 2N ( 2 D ) 2T (EQ. 35) Application Note 1002 The freewheeling current flows through the channel and the body diode of upper FETs in alternate freewheeling periods and at alternate directions. The RMS current through the channel can be calculated with EQ. 36. The average current through the body diode of the upper FET can be estimated with EQ. 37. Iprirmsfr = 1D Io dI dI 2 ( 1 D ) 2 - + - + Imag 2 + - · - - 2N 2N ( 2 D ) 2 2 12N 2 ( 2 D ) 2 of EQ. 42 happens at D=0.5. Several lower-profile ITW Paktron capacitors (105K100ST2814 105K100ST2814) and an external capacitor have been used in the evaluation board. If a hold up time (tHOLDUP) is required when the input line is momentarily disconnected, then EQ. 43 helps define the required hold up capacitance: 2Po · t HOLDUP Cin = - · ( Vin 2 V 2 HOLDUP ) (EQ. 36) Io- -dI - 1 D Ipriavgfr = - + Imag - · - 2N 2 2 2N ( 2 D ) (EQ. 37) or where Thus, the overall RMS current through the channel of each upper FET is defined in EQ. 38: Iprirms = Iprirmstr 2 + Iprirmsfr 2 (EQ. 38) With all the above RMS and average current information, the conduction losses of each power switch can be roughly estimated with EQs. 39 and 40. As shown in EQs. 34 and 36, the higher the inductor ripple current and the magnetizing current are, i.e., the lower the output inductance and the magnetizing inductance are, the larger the RMS currents are, the higher the power losses would be induced by the primary switches. Pupfet = Iprirms 2 · Rdsonpri + Ipriavgfr · Vd (EQ. 39) (EQ. 43) Po · t HOLDUP Cin - · Vin · Vin = Efficiency Vin = Vin V HOLDUP The overall input voltage ripple induced by the ESR and capacitance of the input capacitors can be estimated with EQ. 44. In addition, the spikes caused by the ESL of the input capacitors should be decoupled with lower ESL ceramic capacitor. Io T Vinripple = - · ( D D 2 ) · - + ESRin · Ipripeak 2N Cin (EQ. 44) Furthermore, for a low EMI level performance, an additional L-C filter might be required in the front end. However, the combination of both ZVS full bridge and current doubler topologies helps reduce the size of this input EMI filter. Switches Losses and Driver Losses Plowfet = Iprirmstr 2 · Rdsonpri + Ipriavgres · Vd (EQ. 40) Four 100V Siliconix SUD40N10 SUD40N10 MOSFETs are selected for the bridge switches such that the ratings of the device are greater than Pupfet, Plowfet, and the maximum input voltage. Note that any switching losses, which will be discussed later, should be included in EQs. 39 and 40 to define the maximum power dissipation of the primary switches, which limits the MOSFET selection. Input Filter Design The input pulsating current filtered by the input capacitors has an RMS value in EQ. 41, while the minimum required input capacitance is defined in EQ. 42. Iinrms = 2 Io - 2 · ( D D 2 ) + ( dIp ) - · D - 2N 12 IoT Cin = - · ( D D 2 ) · -2N dVincap (EQ. 41) 1 Ppriswon = - V on · I on · t on · Fsw 2 (EQ. 42) When the lower FET is turned off, its corresponding upper FET is clamped to VIN in a very short time. The corresponding synchronous FET is turned on when the voltage across the secondary winding vanishes, therefore, there are no turn-on switching losses for the synchronous FETs. The resonant delay and the delay caused by the leakage inductance to have any voltage across the The dVINcap is the acceptable input ripple voltage contributed by the amount of input capacitance, of which is the input capacitors (ITW Patron capacitors in the reference design) that filter most of pulsating currents. The maximum value of EQ. 41 happens at D~0.5, while the maximum value 14 In general, switching losses are an insignificant portion compared to conduction losses of the power switches if ZVS transitions are achieved. Since the commutating inductances store the peak energy to swing the output capacitance of the upper FET from VIN to zero volt at the beginning of the freewheeling period before the upper FET is turned on, therefore, the upper FETs are lossless at turn on transitions. At the end of freewheeling period, the commutating inductances store the least energy, which might not be enough (especially in high line and/or low load conditions) to swing the output capacitance of the lower FET to zero volt before they are turned on. The turn-on losses of the lower FETs can be approximated with EQ. 45. The turnoff losses of primary switches can be minimized with a high speed driver such as Intersil HIP2100 HIP2100. (EQ. 45) Application Note 1002 secondary winding, as illustrated in EXPERIMENTAL RESULTS, prior to turn off the synchronous FET, help to achieve ZVT for the synchronous FETs at turn off. To achieve ZVT as discussed in previous lines, the synchronous FET drivers however should have high current capability with little propagation delays such as MICREL 9A MIC4421 MIC4421 inverting drivers or better. The conduction losses and reverse recovery losses of body diodes of the synchronous FETs at turn on or off are not discussed here, but they do show up in Figure 35. Note that the drivers with high current capability can shorten the transition time and reduce the switching losses. The driver losses due to the gate charge of the MOSFETs should be investigated thoroughly to prevent over stressing. The switching losses of both primary and secondary drivers and its corresponding average driver current due to the gate charge can be estimated with EQs. 46 and 47, respectively, the current ramp signal, which makes the supply look voltage mode. A reasonable small Lmag can assist ZVS and decrease any noise sensitivity problems. Around 100uH is a start point for telecom brick applications. In addition, it is recommended to have a small gap in the transformer stabilizing the magnetizing inductance so that the magnetizing current can be within a controllable range. The leakage inductance is not an issue in the design. In fact, it is part of the commutating inductance to assist ZVS using its stored energy. Too much leakage inductance however will lower the effective duty cycle, resulting in a lower turns ratio. The primary-to-secondary capacitance should be minimized since it robs energy from the ZVS elements increasing the resonant time and decreasing the maximum available duty cycle and the ZVS load range. Qg Pdr = - · Vcc 2 · Fsw V GS (EQ. 46) As far as the size of the transformer is concerned, it varies with applications. In the reference design, the transformer is limited to less than 0.5 inch height, being able to fit into a telecom half brick. Qg Idr = - · Vcc · Fsw V GS (EQ. 47) Determine Commutating Inductance where Qg and VGS are defined in the MOSFET datasheet. Define Requirements of Main Transformer This section summarizes major design requirements of the main transformer at the switching frequency. The turns ratio of the transformer is derived from EQ. 9 while EQ. 32 defines the peak current through the primary winding. The RMS current through the primary winding is defined in EQ. 48. Iprms = 2 · Iprirms (EQ. 48) The current through the secondary winding is only half of the load, and its RMS currents in both transfer and freewheeling periods can be defined by EQs. 49 and 50, respectively. The overall RMS current through the secondary winding can be calculated with EQ. 51. Isrmstr = dI 2 Io 2 + - · D - 4 12 (EQ. 49) Isrmsfr = dI Io + - 2 + dI 2 ( 1 D ) 2 · ( 1 D ) - 2 2 ( 2 D ) 12 ( 2 D ) 2 (EQ. 50) Isrms = Isrmstr 2 + Isrmsfr 2 (EQ. 51) The magnetizing inductance (Lmag) is determined by the number of turns of primary winding, the core geometry, and the air gap. The Lmag however should not be designed too low. If it is too low, high power dissipation will be introduced in the primary switches, and too much ramp will be added to 15 The required external commutating inductance is determined by the slower transition (from passive to active period) since the commutating inductance stores the least energy for ZVS. The ZVS condition is that the energy stored in the commutating inductance, defined in EQ. 52, should be greater than the energy stored in the primary capacitance, defined in EQ. 53. Thus, the required external commutating inductance can be roughly estimated with EQ. 54. Refer to [1] for detailed discussion. 1 E L = - ( L ext + L k ) · ( Imag + Ip ) 2 2 (EQ. 52) 1 E C = - ( 2Coss + Cp ) · Vin 2 2 (EQ. 53) 2 ) L ext < Vin · ( 2 · Coss + Cp - L k -( Imag + Ip ) 2 (EQ. 54) Note that the output capacitance (Coss) of the MOSFET varies with the drain to source voltage, and the primary current (Ip) at the end of the freewheeling period determined by the turns ratio and current distribution factor FDIST. The external commutating inductor however would be better defined in the real circuits by trial and errors. Control Loop Design The secondary-referenced, peak current control is implemented in the converter design. Two pulse transformers pass the PWM information of the full-bridge controller (ISL6551 ISL6551) to two high current half-bridge drivers (HIP2100s) in the primary. A current transformer is to feed the primary current information to the full-bridge controller, as a feed-forward loop. The control loop is closed by an error Application Note 1002 amplifier, for loop compensation purpose, cascaded with a differential amplifier, for remote sense purpose. Figure 17 shows the block diagram of the overall closed-loop system. VIN ISOLATION PWM POWER STAGE + OUTPUT FILTER PRIMARY DRIVERS PRIMARY SIDE + - SECONDARY SIDE HIP2100s Lo RAMP Lo Co Ro MIC4421s CURRENT TRANSFORMER SECONDARY DRIVERS ERROR AMPLIFIER DIFFERENTIAL AMPLIFIER + - + Vo - REF. + - FIGURE 17. BLOCK DIAGRAM OF CLOSED-LOOP SYSTEM This peak current mode controlled system can be simplified as shown in Figure 18, for setting up an initial feedback compensation, and EQ. 55 defines the approximate openloop transfer function. The factor "2" in the equation is due to that only half of the load is sensed by the current transformer. 2N · Ncs Hopen ( S ) = - · Hd ( S ) · He ( S ) · Zo ( S ) Rcs (EQ. 57) Refer to Vatché's Article [3] for another way of modeling the loop. G=2N*Ncs/Rcs + - Co Zo(S) ESR Ro ESL ERROR AMP. [He(S)] DIFFERENTIAL AMP. [Hd(S)] + + - (EQ. 56) 1 Qp = -D · Mc · 1 - 0.5 2 Mc = 1 + Se -Sn Vs ( 2 D ) Rcs Sn = - · -2Lo N · Ncs 16 + - 1 Hs ( S ) = -S - + -S2 1 + -Wn · Qp Wn 2 Se = Sm + Sin Hopen2 ( S ) = Hopen ( S ) · Hs ( S ) (EQ. 55) Designers should initially set a low cut-off frequency, such as 1kHz, system loop with this simplified model as a start point and then continue to modify the loop under a stable condition with a design tool such as a Venable System. Note that the model does not include the slope compensation component and does not account for subharmonic oscillation phenomenon in current-mode controlled converters. The high-frequency correction term given by EQ. 56 will account for the phenomenon [4]. Wn = · Fsw A better representation of the open loop transfer function for the overall system is defined in EQ. 57: Vo REF. - FIGURE 18. SIMPLIFIED CLOSED-LOOP MODEL Application Note 1002 Special Notes for Configuring the ISL6551 ISL6551 The controller can be easily configured using Table 1 in the ISL6551 ISL6551 datasheet. In this section, several things that require the users' attention are highlighted. For a detailed configuration, please refer to the device datasheet. · For a tighter tolerance of operating frequency, a 5% NPO ceramic capacitor is recommended for CT. · The resonant delay should not be too long, otherwise, the residual resonant current will flow through the body diode of the lower FET and additional losses are generated. The maximum available duty cycle will also be decreased. · The amount of slope contributed by the magnetizing current is given by EQ. 58, while the amount of slope contributed by the internal circuit of the IC is given by EQ. 59. The overall slope added to the current ramp signal is the sum of these two equations. An internal ramp (programmed by a R_RA resistor) might not be required if the ramp contributed by the Lmag is enough for the slope compensation. Vin - Rcs Sm = - · -Lmag Ncs (EQ. 58) BGREF 1 Sin = - · -R ¬RA 500 10 12 (EQ. 59) · The voltage at ISENSE pin should be scaled appropriately such that the desired peak current equals or less than Vclamp-200mV-Vramp, as defined in EQ. 60. In addition, the turns ratio of the current transformer, Ncs, should be selected so that power losses at Rcs (current sense resistor) at the lowest line and the maximum output load is less than the power rating of one or two SMT0805 SMT0805 resistors so that minimum losses are induced by the Rcs and less board space is required. Sin · D ( Vclamp 200mV ) -Fclock -Rcs Ipripeak -Ncs (EQ. 60) · The peak current limit set by the PKILIM is lower than the cycle-by-cycle current limit controlled by the Vclamp in the reference design for two reasons: 1) ISENSE (at full load) has to be designed no greater than the minimum reference voltage (2.64V) at EANI pin, otherwise, the monotonic output startup at full load cannot be achieved; and 2) high losses can be introduced if ISENSE (at full load) is pushed up to the Vclamp (3.75V) with a low turns ratio (150:1) current transformer. In the reference design, the ISL6550 ISL6550 would latch the ISL6551 ISL6551 off in overload conditions. · The voltage at EANI and EAO should be designed lower than the Vclamp, otherwise the output will be regulated at Vclamp and the output load will be limited to the equivalent current voltage. Since both EANI and EAO are clamped by the same voltage (Vclamp), the output voltage would dip if the current ramp exceeds the EAO during the 17 startup, especially for applications with constant current load. Hence, the EANI should be set higher than EAO, otherwise, the output voltage cannot have a monotonic startup. (This problem could be solved by setting the soft start at the EANI pin instead of the CSS pin allowing the clamping voltage to come up at a very high speed.) In the reference design, the synchronous FETs are turned off during start up achieving monotonic rise for resistive load applications. The FETs are turned on after a certain load and then cannot be turned off even back to no-load, which achieves a better dynamic performance. Users however can completely remove the current peak detecting circuits (D23., they are only handy circuits for users to turned off the synchronous FETs whenever necessary) and rely on the R134 and C132 to achieve monotonicity for the output voltage startup. · The BGREF should be kept as clean as possible, otherwise, the over current trip point set at the PKILIM would be lower than is expected due to the noise/ripple at the bandgap reference. A low ESR 0.1uF ceramic capacitor is recommended for decoupling. Due to an internal race condition, the ISL6551 ISL6551 cannot work properly without a 399kW resistor connecting between BGREF and VDD pins. For additional reference load (no more than 1mA), this pull-up resistor should be scaled accordingly such that the converter can start up properly. In other words, VDD should source at least the amount of BGREF external load current through the pull-up resistor. · The SHARE pin requires a 30k load. A low ESR 0.1uF or higher ceramic capacitor should be connected to the CS_COMP pin to design a much lower current loop bandwidth than that of the voltage regulation loop in current share operation. · It is critical that the input signal to ISENSE decays to zero prior to or during the clock dead time, otherwise, it could cause severe errors in the signal reaching the PWM comparator. Examine the current ramp tail of the converter at maximum duty cycle and full load operations, and extend the dead time to reset the current ramp tail if oscillations occur. The C61 in the peak current detecting circuits (page 6 of the schematics) causes a tail at the current ramp. If it is removed, a smaller dead time can be used while maintaining proper operations. Layout Considerations · When doing the layout, users should pay special attention to the VSS and PGND returns (Analog Ground and Power Ground). VSS is the reference ground, the return of VDD, of all control circuits and must be kept as clean as possible from all switching noises. It should be connected to the PGND in only one location as close to the IC as practical. For a secondary control system, it should be connected to the net after the output capacitors, i.e., the output return pinouts. For a primary control system, it Application Note 1002 should be connected to the net before the input capacitors, i.e., the input return pinouts. land" design for this exposed die pad should include thermal vias that drop down and connect to buried copper plane(s). This combination of vias for vertical heat escape and buried planes for heat spreading allows the MLFP to achieve its full thermal potential. It is recommended to connect this pad to the low noise copper plane Vss. · Heavy copper traces should be connected to the bias pins (VDD, VDDP1, VDDP2) and the ground pins (VSS and PGND) for heat spreading. · The copper routings from the drivers to the FETs should be kept short and wide, especially in very high frequency applications, to reduce the inductance of the traces so that the drive signals can be kept clean, no bouncing. · For additional tips, please refer to "PCB Design Guidelines For Reduced EMI" [5]. · In the MLFP package, the pad underneath the center of the IC is a "floating" thermal substrate. The PCB "thermal 33.3V 34.3V VIN LATCH RESET ENABLE (PEN) 8 LATCH CANNOT BE RESET 1 LATCH RESET 2 4 ON/OFF (START) LATCHED PKILIM > BGREF ILIM_OUT (INTERNAL) 3 LATCHED W/70ms DELAY PKILIM < BGREF 5 LATSD LATCHED LATCH RESET BY VDD 6 VDD 7 8.6V 9.6V SOFT START VOUT DCOK (+/-3, 5%) FAULT CONVERTER OVERCURRENT VOUT INPUT (VOUT < 1-8.33%) BEYOND DISABLED TURN-ON WITH UV DELAY 1+/-8.33% THRESHOLD GOOD MASTER OV (4.0V) VDD VDD INPUT TURN-ON TURN-OFF TURN-OFF THRESHOLD THRESHOLD THRESHOLD FIGURE 19. SHUTDOWN TIMING DIAGRAM OF THE CONVERTER Shutdown Timing Diagram of the Converter INPUT UV (1): With all the biases powered up and the mechanical switch at the PEN pin turned on, the converter is enabled after the input reaches its turn-on threshold (34.3V). The output voltage rises to its regulation point following the soft start. The soft start capacitor continues to be charged up to the clamping voltage (Vclamp). The DCOK is pulled low indicating "GOOD" once the output reaches within -3% of the set point. ENABLE (2): When the PEN pin is pulled low, the soft start capacitor is discharged very quickly and all the drivers are disabled. The DCOK is pulled high indicating "FAULT" when 18 the output voltage is discharged below -5% of the set point. When the PEN pin is released, a soft start is initiated. OVER CURRENT (3): If the output of the converter is over loaded, i.e, the PKILIM is above the bandgap reference (BGREF), the soft start capacitor is discharged quickly and all the drivers are turned off. Once the output voltage is below -8.33% of the regulation point, the capacitor of the under-voltage delay set at ISL6550 ISL6550 is then charged up, and the START is latched when the voltage at the capacitor reaches 5V. The ISL6551 ISL6551 controller is quickly shut down by the START. If the over load is removed and the converter can return to normal operation within the under-voltage Application Note 1002 delay (around 70mS), then the START will not be latched. The latch can be reset by the PEN signal, which is controlled by the input voltage, the mechanical switch, and the thermal condition of the converter. If latching the converter off in overload conditions is not allowed, then version B of ISL6550 ISL6550 can be used. Then the converter would be running in hiccup mode in overload conditions. OUPUT UV & LOCAL OV (4): If the output voltage is beyond +/-8.33% of the set point and does not reach the master OV setpoint (4.19V) for any reason, the START is then latched, so is the converter. The latch can be reset by the PEN. OUPTUT MASTER OV (5): If the master OV circuit is triggered, the LATSD is pulled high and latches the controller off. The latch can be reset ONLY by cycling VDD. It CANNOT be reset by toggling ENABLE (PEN). RESET LATCH (6): The soft start capacitor starts to be charged after the VDD increases above the ISL6551 ISL6551 and ISL6550 ISL6550 turn-on thresholds. VDD UV LOCKOUT (7): The IC is turned off when the VDD is below the ISL6551 ISL6551 and ISL6550 ISL6550 turn-off thresholds. The soft start is reset. INPUT UV LOCKOUT (8): When the input voltage is below its turn-off threshold 33.3V, the converter is disabled and latched off. The soft start is reset. TABLE 1. BDAC OUTPUT PROGRAMMING CODE # VID4 VID3 VID2 VID1 VID0 VOUT (V) 17 0 1 1 1 0 3.185 18 0 1 1 0 1 3.216 19 0 1 1 0 0 3.248 20 0 1 0 1 1 3.280 21 0 1 0 1 0 3.312 22 0 1 0 0 1 3.344 23 0 1 0 0 0 3.376 24 0 0 1 1 1 3.408 25 0 0 1 1 0 3.440 26 0 0 1 0 1 3.472 27 0 0 1 0 0 3.504 28 0 0 0 1 1 3.536 29 0 0 0 1 0 3.568 30 0 0 0 0 1 3.599 31 0 0 0 0 0 3.631 Table 2 summarizes major design parameter requirements. Most components are selected or designed based on these values. Users should generate a similar table for their applications and select components with derating guideline of the datasheet or their own companies. Summary of Design TABLE 2. DESIGN PARAMETER REQUIREMENTS Table 1 is the BDAC output programming code. PARAMETER TABLE 1. BDAC OUTPUT PROGRAMMING CODE CONDITION VALUE UNIT DUTY CYCLE AND SWITCHING FREQUENCY # VID4 VID3 VID2 VID1 VID0 VOUT (V) 0 1 1 1 1 1 2.642 1 1 1 1 1 0 2.674 2 1 1 1 0 1 2.706 3 1 1 1 0 0 2.738 Cin 4 1 1 0 1 1 2.770 Iinrms 5 1 1 0 1 0 2.801 6 1 1 0 0 1 2.833 Co 7 1 1 0 0 0 2.865 8 1 0 1 1 1 9 1 0 1 1 10 1 0 1 11 1 0 12 1 13 Dmaxav tDEAD=200ns, tRESDLY=100ns, Fsw=250kHz 85 % Fsw CT=180pF 235 kHz D=0.5, dVincap=1.65V 3 uF Vin=48V, D~0.5, Vo=3.63V 5.4 A fc=Fsw/10=23.5kHz 677 uF dIo Lo=0.8uH, Vin=75V, Vo=3.63V 12.9 A 2.897 Iorms Vin=75V, Lo=8uH, Vo=3.63V 3.4 A 0 2.929 ESR dVtr = 150mV @ 25% Load Step 10 m 0 1 2.961 1 0 0 2.993 dI Lo=0.8uH, Vin=75V, Vo=3.63V 16.3 A 0 0 1 1 3.025 Iindpeak 38.2 A 1 0 0 1 0 3.057 Io=60A, Vin=75V, Vo=3.63V assuming the load evenly distributed between both output inductors 14 1 0 0 0 1 3.089 Iindrms A 1 0 0 0 0 3.121 Io=60A, Vin=75V, Vo=3.63V assuming the load evenly distributed between both output inductors 34.7 15 16 0 1 1 1 1 3.153 19 INPUT CAPACITORS OUTPUT CAPACITORS OUTPUT INDUCTORS Application Note 1002 TABLE 2. DESIGN PARAMETER REQUIREMENTS (Continued) PARAMETER CONDITION TABLE 3. FULL LOAD POWER LOSSES ANALYSIS POWER DISSIPATION AT 60A LOAD VALUE UNIT MAIN TRANSFORMER ELEMENTS Imag Lmag=60uH (Limited by Core), Vo=3.63V, Fsw 0.92 A Ipripeak Vin=75V, Vo=3.63V 11.4 A Iprms VIN=75V, Vo=3.63V 9.9 A Isrms Vin=75V, Vo=3.63V 33.4 A N Limited by Core 7:2 - 36V 48V CALCULATION CONDITIONS Clock Dead Time 175ns Resonant Time 50ns Td 40ns Vin=36V, Vomax=3.63V, Vmisc=0.3V, Dmaxav=0.85 - CURRENT TRANSFORMER Ncs 150:1 - 235kHz 7:2 Magnetizing Inductance 60uH Output Inductor 3.77 Switching Frequency Transformer Turns Ratio Nmax 75V 0.8uH MOSFET Rds(on) Value at Tj=500C PRIMARY SIDE PRIMARY SWITCHES Vin=75V, Vo=3.63V 3.6 A Ipriavgres Vin=36V, Vo=3.63V 0.095 A Iprirms Vin=75V, Vo=3.63V 4.94 A Iprirsmtr Vin=75V, Vo=3.63V 2.57 A Iprirsmtr Vin=36V, Vo=3.63V 3.71 Pdr Each Primary Driver Vcc(max)=13.2, Qg=50nC x 2 at VGS=10V, Two Siliconix SUD40N1025 SUD40N1025 0.42 Pupfet Vin=75V, Vd=0.78V, Vo=3.63V 4.1 W Plowfet Vin=36V, Vd=0.75V, Vo=3.63V with Td=40n. The worse case could be at Vin=75 due to switching losses 0.90 W Upper FETs Conduction 2.616W 3.371W 4.179W Lower FETs Conduction Ipriavgfr 0.819w 0.630W 0.427W Primary Winding Copper 1.023W 1.087W 1.155W Current Sense Winding 0.110W 0.082W 0.053W Pinouts of Current Sense Transformer 1.521W 1.141W 0.731W A W Full Bridge Drivers 0.677W 0.677W 0.677W SECONDARY SIDE Synchronous FETs Conduction 2.290W 2.293W 2.296W Secondary Winding Copper 1.005W 1.054W 1.106W Output Inductors Copper 2.575W 2.642W 2.716W Synchronous Drivers Isynpeak Vin=75V, Vo=3.63V 66.4 A Isynrms Vin=75V, Vo=3.63V 42.5 Each Secondary Driver Vcc(max)=13.2V, Qg=30nC x 4 at VGS=4.5V Four Siliconix Si4842DY Si4842DY 1.09 W Vin=75V, Four Siliconix Si4842DYs Si4842DYs. Body Diode Conduction and Recovery Losses are not Included Here 2.3 1.8056W 1.805W 0.122W 0.095W 0.063W Current Sense Rectifiers 0.075W 0.055W 0.034W A Pdr 1.805W Current Sense Resistor SYNCHRONOUS FETs Psynfet OTHERS 20 0.697W 0.741W 1.126W 1.157W 0.360W 0.360W 0.360W Guess Overall Magnetics Core (20% of Conduction) 0.942W 0.973W 1.006w Miscounted Switching Losses, Body Diodes Conduction and Reverse Recovery Losses at Bridge FETs and Synchronous FETs, Contact Resistance, Clamping Losses, and Error 3.914W 3.492W 5.625W TOTAL Table 3 summarizes a rough full load power losses analysis for 3.3V output of the reference design. 0.656W 1.096W Biases other than Drivers W R22 PCB Copper 27.33W 27.87W 31.03W Application Note 1002 Thoughts After Design Users can use these thoughts to make some possible improvements of the reference design. 1. The input capacitors (C13-C15 C13-C15) can be replaced with ceramic capacitors with smaller footprints such as TDK SMT1812 SMT1812 C4532X7R2A105M C4532X7R2A105M. 2. The output capacitors (2220 footprint) can be replaced with smaller footprint 1812 capacitors such as the TDK new product, C4532X5R0J107M C4532X5R0J107M. 3. The main transformer (T2) and output chokes (L2 and L3) are too tall for brick applications with current design form factors. They can be integrated with the PCB to save board space and reduce losses. An external inductance however might be required for ZVS operation because an integrated PCB transformer would have a very low leakage inductance, which could not store enough energy to swing the primary capacitance. 4. The current sense transformer (T4) runs hot due to its high pinout resistance (more than 10m) and it eats up too much space, users should redesign the current sense transformer for better form factor (like J-lead) and thermal performance. In addition, it cannot be placed symmetrically in the board due to space constraint. In the applications of no space limitation, it should be relocated. 5. The overall layout can be improved by removing test point connectors (TP1-TR34 TP1-TR34), which are not required in the real design. 6. The peak current limit set by the PKILIM is lower than the cycle-by-cycle current limit controlled by the Vclamp, i.e., the PKILIM is triggered earlier than the cycle-by-cycle limit.Thus, the reference-based clamp circuit, for the cycle-by-cycle current limit accuracy, is not necessary. 7. Users can completely remove the current peak detecting circuits (D23, C61., they are only handy circuits for users to turned off the synchronous FETs whenever necessary) and rely on the R134 and C132 to achieve monotonicity for the output voltage startup. The dead time then can be cut down. 8. R22 can be replaced with a wire for users to look at the primary current. It is not an ideal zero Ohm, couple milliOhms could induce 0.2% or higher less efficiency. 9. For a narrower range input (48V+/-10%) and/or a lower output voltage application, a higher turns ratio (4:1) can improve the efficiency as much as 1%. Design Tips For Using ISL6551 ISL6551 1. Since the upper FETs carry not only active currents through their channels but also freewheeling currents through their body diodes, the power dissipation of the upper FETs (QA and QD) is higher than the lower FETs (QC and QB), which can be replaced with smaller size of MOSFETs such as SO-8 in moderate primary current applications. The switching losses however should be taken into account. 2. With assistance of a pre-regulator, the post full-bridge regulator can be designed to operate at a fixed maximum duty cycle (~100%). Thus, the freewheeling currents flow 21 through the body diodes of the upper FETs in the shortest period. The power dissipation of the upper FETs therefore can be reduced significantly in high primary current applications. The narrower the input line range is, the higher the turns ratio of the main transformer can be chosen, and the higher the efficiency can be achieved. The power losses and cost of the pre-regulator however should be taken into account for overall performance evaluation. 3. An external commutating inductor can be added in series with the primary side of the transformer to assist ZVS transitions if the energy stored in the leakage inductance and the magnetizing inductance is less than the energy stored in the output capacitance (2*Coss) of the power switches, the primary capacitance (Cp), and any external capacitance. Extending the ZVS range with an external inductor is at the penalties of additional component cost and less effective duty cycle resulting in a lower turns ratio, which adds power losses to the primary side. 4. An external capacitor in parallel with the primary side of the transformer can help lower the dV/dt and the noise level without introducing additional losses when the zerovoltage switching is still retained. The penalties, as discussed above, still hold. 5. External high current bridge drivers cascading with the ISL6551 ISL6551 drivers help absorb the power that supposed to dissipate in the controller so that the controller is not over stressed in high gate capacitive load applications, which extends the application range in a much higher power level. 6. The higher the switching frequency is, the higher the system closed-loop bandwidth can be realized, and the lower the input and output capacitances are required for overcoming load transients. This, however, comes at the cost of the efficiency. 7. The current ramp signal to ISENSE should decay to zero prior to or during the clock dead time. Hence, the dead time should be set long enough to reset the trailing-edge tail of the current ramp at the maximum duty cycle operation, otherwise, oscillations could occur. 8. The leakage inductance of pulse transformers would induce propagation delay depending on the drive current through it. The higher the energy through the pulse transformer is, the longer the delay would be. 9. To save board space, the silk screen text can be deleted, as some brick manufacturers do today. 10. In the initial design, use a SOD123 diode (such as MBR0530T1 MBR0530T1) in series with VDD and VDDP pins to protect the ISL6551 ISL6551 from being damaged by reverse biasing, especially for the design with the MLF package, which cannot to be replaced easily. At the end of the design, the diode can be substituted with a zero Ohm 805 resistor. 11. For a high current density and multi-layer design, buried vias can be used to save space, but cost is added. 12. The current share support is for paralleling operation but not for redundancy. When it is used in redundant systems, it requires OR'ing circuit inserting between the converter and the common output bus. Application Note 1002 Debugging TIPS This section discusses some easy ways to bring up the power train in the least amount of time. Before/After Build 1. Before building the board, it is wise to check if all magnetics components such as current transformer, main transformer, output inductors, input inductor, and commutating inductor are designed properly using magnetics design tools or waveforms across the magnetics method. In addition, all components, especially the power train components, should be checked if their power/thermal derating guidelines are met. 3. Increase the input voltage slowly with input and output current limiting and monitor the current through the main transformer or the current ramp signal that is fed into the ISL6551 ISL6551. No asymmetric behaviors should be seen and ten percent of load is a good start point. 4. If the converter is not stable, use a low ESR ceramic capacitor (say 0.1uF) at the feedback network to cut down the cut-off frequency until the converter becomes stable. Or use the simplified model in Figure 18 to design a low cut-off frequency system loop. Later, optimize the loop with a tool. Apply Biases with Current and Voltage Limiting 5. Enable the synchronous drivers. If the timing is not set properly, shoot-through currents between the secondary winding and the synchronous FETs would be induced and affect the converter's performance, especially in light load conditions. Start with some load (10% rated load) and work backward. Before applying the input voltage to the converter, a quick check of all control circuits is always the first step. 6. Check the current ramp signal at the ISENSE pin of ISL6551 ISL6551 and see if a longer blanking time is required. 2. After the build, check if pin 1 of all ICs is placed properly. 1. Use Table 1 on page 15 of the ISL6551 ISL6551 datasheet design checklist. 2. Disable anything that prevents both ISL6551 ISL6551 and ISL6550 ISL6550 from free running. In the reference design, disconnecting the resistor (R6) between the START pin of the ISL6550 ISL6550 and the ON/OFF pin of ISL6551 ISL6551 will allow both chips to be free running. 3. In series forward diodes with the bias lines so that all ICs will not be damaged by reverse biasing. The reference design has built-in diodes. 4. Apply biases with current limiting. 5. Check if both DC and AC voltage levels of each ISL6550 ISL6550 pinout are correct. No noises and no over stressed. 6. Check if both DC and AC voltage levels of each ISL6551 ISL6551 pinout are correct. No noises and no over stressed. 7. Check if a nice sawtooth is in CT pin and equal pulse width is between upper drive signals. 8. Check if both DC and AC voltage levels of drive signals of bridge FETs and synchronous FETs are correct. No noises and no over stressed. 9. Check if the delays such as Dead Time, Resonant Delay, and LEB Delay are designed properly. 10. Check if the timing of the synchronous signals is designed properly. No shoot through. Power Up Slowly with Current and Voltage Limiting 1. If possible, disconnect the secondary winding from the secondary side, then increase the input voltage slowly. Fix the primary timing until no (very low) current is drawn from the input line. And check if the magnetizing current is in a proper level. 2. Connect the secondary winding back to the circuit and disable the synchronous drivers such that the current conducts only through the body diodes of the synchronous FETs. 22 7. Tune up. Design a proper resonant delay by programming the R_RESDLY resistor and changing (if possible) the ZVS elements such as, the magnetizing inductance, the leakage inductance, any external commutating inductor, the output capacitance of bridge FETs, and any external primary capacitance. Note that any loop that is used to measure the primary current can induce additional commutating inductance, depending upon the enclosed air area, and extends the ZVS load range. For instance, 5.0" of 14AWG 14AWG wire can contribute as much as 80nH inductance. Experimental Results The evaluation board is intended to test the ISL6551 ISL6551 in a 200W half brick form factor. The specification of this converter is summarized at the end of this paper. Most of the converter circuitries are placed in the central 2.50"x2.45" area and limited within 0.5" height, and all unnecessary components such as test point connectors and Input/Output connectors are placed beyond the center.This DC/DC converter accepts a wide range input, 36V to 75V, and generates a wide range output, 2.64V to 3.63V with 31.918mV step and 60A full load. An ultra high efficiency, 88% efficiency at 3.3V fully loaded output, has been achieved. In the following sections, some critical aspects of the converter are examined with detailed experimental data. Drive Signal Timing The drive signals are taken when the ISL6551 ISL6551 is free running, which can be done by removing the input line and R6 that connects to the START pin of the ISL6550 ISL6550. The resonant delay to turn on the lower switch after the corresponding upper switch is turned off, as shown in Figure 20, helps achieve zero-voltage switching (ZVS). The dead time to turn on the upper FET after the corresponding lower switch is turned off, as shown in Figure 21, helps eliminate the shoot-through currents through the primary switches during switching transitions. Figures 22 and 23 show the resonant delay and the dead Application Note 1002 time set at the ISL6551 ISL6551 prior to be processed through pulse transformers (T3 andT5) and bridge drivers (Intersil HIP2100 HIP2100). The dead time and the resonant delay, with 2V as the turn-on threshold of primary switches, of one converter is summarized in Table 3. The real delays at the primary switches are shorter than the "delays" set at the ISL6551 ISL6551 due to long propagation delays of falling edges of both upper and lower drive signals. Furthermore, the leakage inductances of pulse transformers also would induce additional propagation delays depending on the drive current through it. The higher the energy through the pulse transformer is, the longer the delay would be. 2 3 1 TABLE 4. RESONANT DELAY AND DEAD TIME DELAY AT SWITCH'S GATE AT ISL6551 ISL6551 Resonant Delay 32 ns 36 ns Dead Time 157 ns 186 ns FIGURE 22. RESONANT DELAY AT ISL6551 ISL6551. CHANNEL 1: LOWER DRIVE SIGNAL; CHANNEL 2 & 3: UPPER DRIVE SIGNALS 3 3 1 2 2 1 FIGURE 20. RESONANT DELAY AT LOWER FET. CHANNEL 1: LOWER DRIVE SIGNAL; CHANNEL 2 & 3: UPPER DRIVE SIGNALS 1 2 FIGURE 21. DEAD TIME AT LOWER FET. CHANNEL 1: LOWER DRIVE SIGNAL; CHANNEL 2 & 3: UPPER DRIVE SIGNALS 23 3 FIGURE 23. DEAD TIME AT ISL6551 ISL6551. CHANNEL 1: LOWER DRIVE SIGNAL; CHANNEL 2 & 3: UPPER DRIVE SIGNALS The synchronous drive signals are the inverting version of both lower drive signals with little propagation delays. The turn-on gate resistors, R23 and R33, soften the rising edge of the lower drive signals, while the diodes, D5 and D19, reduce their falling edge delay. Meanwhile, the diodes, D1 and D4, minimize the turn-off delay of the synchronous drive signals, while the resistors, R3 and R18, increase their turnon delay. As shown in Figure 24, the synchronous FET is turned off/on (Channel 2) whenever its corresponding lower switch is turned on/off (Channel 3). There is no overlap between these two drive signals. Hence, shoot-through currents between the secondary winding and the synchronous FETs are eliminated. Application Note 1002 1 3 2 Figure 29 shows the operation waveforms for INV_SYNC DRIVE scheme. Since only one synchronous FET is turned on and conducts currents during the freewheeling period, the freewheeling current reflected to the primary is higher than that of the INV_LOW DRIVE scheme. Hence, the INV_LOW DRIVE scheme produces as much as 2% higher efficiency than the INV-SYNC DRIVE scheme. 3 4 2 FIGURE 24. SYNCHRONOUS DRIVE SIGNAL. CHANNEL 1: LOWER DRIVE SIGNAL AT ISL6551 ISL6551; CHANNEL 2: SYNCHRONOUS DRIVE SIGNAL; CHANNEL 3: LOWER DRIVE SIGNAL AT THE LOWER FET Switching Waveforms WINDING VOLTAGE AND CURRENT Figures 24 to 29 show the voltage waveforms across the transformer and the primary currents through it. Note that the R22 is replaced with a 5.0" of 14AWG 14AWG wire so that the primary current can be measured at this loop, which should be shorted when determining the ZVS load range. The delay between the primary voltage and secondary voltage on the leading edge, as shown in Figures 25 and 26, is caused by the leakage inductance of the transformer. The input voltage is applied first across the leakage inductor resetting its current, and the voltage across the real primary and secondary must stay zero until the current through the leakage inductor changes in direction and reaches the value of the reflected load. A higher load results in larger stored energy in the leakage inductor that needs to be reset before going into the active mode, and the longer the delay is. There is almost no delay for zero load operation, as shown in Figure 27. As shown in Figure 27, with the synchronous FETs turned on, the converter still runs at continuous mode (CCM) with a large duty cycle even at no-load operation. Figure 28 shows the operation waveforms with synchronous FETs off. In this case, the synchronous FETs block any negative current, which forces the converter to run at discontinuous mode (DCM) cutting down the duty cycle significantly. 24 FIGURE 25. TRANSFORMER WAVEFORMS AT VIN=48V, VOUT=3.3V, AND IOUT=60A. CHANNEL 4: PRIMARY CURRENT (IP); CHANNEL 3: PRIMARY VOLTAGE (VP); CHANNEL 2: SECONDARY VOLTAGE (VS) 3 2 4 FIGURE 26. TRANSFORMER WAVEFORMS AT VIN=48V, VOUT=3.3V, AND IOUT=30A. CHANNEL 4: PRIMARY CURRENT (IP); CHANNEL 3: PRIMARY VOLTAGE (VP); CHANNEL 2: SECONDARY VOLTAGE (VS) Application Note 1002 ZVS TRANSITIONS 3 2 4 FIGURE 27. TRANSFORMER WAVEFORMS AT VIN=48V, VOUT=3.3V, AND IOUT=0A (SYN ON). CHANNEL 4: PRIMARY CURRENT (IP); CHANNEL 3: PRIMARY VOLTAGE (VP); CHANNEL 2: SECONDARY VOLTAGE (VS) Figures 30 to 34 show resonant transitions for the lower FET in various situations, and they are taken by shortening the loop that is used to measure the primary current. Table 5 summarizes the ZVS conditions of one converter for various input and output voltages (which do not apply to every converter since the ZVS conditions of each converter are heavily dependant upon the leakage inductance and the output capacitance of the primary switches). In the nominal 48V input and 3.3V output condition, the converter loses ZVS transitions below 62% of full load, as shown in Figure 31. At the low line (36V) situation, ZVS transitions extend to 42% of full load, as shown in Figure 33, since the energy stored in the parasitic capacitance is proportional to VIN2 and reaches its minimum. On the other hand, the high line (75V) completely loses ZVS transitions even at 100% load since the energy stored in the parasitic capacitance reaches its maximum and the energy in the commutating inductance is not enough to resonate the tank to the valley, as shown in Figure 34. TABLE 5. ZVS LOAD RANGE 3 VIN\VOUT 2.64V 3.30V 3.63V 36V