ISL6131 ISL6132 FN9119 PUB95 MO-220 ISL6131IR ISL6132IR ISL6131IRZA ISL6132IRZA

® Data Sheet July 22, 2005 Multiple Voltage Supervisory ICs Features The ISL6131 and ISL6132 are a family of high accuracy

ISL6131 ISL6131, ISL6132 ISL6132 ® Data Sheet July 22, 2005 Multiple Voltage Supervisory ICs Features The ISL6131 ISL6131 and ISL6132 ISL6132 are a family of high accuracy multi voltage supervisory ICs designed to monitor voltages greater than 0.7V in applications ranging from microprocessors to industrial power systems. The ISL6131 ISL6131 is an undervoltage four supply supervisor whereas the ISL6132 ISL6132 is a two voltage supervisor monitoring both for undervoltage (UV) and overvoltage (OV) conditions. FN9119 FN9119.3 · Operates from 1.5V to 5.5V Supply Voltage Both ICs feature four external resistor programmable voltage monitoring (VMON) inputs each with a related STATUS output that individually reports the related monitor input condition. In addition there is a PGOOD (power good) signal that asserts high when the STATUS outputs are in their correct state. There is a stability delay of approximately 160ms to ensure that the monitored supply is stable before STATUS and PGOOD are released to go high. The PGOOD and STATUS outputs are open-drain to allow ORing of the signals and interfacing to a wide range of logic levels. STATUS and PGOOD outputs are guaranteed to be valid with IC bias lower than 1V eliminating concern about STATUS and PGOOD outputs during IC bias up and down. VMON inputs are designed to ignore momentary transients on the monitored supplies. PART NUMBER · 150ms STATUS/PGOOD Stability Time Delay · Four Individual Open Drain STATUS Outputs · Guaranteed STATUS/PGOOD Valid to VDD Vuv_vth. This delay is for stabilization of monitored voltages. STATUS will deassert and pull low upon VMON not being satisfied for about 30µs. 6 NA STATUS_C 7 NA STATUS_D NA 5 OVSTATUS_1 NA 2 UVSTATUS_1 NA 6 UVSTATUS_2 NA 7 OVSTATUS_2 1 1 EN1 On ISL6131 ISL6131 provides 4 voltage UV function enabling/disabling input. Internally pulled up to VDD. Controls monitor 1 (AB pair) on ISL6132 ISL6132. NA 11 EN2 On ISL6132 ISL6132, controls monitor 2 (CD pair) voltage, voltage monitoring function enabling input, pulled up to VDD. NC 3, 4, 8, 13, 15, 16, 18, 19, 21, 22 On the ISL6131 ISL6131 these inputs provide for a programmable UV threshold referenced to an internal 0.633V. The related STATUS output will assert once the related input > internal reference voltage. On the ISL6132 ISL6132, these inputs provide for a programmable UV and OV threshold referenced to an internal 0.633V reference. In the `AB' pair VMON_A is the UV input and VMON_B is the OV input. In the `CD' pair VMON_C is the UV input and VMON_D is the OV input. These inputs have a 30µs glitch filter to prevent PGOOD reset due to a transient. On the ISL6132 ISL6132 the STATUS outputs indicate compliance with a high output state for each pair of monitors. No Connect 3 FN9119 FN9119.3 July 22, 2005 ISL6131 ISL6131, ISL6132 ISL6132 Absolute Maximum Ratings Thermal Information VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +6.0V VMON, ENABLE, STATUS, PGOOD . . . . . . . . . . -0.3V to VDD+0.3V ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2kV (HBM) Thermal Resistance (Typical, Notes 1, 2) JA (°C/W) JC (°C/W) 4x4 QFN Package . . . . . . . . . . . . . . . . 48 9 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150°C Maximum Storage Temperature Range . . . . . . . . . . . -65°C to 150°C Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300°C (QFN - Leads Only) Operating Conditions VDD Supply Voltage Range . . . . . . . . . . . . . . . . . . . . +1.5V to +5.5V Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . . . .-40°C to 85°C CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 1. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 TB379 for details. 2. For JC, the "case temp" location is the center of the exposed metal pad on the package underside. 3. All voltages are relative to GND, unless otherwise specified. Electrical Specifications Nominal VDD = 1.5V to +5V, TA = TJ = -40°C - 85°C, Unless Otherwise Specified PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT 619 633 647 mV - 40 - nV/°C VMON/ENABLE INPUTS VMON Threshold VVMONvth TJ = 25°C VMON Threshold Temp. Coeff. TCVMONvth VMON Hysteresis VVMONhys - 10 - mV VMON Glitch Filter Tfil - 30 - µs VMON Minimum Input Impedance Zin_min TJ from -40°C to +85°C Tj = 40°C, VMON within 63mV of VVMONvth 8 M ENABLE L2H, Delay to STATUS & PGOOD VMON valid, EN high to STATUS & PG high - 160 - ms EN H2L, Delay to PGOOD EN low to PGOOD low - - 0.1 µs EN H2L, Delay to STATUS EN low to STATUS low - 13 - µs ENABLE Pull-up Voltage EN open - VDD - V - VDD/2 - V ENABLE Threshold Voltage VENVTH STATUS/PGOOD OUTPUTS STATUS Pull-Down Current IRSTpd RST = 0.1V - 88 - mA STATUS/PGOOD Delay after VMON Valid TdelST VMON > VUVvth to STATUS = 0.2V - 160 - ms Measured at VDD = 1.0V - 0.04 0.1 V STATUS/PGOOD Output Low Vol BIAS IC Supply Current IVDD_5.5V VDD = 5V - 170 - µA IC Supply Current IVDD_3.3V VDD = 3.3V - 145 - µA IC Supply Current IVDD_1.5V VDD = 1.5V - 100 - µA VDD Power On VDD_POR VDD high to low - 0.89 1 V VDD_LO VDD low to high - 0.91 - V VDD Power On Lock Out 4 FN9119 FN9119.3 July 22, 2005 ISL6131 ISL6131, ISL6132 ISL6132 Description and Operation The ISL6131 ISL6131 is a four voltage high accuracy supervisory IC designed to monitor multiple voltages greater than 0.7V relative to PIN 10 of the IC. Upon VDD bias power up, the STATUS and PGOOD outputs are held correctly low once VDD is as low as 1V. Once biased to 1.5V the IC continuously monitors from one to four voltages independently through external resistor dividers comparing each voltage monitoring (VMON) pin voltage to an internal 0.633V (VVMONvth) reference. With the EN input driven high or open as each VMON input rises above VVMONvth a timer is set to ensure ~160ms of continuous compliance then the related STATUS output is released to be pulled high. The STATUS outputs are opendrain to allow ORing of these signals and interfacing to a logic high level up to VDD. The STATUS are designed to reject short transients (~30µs) on the VMON inputs. Once all STATUS outputs are high a power good (PGOOD) output signal is generated high to indicate all the monitored voltages are greater than minimum compliance level. Once any VMON input falls below VVMONvth for longer than the glitch filter time both the PGOOD and the related STATUS output are pulled low. The other STATUS outputs will remain high as long as their corresponding VMON voltage remains valid and the PGOOD validation process is reset. Figure 1 illustrates ISL6131 ISL6131 typical application schematic and Figure 3 is an operational timing diagram. See Figures 10 to 17 for ISL6131 ISL6131 function and performance. Figures 10 and 11 show the VDD rising along with STATUS and PGOOD response. Figures 12 and 13 illustrate VMON falling below VVMONvth and Figure 14 illustrates VMON rising above VVMONvth with STATUS and PGOOD response. Figure 15 shows the VDD failing with STATUS and PGOOD response. Figures 16 and 17 illustrate ENABLE to STATUS and PGOOD timing. If less than four voltages are being monitored, connect the unused VMON pins to VDD for proper operation. All unused STATUS outputs can be left open. The ISL6132 ISL6132 is a dual voltage monitor for under and overvoltage compliance. Figure 2 illustrates the typical ISL6132 ISL6132 implementation schematic and Figure 4 is the operational timing diagram. There are 2 pairs of monitors each with an undervoltage (UVMON) input and overvoltage (OVMON) input along with with associated STATUS and PGOOD outputs. Upon VDD bias power up, the STATUS and PGOOD outputs are held correctly low once VDD is as low as 1V. Once biased to 1.5V the IC continuously monitors the voltage through external resistor dividers comparing each VMON pin voltage to an internal 0.633V reference. At proper bias the OVSTATUS are pulled high and the UVSTATUS and 5 PGOOD are pulled low. Once the UVMON input > the VMON Vth continuously for ~160ms, its associated STATUS output will release high indicating that the minimum voltage condition has been met. As both UVMON and OVMON inputs are satisfied the PGOOD output is released to go high indicating that the monitored voltage is within the specified window. Figure 18 illustrates this performance for a 4V to 5V window. When VMON does not satisfy its voltage high or low criteria for more than the glitch filter time, the associated STATUS and PGOOD are pulled low. Figures 19 and 20 illustrate this performance for a 4V to 5V compliant window. Figures 21-23 illustrate the VMON glitch filter timing to STATUS and PGOOD notification and transient immunity. The ENABLE input when pulled low allows for monitoring and reporting function to be disabled. Figure 24 shows ENABLE high to PGOOD timing for compliant voltage. When choosing resistors for the divider remember to keep the current through the string bounded by power loss tolerance at the top end and noise immunity at the bottom end. For most applications total divider resistance in the 10k -100k range is advisable with 1% tolerance resistors being used to reduce monitoring error. Referencing Figures 1 and 2, choosing the two resistor values is straightforward for the ISL6131 ISL6131 as the ratio of resistance should equal the ratio of the desired trip voltage to the internal reference, 0.633V). For the ISL6131 ISL6131, two dividers of two resistors each can be employed to monitor the OV and UV levels for each voltage. Otherwise, use a single three resistor string for each voltage. In the three resistor divider string the ratio of the desired over voltage trip point to the internal reference is equal to the ratio of the two upper resistors to the lowest (gnd connected) resistor. The desired under voltage trip point ratio to the internal reference voltage is equal to the ratio of the uppermost (voltage connected) resistor to the lower two resistors. An example follows; 1. Establish lower and upper trip level: 3.3V ±20% or 2.64V (UV) and 3.96V (OV) 2. Establish total resistor string value: 10k, Ir = divider current 3. (Rm+Rl)*Ir = 0.623V @ UV and Rl * Ir = 0.633V @ OV 4. Rm+Rl = 0.623V / Ir @ UV => Rm+Rl = 0.623V / (2.64V /10k) = 2.359k 5. Rl = 0.633V / Ir @ OV => Rl = 0.633V /(3.96V/10k) = 1.598k 6. Rm = 2.359k - 1.598k = 0.761k 7. Ru = 10k - 2.397k = 7.641k 8. Choose standard value resistors that most closely approximate these ideal values. Choosing a different total divider resistance value may yield a more ideal ratio with available resistors values. FN9119 FN9119.3 July 22, 2005 ISL6131 ISL6131, ISL6132 ISL6132 VMONVth A B VMON INPUT VOLTAGE C D C D STSDLY STSDLY Tfil STSDLY STSDLY STSDLY A STATUS OUTPUTS B C C D PGOOD OUTPUT EN INPUT FIGURE 3. ISL6131 ISL6131 OPERATIONAL DIAGRAM OVERVOLTAGE LIMIT OV TdelST Tfil UNDERVOLTAGE LIMIT VVMONVth to STATUS high ensures stability at each step prior to subsequent turn7 EN VIN EN ABC STATUS PGOOD VOUT DC-DC_A VOUT DC-DC_B VOUT DC-DC_C VMON_A VMON_D ISL6131 ISL6131 VMON_C VDD ENABLE VMON_B GND FIGURE 7. ISL6131 ISL6131 `LOSSLESS' SEQUENCING CONFIGURATION Using the ISL6131 ISL6131 for System Voltage and Over Temperature Monitoring Being a multivoltage monitoring IC the ISL6131 ISL6131 can also be used to monitor over temperature as well as voltage for a more complete coverage of system health. Using a Negative Temperature Coefficient (NTC) passive device in place of one of the resistors in a VMON divider provides over temperature monitoring either locally or remotely. Evaluations of this application configuration have involved the QT0805T-202J QT0805T-202J, QT0805Y-502J QT0805Y-502J and QT0805Y-103J QT0805Y-103J NTCs from Quality Thermistor. ISL6131 ISL6131 over temperature monitoring is not as accurate as specific temperature monitor ICs but this implementation provides a cost efficient solution with 5% tolerances achievable. See Figures 8 - 9 for over temp sensing configuration and operation results. In this example, the desired maximum temp is 100°C. The QT0805Y-103J QT0805Y-103J NTC was placed at the end of 3 feet of twisted pair wire to emulate a remote sensing application. From the Quality Thermistor data sheet, this NTC device has a +25°C value of 10K and at +100°C a value of 0.923K. An accompanying standard value resistor of 3.83K was chosen for divider so that at 100°C, VMON ~0.633V with the bias voltage at 3.3V. FN9119 FN9119.3 July 22, 2005 ISL6131 ISL6131, ISL6132 ISL6132 The resulting falling VMON trip point with configuration shown is ~0.634V, with ~0.642V for rising which equates to ~95°C for under temperature and ~97°C for over temperature respectively. Choosing the standard resistor value above and below R1 allows for small adjustments in the temperature trip point. The low ISL6131 ISL6131 VMON temperature coefficient makes this a viable and low cost addition to complete system monitoring. TEMP INDICATOR TEMP (°C) VMON (V) TEMP STATUS 25 2.36 H = Under Temp 50 1.61 H = Under Temp 75 1.01 H = Under Temp 95 0.67 H = Under Temp 100 0.61 L = Over Temp 105 0.54 L = Over Temp STATUS 3.3V VMON 0.1V/DIV VDD 3.83k R1 VMON T ISL6131 ISL6131 QT0805Y-103J QT0805Y-103J (REMOTE HEAT SOURCE LOCATION) Low = OVER TEMP GND TEMP STATUS 5V/DIV FIGURE 8. ISL6131 ISL6131 OVER TEMP SENSING CONFIGURATION 10s/DIV FIGURE 9. ISL6132 ISL6132 OVER TEMP SENSING RESULT Functional and Performance Waveforms STATUS OUTPUTS PULLED-UP TO 1.5V VDD RISING STATUS OUTPUTS TO VDD VDD RISING PGOOD PGOOD 1V/DIV 100µs/DIV FIGURE 10. ISL6131 ISL6131 VDD RISING 8 1V/DIV 200µs/DIV FIGURE 11. ISL6131 ISL6131 VDD RISING WITH PULL-UP FN9119 FN9119.3 July 22, 2005 ISL6131 ISL6131, ISL6132 ISL6132 Functional and Performance Waveforms (Continued) VMON FALLING BELOW UV Vth (0.1V/DIV) UV Vth 0.63V VMON FALLING BELOW UV Vth (0.1V/DIV) UV Vth 0.63V UNRELATED STATUS OUTPUTS UNRELATED STATUS OUTPUTS RELATED STATUS OUTPUT RELATED STATUS OUTPUT PGOOD PGOOD 1V/DIV 40ms/DIV FIGURE 12. ISL6131 ISL6131 VMON FALLING TO PGOOD 1V/DIV 10ms/DIV FIGURE 13. ISL6131 ISL6131 VMON FALLING TO PGOOD VMON RISING ABOVE UV Vth (0.1V/DIV) UV Vth 0.63V VDD FALLING UNRELATED STATUS OUTPUTS STATUS OUTPUTS RELATED STATUS OUTPUT PGOOD PGOOD 1V/DIV 20ms/DIV 1V/DIV FIGURE 14. ISL6131 ISL6131 UV RISING TO PGOOD 40ms/DIV FIGURE 15. ISL6131 ISL6131 VDD FALLING ENABLE STATUS ENABLE STATUS PGOOD PGOOD 2V/DIV 20ms/DIV FIGURE 16. ISL6131 ISL6131 ENABLE L2H TO PGOOD 9 2V/DIV 2µs/DIV FIGURE 17. ISL6131 ISL6131 EN H2L TO PGOOD FN9119 FN9119.3 July 22, 2005 ISL6131 ISL6131, ISL6132 ISL6132 Functional and Performance Waveforms (Continued) MONITORING 4V TO 5V MONITORING 4V TO 5V OV STATUS VDD RISING MONITORED VOLTAGE FALLING OV STATUS RISING UV/PGOOD STATUS RISING 1V/DIV 40ms/DIV PGOOD AND UV STATUS PULLED LOW 1V/DIV FIGURE 18. ISL6132 ISL6132 TURN-ON 10ms/DIV FIGURE 19. ISL6132 ISL6132 IN UV CONDITION MONITORING 4V TO 5V MONITORING 4V TO 5V UV STATUS VMON FALLING (1V/DIV) MONITORED VOLTAGE RISING 4V MIN LIMIT UV STATUS PGOOD AND OV STATUS PULLED LOW OV STATUS PGOOD 1V/DIV 10ms/DIV FIGURE 20. ISL6132 ISL6132 IN OV CONDITION 5V/DIV 10µs/DIV FIGURE 21. ISL6132 ISL6132 UV GLITCH FILTER TIMING MONITORING 4V TO 5V VMON RISING (1V/DIV) 5V MAX LIMIT VMON 5.5V TO 3.5V UV STATUS UV, OV STATUS & PGOOD OV STATUS 5VOUT PGOOD 5V/DIV 10µs/DIV FIGURE 22. ISL6132 ISL6132 OV GLITCH FILTER TIMING 10 8µs/DIV FIGURE 23. ISL6132 ISL6132 GLITCH FILTER TRANSIENT IMMUNITY FN9119 FN9119.3 July 22, 2005 ISL6131 ISL6131, ISL6132 ISL6132 Functional and Performance Waveforms (Continued) ENABLE PGOOD OV, UV STATUS 1V/DIV 20ms/DIV FIGURE 24. ISL6132 ISL6132 ENABLE TO PGOOD FIGURE 25. ISL613XSUPEREVAL2 ISL613XSUPEREVAL2 PHOTOGRAPH 11 FN9119 FN9119.3 July 22, 2005 ISL6131 ISL6131, ISL6132 ISL6132 VDD IN2 JP1 R16 R15 IN4 IN3 R17 R18 IN1 1 R1 R3 R5 R7 2 3 STATUS 4 VDD C1 VMON2 (OV1) R9 VMON4 (OV2) R2 VMON3 (UV2) R4 VMON1 (UV1) R6 ISL6131 ISL6131, ISL6132 ISL6132 R8 D4 R10 D3 PGOOD1 PGOOD2 GND EN1 EN2 FIGURE 26. ISL613XSUPEREVAL2 ISL613XSUPEREVAL2 CHANNEL 1 SCHEMATIC TABLE 1. ISL6131SUPEREVAL2 ISL6131SUPEREVAL2 BOARD CHANNEL 1 COMPONENT LISTING COMPONENT DESIGNATOR COMPONENT FUNCTION COMPONENT DESCRIPTION DUT1 ISL6131 ISL6131, Quad Under Voltage Supervisor in socket Intersil, ISL6131IR ISL6131IR Quad Under Voltage Supervisor DUT2 ISL6132 ISL6132, Dual Over & Under Voltage Supervisor in bag Intersil, ISL6132IR ISL6132IR Dual Over & Under Voltage Supervisor R1A IN2 to VMONB (OV1) Resistor for Divider String 8.45k 1%, 0402 R2A VMONB (OV1) to GND Resistor for Divider String 1.47k 1%, 0402 R7A IN1 to VMONA (UV1) Resistor for Divider String 7.68k 1%, 0402 R8A VMONA (UV1) to GND Resistor for Divider String 2.26k 1%, 0402 R3A IN4 to VMOND (OV2) Resistor for Divider String 6.98k 1%, 0402 R4A VMOND (OV2) to GND Resistor for Divider String 3.01k 1%, 0402 R5A IN3 to VMONC (UV2) Resistor for Divider String 4.99k 1%, 0402 R6A VMONC (UV2) to GND Resistor for Divider String 4.99k 1%, 0402 STATUS Pull-up Resistors 5.1k 10%, 0402 C1A Decoupling Capacitor 0.1µF, 0805 D3, D4 PGOOD# INDICATOR SMD RED LED R15-R18 R15-R18 12 FN9119 FN9119.3 July 22, 2005 ISL6131 ISL6131, ISL6132 ISL6132 Quad Flat No-Lead Plastic Package (QFN) Micro Lead Frame Plastic Package (MLFP) L24.4x4 24 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE (COMPLIANT TO JEDEC MO-220VGGD-2 MO-220VGGD-2 ISSUE C) MILLIMETERS SYMBOL MIN NOMINAL MAX NOTES A 0.80 0.90 1.00 - A1 - - 0.05 - A2 - - 1.00 A3 b 0.18 D 0.23 9 0.30 5, 8 4.00 BSC D1 D2 9 0.20 REF - 3.75 BSC 1.95 2.10 9 2.25 7, 8 E 4.00 BSC - E1 3.75 BSC 9 E2 1.95 e 2.10 2.25 7, 8 0.50 BSC - k 0.25 - - - L 0.30 0.40 0.50 8 L1 - - 0.15 10 N 24 2 Nd 6 3 Ne 6 3 P - - 0.60 9 - - 12 9 Rev. 2 10/02 NOTES: 1. Dimensioning and tolerancing conform to ASME Y14.5-1994. 2. N is the number of terminals. 3. Nd and Ne refer to the number of terminals on each D and E. 4. All dimensions are in millimeters. Angles are in degrees. 5. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. 7. Dimensions D2 and E2 are for the exposed pads which provide improved electrical and thermal performance. 8. Nominal dimensions are provided to assist with PCB Land Pattern Design efforts, see Intersil Technical Brief TB389 TB389. 9. Features and dimensions A2, A3, D1, E1, P & are present when Anvil singulation method is used and not present for saw singulation. 10. Depending on the method of lead termination at the edge of the package, a maximum 0.15mm pull back (L1) maybe present. L minus L1 to be equal to or greater than 0.3mm. All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 13 FN9119 FN9119.3 July 22, 2005