ISL6115 ISL6116 ISL6117 ISL6120 FN9100 ISL6115CB ISL61 ISL6116CB ISL6117CB - Datasheet Archive

 

® Data Sheet February 6, 2007 FN9100.4 Power Distribution Controllers Features This family of fully featured hot swap power

 

ISL6115 ISL6115, ISL6116 ISL6116, ISL6117 ISL6117, ISL6120 ISL6120 ® Data Sheet February 6, 2007 FN9100 FN9100.4 Power Distribution Controllers Features This family of fully featured hot swap power controllers targets applications in the +2.5V to +12V range. The ISL6115 ISL6115 is for +12V control, the ISL6116 ISL6116 for +5V, the ISL6117 ISL6117 for +3.3V and the ISL6120 ISL6120 for +2.5V control applications. Each has a hard wired undervoltage (UV) monitoring and reporting threshold level approximately 80% of the aforementioned voltage. · HOT SWAP Single Power Distribution Control (ISL6115 ISL6115 for +12V, ISL6116 ISL6116 for +5V, ISL6117 ISL6117 for +3.3V and ISL6120 ISL6120 for +2.5V) The ISL6115 ISL6115 has an integrated charge pump allowing control of up to +16V rails using an external N-Channel MOSFET whereas the other devices utilize the +12V bias voltage to fully enhance the N-channel pass FET. All ICs feature programmable overcurrent (OC) detection, current regulation (CR) with time delay to latch-off and soft-start. · Rail to Rail Common Mode Input Voltage Range (ISL6115 ISL6115) The current regulation level is set by 2 external resistors; RISET sets the CR Vth and the other is a low ohmic sense element across, which the CR Vth is developed. The CR duration is set by an external capacitor on the CTIM pin, which is charged with a 20µA current once the CR Vth level is reached. If the voltage on the CTIM cap reaches 1.9V the IC then quickly pulls down the GATE output latching off the pass FET. · Protection During Turn On This family although designed for high side switch control the ISL6116 ISL6116, ISL6117 ISL6117, ISL6120 ISL6120 can also be used in a low side configuration for control of much higher voltage potentials. Applications · Overcurrent Fault Isolation · Programmable Current Regulation Level · Programmable Current Regulation Time to Latch-Off · Internal Charge Pump Allows the use of N-Channel MOSFET for +12V control (ISL6115 ISL6115) · Undervoltage and Overcurrent Latch Indicators · Adjustable Turn-On Ramp · Two Levels of Overcurrent Detection Provide Fast Response to Varying Fault Conditions · 1µs Response Time to Dead Short · Pb-Free Plus Anneal Available (RoHS Compliant) · Tape & Reel Packing with `-T' Part Number Suffix · Power Distribution Control · Hot Plug Components and Circuitry Ordering Information TEMP. PKG. RANGE (°C) PACKAGE DWG. # Pinout PART NUMBER PART MARKING ISL6115CB ISL6115CB* ISL61 ISL61 15CB 0 to +85 8 Ld SOIC M8.15 ISL6116CB ISL6116CB* ISL61 ISL61 16CB 0 to +85 8 Ld SOIC M8.15 ISL6117CB ISL6117CB* ISL61 ISL61 17CB 0 to +85 8 Ld SOIC M8.15 ISET 1 8 PWRON ISL6120CB ISL6120CB* ISL61 ISL61 20CB 0 to +85 8 Ld SOIC M8.15 ISEN 2 7 PGOOD ISL6115CBZA ISL6115CBZA* 6115 CBZ (Note) 0 to +85 8 Ld SOIC (Pb-free) M8.15 GATE 3 6 CTIM VSS 4 5 VDD ISL6116CBZA ISL6116CBZA* 6116 CBZ (Note) 0 to +85 8 Ld SOIC (Pb-free) M8.15 ISL6117CBZA ISL6117CBZA* 6117 CBZ (Note) 0 to +85 8 Ld SOIC (Pb-free) M8.15 ISL6120CBZA ISL6120CBZA* 6120 CBZ (Note) 0 to +85 8 Ld SOIC (Pb-free) M8.15 ISL6115 ISL6115, ISL6116 ISL6116, ISL6117 ISL6117, ISL6120 ISL6120 (8 LD SOIC) TOP VIEW *Add "-T" suffix for tape and reel. NOTE: Intersil Pb-free products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which is compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J Std-020B. 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2004-2007. All Rights Reserved All other trademarks mentioned are the property of their respective owners. ISL6115 ISL6115, ISL6116 ISL6116, ISL6117 ISL6117, ISL6120 ISL6120 Application One - High Side Controller LOAD + Application Two - Low Side Controller +VBUS - LOAD 1 8 2 7 PWRON 1 2 3 4 PGOOD 4 3 ISL6115 ISL6115 ISL6116 ISL6116 ISL6117 ISL6117 ISL6120 ISL6120 6 OC 5 ISL6116/7/20 ISL6116/7/20 PWRON 8 7 6 5 +12V +V supply to be controlled 12V REG OC 2 February 6, 2007 ISL6115 ISL6115, ISL6116 ISL6116, ISL6117 ISL6117, ISL6120 ISL6120 Simplified Block Diagram VDD + POR + QN 8V ISET R + R Q UV PWRON S + VREF - ENABLE 12V ISEN PGOOD ISL611X ISL611X UV DISABLE 20µA CLIM OC GATE FALLING EDGE DELAY 10µA + - 7.5K + + 1.86V WOCLIM 18V - ENABLE VSS CTIM + - 20µA RISING EDGE PULSE 18V VDD Pin Descriptions PIN # SYMBOL FUNCTION 1 ISET Current Set Connect to the low side of the current sense resistor through the current limiting set resistor. This pin functions as the current limit programming pin. 2 ISEN Current Sense Connect to the more positive end of sense resistor to measure the voltage drop across this resistor. 3 GATE External FET Gate Drive Pin Connect to the gate of the external N-Channel MOSFET. A capacitor from this node to ground sets the turn-on ramp. At turn-on this capacitor will be charged to VDD +5V (ISL6115 ISL6115) and to VDD (ISL6116 ISL6116, ISL6117 ISL6117, ISL6120 ISL6120) by a 10A current source. 4 VSS Chip Return 5 VDD Chip Supply 12V chip supply. This can be either connected directly to the +12V rail supplying the switched load voltage or to a dedicated VSS +12V supply. 6 CTIM Current Limit Timing Capacitor Connect a capacitor from this pin to ground. This capacitor determines the time delay between an overcurrent event and chip output shutdown (current limit time-out). The duration of current limit time-out is equal to 93k x CTIM. 7 PGOOD Power Good Indicator Indicates that the voltage on the ISEN pin is satisfactory. PGOOD is driven by an open drain N-Channel MOSFET and is pulled low when the output voltage (VISEN) is less than the UV level for the particular IC. 8 PWRON Power ON PWRON is used to control and reset the chip. The chip is enabled when PWRON pin is driven high to a maximum of 5V or is left open. After a current limit time out, the chip is reset by a low level signal applied to this pin. This input has 20A pull up capability. 3 DESCRIPTION February 6, 2007 ISL6115 ISL6115, ISL6116 ISL6116, ISL6117 ISL6117, ISL6120 ISL6120 Absolute Maximum Ratings TA = +25°C Thermal Information VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +16V GATE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to VDD+8V ISEN, PGOOD, PWRON, CTIM, ISET. . . . . . . -0.3V to VDD + 0.3V ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5kV Thermal Resistance (Typical, Note 1) Operating Conditions JA (°C/W) SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Maximum Junction Temperature (Plastic Package) . . . . . . . +150°C Maximum Storage Temperature Range . . . . . . . . . .-65°C to +150°C Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . +300°C (SOIC - Lead Tips Only) VDD Supply Voltage Range . . . . . . . . . . . . . . . . . . . . . . +12V ±15% Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . . . . 0°C to +85°C CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 1. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. (See Tech Brief, #TB379 TB379.1 for details.) 2. All voltages are relative to GND, unless otherwise specified 3. G.N.T. Guaranteed by design and characterization but Not Tested. Electrical Specifications VDD = 12V, TA = TJ = 0°C to +85°C, Unless Otherwise Specified PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS 18.5 20 21.5 A TJ = +15°C to +55°C 19 20 21 A CURRENT CONTROL ISET Current Source IISET_ft ISET Current Source IISET_pt Current Limit Amp Offset Voltage Vio_ft VISET - VISEN -6 0 6 mV Current Limit Amp Offset Voltage Vio_pt VISET - VISEN, TJ = +15°C to +55°C -2 0 2 mV GATE DRIVE GATE Response Time To Severe OC pd_woc_amp VGATE to 10.8V - 100 - ns GATE Response Time to Overcurrent pd_oc_amp VGATE to 10.8V - 600 - ns IGATE VGATE to = 6V 8.4 10 11.6 A Overcurrent 45 75 - mA Severe Overcurrent 0.5 0.8 - A 9.2 9.6 10 V VDD + 4.5V VDD + 5V - V GATE Turn-On Current GATE Pull Down Current OC_GATE_I_4V GATE Pull Down Current (3) WOC_GATE_I_4V ISL6115 ISL6115 Undervoltage Threshold ISL6115 ISL6115 GATE High Voltage 12VUV 12VUV_VTH 12VG GATE Voltage ISL6116 ISL6116 Undervoltage Threshold 5VUV_VTH 4.0 4.35 4.5 V ISL6117 ISL6117 Undervoltage Threshold 3VUV_VTH 2.4 2.6 2.8 V ISL6120 ISL6120 Undervoltage Threshold 2VUV_VTH 1.8 1.85 1.9 V VDD - 1.5V VDD - V - 3 5 mA ISL6116 ISL6116, 17, 20 GATE High Voltage VG GATE Voltage BIAS VDD Supply Current IVDD VDD POR Rising Threshold VDD_POR_L2H VDD Low to High 7.8 8.4 9 V VDD POR Falling Threshold VDD_POR_H2L VDD High to Low 7.5 8.1 8.7 V VDD POR Threshold Hysteresis VDD_POR_HYS VDD_POR_L2H - VDD_POR_H2L 0.1 0.3 0.6 V PWRON Pin Open 2.7 3.2 - V PWRON Pull-Up Voltage PWRN_V PWRON Rising Threshold PWR_Vth 1.4 1.7 2.0 V PWRON Hysteresis PWR_hys 130 170 250 mV PWRON Pull-Up Current PWRN_I 9 17 25 A 4 February 6, 2007 ISL6115 ISL6115, ISL6116 ISL6116, ISL6117 ISL6117, ISL6120 ISL6120 Electrical Specifications VDD = 12V, TA = TJ = 0°C to +85°C, Unless Otherwise Specified PARAMETER SYMBOL (Continued) TEST CONDITIONS MIN TYP MAX UNITS 16 20 23 A - 20 - mA CURRENT REGULATION DURATION/POWER GOOD CTIM Charging Current CTIM_ichg0 VCTIM = 0V CTIM Fault Pull-Up Current (Note 3) Power Good Pull Down Current CTIM_Vth CTIM Voltage 1.3 1.8 2.3 V PG_Ipd Current Limit Time-Out Threshold Voltage VOUT = 0.5V - 8 - mA Description and Operation The members of this family are single power supply distribution controllers for generic hot swap applications across the +2.5V to +12V supply range. The ISL6115 ISL6115 is targeted for +12V switching applications whereas the ISL6116 ISL6116 is targeted for +5V, the ISL6117 ISL6117 for +3.3V and the ISL6120 ISL6120 for +2.5V applications. Each IC has a hardwired undervoltage (UV) threshold level approximately 17% lower than the stated voltages. These ICs feature a highly accurate programmable overcurrent (OC) detecting comparator, programmable current regulation (CR) with programmable time delay to latch off, and programmable soft-start turn-on ramp all set with a minimum of external passive components. The ICs also include severe OC protection that immediately shuts down the MOSFET switch should a rapid load current transient such as a near dead short cause the CR Vth to exceed the programmed level by 150mV. Additionally, the ICs have a UV indicator and an OC latch indicator. The functionality of the PGOOD feature is enabled once the IC is biased, monitoring and reporting any UV condition on the ISEN pin. Upon initial power up, the IC can either isolate the voltage supply from the load by holding the external N-Channel MOSFET switch off or apply the supply rail voltage directly to the load for true hot swap capability. The PWRON pin must be pulled low for the device to isolate the power supply from the load by holding the external N-channel MOSFET off. With the PWRON pin held high or floating the IC will be in true hot swap mode. In both cases the IC turns on in a softstart mode protecting the supply rail from sudden in-rush current. At turn-on, the external gate capacitor of the N-Channel MOSFET is charged with a 10A current source resulting in a programmable ramp (soft-start turn-on). The internal ISL6115 ISL6115 charge pump supplies the gate drive for the 12V supply switch driving that gate to ~VDD +5V, for the other three ICs the gate drive voltage is limited to the chip bias voltage, VDD. Load current passes through the external current sense resistor. When the voltage across the sense resistor exceeds the user programmed CR voltage threshold value, (see Table 1 for RISET programming resistor value and resulting nominal current regulation threshold voltage, VCR) the 5 controller enters its current regulation mode. At this time, the time-out capacitor, on CTIM pin is charged with a 20A current source and the controller enters the current limit time to latchoff period. The length of the current limit time to latch-off duration is set by the value of a single external capacitor (see Table 2) for CTIM capacitor value and resulting nominal current limited time out to latch-off duration placed from the CTIM pin (pin 6) to ground. The programmed current level is held until either the OC event passes or the time out period expires. If the former is the case then the N-Channel MOSFET is fully enhanced and the CTIM capacitor is discharged. Once CTIM charges to 1.87V, signaling that the time out period has expired an internal latch is set whereby the FET gate is quickly pulled to 0V turning off the N-Channel MOSFET switch, isolating the faulty load. TABLE 1. RISET RESISTOR NOMINAL OC VTH 10k 200mV 4.99k 100mV 2.5k 50mV 750 15mV NOTE: Nominal Vth = RISET x 20A. TABLE 2. CTIM CAPACITOR NOMINAL CURRENT LIMITED PERIOD 0.022F 2ms 0.047F 4.4ms 0.1F 9.3ms NOTE: Nominal time-out period = CTIM x 93k. This IC responds to a severe overcurrent load (defined as a voltage across the sense resistor >150mV over the OC Vth set point) by immediately driving the N-Channel MOSFET gate to 0V in about 10s. The gate voltage is then slowly ramped up turning on the N-Channel MOSFET to the programmed current regulation level; this is the start of the time out period. Upon a UV condition the PGOOD signal will pull low when tied high through a resistor to the logic or VDD supply. This pin is a UV fault indicator. For an OC latch off indication, monitor CTIM, pin 6. This pin will rise rapidly from 1.9V to VDD once the time out period expires. See Figures 12 to 16 for waveforms relevant to text. The IC is reset after an OC latch-off condition by a low level on the PWRON pin and is turned on by the PWRON pin being driven high. February 6, 2007 ISL6115 ISL6115, ISL6116 ISL6116, ISL6117 ISL6117, ISL6120 ISL6120 Application Considerations 0.005 1% LOAD 0.001µF 1.47k 1% 2k 1 2 3 RCL 4 During the soft-start and the time-out delay duration with the IC in its current limit mode, the VGS of the external N-Channel MOSFET is reduced driving the MOSFET switch into a (linear region) high rDS(ON) state. Strike a balance between the CR limit and the timing requirements to avoid periods when the external N-Channel MOSFETs may be damaged or destroyed due to excessive internal power dissipation. Refer to the MOSFET SOA information in the manufacturer's data sheet. 1.58k 1W 0.01µF ISL6116 ISL6116 8 7 6 5 When driving particularly large capacitive loads a longer softstart time to prevent current regulation upon charging and a short CR time may offer the best application solution relative to reliability and FET MTF. NC Physical layout of RSENSE resistor is critical to avoid the possibility of false overcurrent occurrences. Ideally, trace routing between the RSENSE resistors and the IC is as direct and as short as possible with zero current in the sense lines (See Figure 1). 0.047µF 12V DD1 PWRON VBUS -48V FIGURE 2. CORRECT INCORRECT Biasing the ISL6116 ISL6116 Table 3 gives typical component values for biasing the ISL6116 ISL6116 in a ±48V application. The formulas and calculations deriving these values are also shown below. TO ISEN AND RISET TABLE 3. TYPICAL VALUES FOR A -48V HOT SWAP APPLICATION SYMBOL CURRENT SENSE RESISTOR PARAMETER Using the ISL6116 ISL6116 as a -48V Low Side Hot Swap Power Controller To supply the required VDD, it is necessary to maintain the chip supply 10 to 16V above the -48V bus. This may be accomplished with a suitable regulator between the voltage rail and pin 5 (VDD). By using a regulator, the designer may ignore the bus voltage variations. However, a low-cost alternative is to use a Zener diode (See Figure 2 for typical 5A load control); this option is detailed below. Note that in this configuration the PGOOD feature (pin 7) is not operational as the ISEN pin voltage is always < UV threshold. See Figures 17 to 20 for waveforms relevant to -48V and other high voltage applications. 1.58k, 1W DD1 FIGURE 1. SENSE RESISTOR PCB LAYOUT RCL 12V Zener Diode, 50mA Reverse Current When using the ISL6116 ISL6116 to control -48V, a Zener diode may be used to provide the +12V bias to the chip. If a Zener is used then a current limit resistor should also be used. Several items must be taken into account when choosing values for the current limit resistor (RCL) and Zener Diode (DD1): · The variation of the VBUS (in this case, -48V nominal) · The chip supply current needs for all functional conditions · The power rating of RCL. · The current rating of DD1 Formulas 1. Sizing RCL: RCL = (VBUS,MIN - 12)/ICHIP 2. Power Rating of RCL: PRCL = IC(VBUS,MAX - 12) 3. DD1 Current Rating: IDD1 = (VBUS,MAX - 12)/RCL 6 February 6, 2007 ISL6115 ISL6115, ISL6116 ISL6116, ISL6117 ISL6117, ISL6120 ISL6120 Example A typical -48V supply may vary from -36 to -72V. Therefore, VBUS,MAX = -72V VBUS,MIN = -36V Power Rating of RCL: PRCL = IC(VBUS,MAX - 12) PRCL = (0.015)(72 - 12) PRCL = 0.9W [Typical Value = 1W] DD1 Current Rating: IDD1 = (VBUS,MAX - 12)/RCL IDD1 = (72 - 12)/1.58k IDD1 = 38mA [Typical Value = 12V rating, 50mA reverse current] ICHIP = 15mA (max) Sizing RCL: RCL = (VBUS,MIN - 12)/IC RCL = (36 - 12)/0.015 RCL = 1.6k [Typical Value = 1.58k] Typical Performance Curves 5.0 20.2 20.0 ISET CURRENT µA) SUPPLY CURRENT (mA) 4.5 4.0 3.5 3.0 2.5 19.8 19.6 19.4 19.2 2.0 0 10 20 30 40 50 60 70 80 90 19.0 0 100 10 20 TEMPERATURE (°C) 40 50 60 70 80 90 100 90 100 TEMPERATURE (°C) FIGURE 3. VDD BIAS CURRENT FIGURE 4. ISET SOURCE CURRENT 1.89 CTIM OC VOLTAGE THRESHOLD (V) 20.50 CTIM = 0V, CURRENT SOURCE (µA) 30 20.32 CTIM - 0V 20.16 20.00 19.82 19.66 19.50 1.88 1.87 1.86 1.85 1.84 1.83 0 10 20 30 40 50 60 70 80 TEMPERATURE (°C) FIGURE 5. CTIM CURRENT SOURCE 7 90 100 0 10 20 30 40 50 60 70 80 TEMPERATURE (°C) FIGURE 6. CTIM OC VOLTAGE THRESHOLD February 6, 2007 ISL6115 ISL6115, ISL6116 ISL6116, ISL6117 ISL6117, ISL6120 ISL6120 (Continued) 2.70 ISL6116 ISL6116 ISL6115 ISL6115 9.75 4.36 9.74 0 10 20 30 40 50 60 70 80 90 ISL6117 ISL6117, 3.3V UV THRESHOLD (V) 4.37 ISL6116 ISL6116, 5V UV THRESHOLD (V) 4.35 100 1.860 ISL6117 ISL6117 2.65 1.855 ISL6120 ISL6120 2.60 0 10 20 30 40 50 60 70 80 90 TEMPERATURE (°C) TEMPERATURE (°C) FIGURE 7. ISL6115/6116 ISL6115/6116 UV THRESHOLD 1.850 100 FIGURE 8. ISL6117/6120 ISL6117/6120 UV THRESHOLD 17.200 12.00 10.1 17.183 11.99 17.166 11.98 17.150 11.97 17.133 11.96 17.116 11.95 ISL6115 ISL6115, GATE DRIVE (V) GATE CHARGE CURRENT (A) 10.2 10.0 9.9 9.8 9.7 17.100 9.6 0 10 20 30 40 50 60 70 80 90 100 TEMPERATURE (°C) 0 10 20 30 40 50 60 70 80 90 ISL6116 ISL6116,17,20 GATE DRIVE (V) ISL6115 ISL6115, 12V UV THRESHOLD (V) 9.76 ISL6120 ISL6120, 2.5V UV THRESHOLD (V) Typical Performance Curves 11.94 100 TEMPERATURE (°C) FIGURE 9. GATE CHARGE CURRENT FIGURE 10. GATE DRIVE VOLTAGE, VDD = 12V POWER ON RESET (V) 8.5 VDD LO TO HI 8.4 8.3 GATE VOUT 8.2 PGOOD 8.1 VDD HI TO LO IOUT PWRON 8.0 0 10 20 30 40 50 60 70 80 90 100 TEMPERATURE (°C) FIGURE 11. POWER ON RESET VOLTAGE THRESHOLD 8 5V/DIV. 0.5A/DIV 1ms/DIV FIGURE 12. ISL6115 ISL6115 +12V TURN-ON February 6, 2007 ISL6115 ISL6115, ISL6116 ISL6116, ISL6117 ISL6117, ISL6120 ISL6120 Typical Performance Curves (Continued) GATE PGOOD IOUT GATE PWRON VOUT VOUT IOUT CTIM PGOOD 2V/DIV 0.5A/DIV 1ms/DIV 5V/DIV 0.5A/DIV 1ms/DIV FIGURE 13. ISL6116 ISL6116 +5V TURN-ON FIGURE 14. ISL6115 ISL6115 `LOW' OVERCURRENT RESPONSE IOUT IOUT VOUT GATE CTIM PGOOD VOUT GATE CTIM PGOOD 5V/DIV 0.5A/DIV 1ms/DIV 2V/DIV 0.5A/DIV 1ms/DIV FIGURE 15. ISL6115 ISL6115 `HIGH' OVERCURRENT RESPONSE VDRAIN 10V/DIV. IOUT 1A/DIV. FIGURE 16. ISL6116 ISL6116 `HIGH' OVERCURRENT RESPONSE VDRAIN 10V/DIV. IOUT 1A/DIV. 0V +50V VGATE 5V/DIV. VGATE 5V/DIV. PWRON 5V/DIV. EN 5V/DIV. 0V 0V -50V 0V 5ms/DIV 5ms/DIV FIGURE 17. +50V LOW SIDE SWITCHING CGATE = 100pF FIGURE 18. -50V LOW SIDE SWITCHING CGATE = 1000pF 9 February 6, 2007 ISL6115 ISL6115, ISL6116 ISL6116, ISL6117 ISL6117, ISL6120 ISL6120 Typical Performance Curves (Continued) +350V +350V IOUT 1A/DIV IOUT 1A/DIV VDRAIN 50V/DIV VDRAIN 50V/DIV VGATE 5V/DIV VGATE 5V/DIV. PWRON 5V/DIV PWRON 5V/DIV 0V 0V 2ms/DIV FIGURE 19. +350V LOW SIDE SWITCHING CGATE = 100pF 2ms/DIV FIGURE 20. +350V LOW SIDE SWITCHING CGATE = 1000pF ISL6115EVAL1 ISL6115EVAL1 Board ISL6116EVAL1 ISL6116EVAL1 Board The ISL6115EVAL1 ISL6115EVAL1 is configured as a +12V high side switch controller with the CR level set at ~1.5A. (See Figure 21 for ISL6115EVAL1 ISL6115EVAL1 schematic and Table 4 for BOM). Bias and load connection points are provided along with test points for each IC pin. The ISL6116EVAL1 ISL6116EVAL1 is default configured as a negative voltage low side switch controller with a ~2.4A CR level. (See Figure 22 for ISL6116EVAL1 ISL6116EVAL1 schematic and Table 4 for BOM and component description). This basic configuration is capable of controlling both larger positive or negative potential voltages with minimal changes. With the chip to be biased from the +12V bus being switched, through B2, GND B5, the load connected between B3 and B4 and with jumper J1 installed the ISL6115 ISL6115 can be evaluated. PWRON pin pulls high enabling the ISL6115 ISL6115 if not driven low. With R2 = 750 the CR Vth is set to 15mV and with the 10m sense resistor the ISL6115EVAL1 ISL6115EVAL1 has a nominal CR level of 1.5A. The 0.047F delay time to latch-off capacitors results in a nominal 4.4ms before latch-off of outputs after an OC event. Also included with the ISL6115EVAL1 ISL6115EVAL1 board are one each of the ISL6116 ISL6116, ISL6117 ISL6117 and ISL6120 ISL6120 for evaluation. Bias and load connection points are provided in addition to test points, TP1-8 for each IC pin. The terminals, J1 and J4 are for the bus voltage and return, respectively, with the more negative potential being connected to J4. With the load between terminals J2 and J3 the board is now configured for evaluation. The device is enabled through LOGIN, TP9 with a TTL signal. ISL6116EVAL1 ISL6116EVAL1 includes a level shifting circuit with an opto-coupling device for the PWRON input so that standard TTL logic can be translated to the -V reference for chip control. When controlling a positive voltage, PWRON can be accessed at TP8. The ISL6116EVAL1 ISL6116EVAL1 is provided with a high voltage linear regulator for convenience to provide chip bias from ±24V to ±350V. This can be removed and replaced with the zener & resistor bias scheme as discussed earlier. High voltage regulators and power discrete devices are no longer available from Intersil but can be purchased from other semiconductor manufacturers. Reconfiguring the ISL6116EVAL1 ISL6116EVAL1 board for a higher CR level can be done by changing the RSENSE and RISET resistor values as the provided FET is 75A rated. If evaluation at >60V, an alternate FET must be chosen with an adequate BVDSS. 10 February 6, 2007 ISL6115 ISL6115, ISL6116 ISL6116, ISL6117 ISL6117, ISL6120 ISL6120 HI J2 LOAD J3 LO R1 Q2 + LOAD B3 J1 +VBUS - B4 J4 -VBUS C1 R2 R7 1 2 3 4 R2 8 1 R1 2 3 ISL6115 ISL6115 7 U1 C3 R5 C2 LOGIN TP9 R G 1 D2 R4 C3 8 DD1 3.3V 7 D1 6 5 5 R3 ISL6116 ISL6116 U1 6 4 Q1 PWRON TP8 PWRON B5 JP1 R11 +12V D2 B1 VBIAS V+ B2 R10 R8 R6 C1 DD1 3.3V R5 R9 OFF 0-5V ON OT1 FIGURE 21. ISL6115EVAL1 ISL6115EVAL1 HIGH SIDE SWITCH APPLICATION FIGURE 22. ISL6116EVAL1 ISL6116EVAL1 NEGATIVE VOLTAGE LOW SIDE CONTROLLER TABLE 4. BILL OF MATERIALS, ISL6115EVAL1 ISL6115EVAL1, ISL6116EVAL1 ISL6116EVAL1 COMPONENT DESIGNATOR COMPONENT NAME COMPONENT DESCRIPTION Q1 HUF76132SK8 HUF76132SK8 11.5m, 30V, 11.5A Logic Level N-Channel Power MOSFET or equiv. Q2 HUF7554S3S HUF7554S3S 10m, 80V, 75A N-Channel Power MOSFET or equiv. R1 Load Current Sense Resistor Dale, WSL-2512 WSL-2512 10m 1W Metal Strip Resistor High Side R2 Overcurrent Voltage Threshold Set Resistor 750 805 Chip Resistor (Vth = 15mV) Low side R2 Overcurrent Voltage Threshold Set Resistor 1.21k 805 Chip Resistor (Vth = 24mV) C2 Time Delay Set Capacitor 0.047F 805 Chip Capacitor (4.5ms) C1 Gate Timing Capacitor 0.001F 805 Chip Capacitor (