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SPARTAN-6LX16-REF Texas Instruments Spartan-6 LX16 Eval Kit visit Texas Instruments
SPARTAN-6-LX150T-REF Texas Instruments Spartan-6 LX150T Dev Kit visit Texas Instruments
SPARTAN-3TM-CYCLONE-IITM-PCI-EXPRESS-DEV-KIT Texas Instruments Spartan 3?/Cyclone II? based x1 PCI Express Development kit visit Texas Instruments

ISERDES spartan 6

Catalog Datasheet MFG & Type PDF Document Tags

XAPP758c

Abstract: ISERDES spartan 6 Application Note: Virtex Series and Spartan-3 Series FPGAs R XAPP802 (v1.9) March 26, 2007 , . (Figure 6 shows the block diagram.) - With the SERDES technique, the read data is captured in the delayed strobe domain and recaptured in the FPGA clock domain in the ISERDES. The IDELAY element is used to , 4bit parallel single data rate (SDR) data at half the frequency of the interface using the ISERDES , resource. The BUFIO clocking resource routes the delayed read DQS to its associated data ISERDES clock
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XAPP701 XAPP852 XAPP758c ISERDES spartan 6 XAPP678 ISERDES FF1136 XAPP858 XAPP758 XAPP702 XAPP703 XAPP709 XAPP710

XAPP1064

Abstract: BUFIO2 and phase detector circuitry. ISERDES and OSERDES Guidelines Each Spartan-6 FPGA input/output , possible, and the Spartan-6 FPGA ISERDES can support ratios of 2, 3, and 4:1, and also 5, 6, 7, and 8:1 , Application Note: Spartan-6 FPGAs Source-Synchronous Serialization and Deserialization (up to 1050 Mb/s) XAPP1064 (v1.1) June 3, 2010 Author: NIck Sawyer Summary Spartan®-6 devices , Reception Using BUFIO2 Delaying Input Data and Clocks The Spartan-6 FPGA data capture mechanism is based
Xilinx
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BUFIO2 ISERDES2 iodelay OSERDES oserdes2 DDR spartan6 serdes

OSERDES

Abstract: oserdes2 DDR spartan6 and phase detector circuitry. ISERDES and OSERDES Guidelines Each Spartan-6 FPGA input/output , possible, and the Spartan-6 FPGA ISERDES can support ratios of 2, 3, and 4:1, and also 5, 6, 7, and 8:1 , Application Note: Spartan-6 FPGAs Source-Synchronous Serialization and Deserialization (up to 1050 Mb/s) XAPP1064 (v1.0) December 23, 2009 Author: NIck Sawyer Summary Spartan®-6 devices , Reception Using BUFIO2 Delaying Input Data and Clocks The Spartan-6 FPGA data capture mechanism is based
Xilinx
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oserdes2 clock_generator_ddr_s8_diff testbench of a oserdes2 in verilog Clock-Generator X10640

XAPP753

Abstract: ISERDES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 , . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Chapter 2: Virtex-II Series or Spartan , Virtex-4 IOB with ISERDES and OSERDES Functionalities . . . . . . . . . . . . . . . . . . 52 , Virtex-4 ISERDES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . , : Virtex-4 ISERDES Sample Code Appendix B: EMIF Register Field Descriptions Appendix C: Related
Xilinx
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XAPP753 IPC-2141 RAMB16 TMSC6000 TMS320C64xx cpu microblaze block architecture TMS320C6201 SPRS051 SPRA839 XAPP623

UG381

Abstract: Spartan-6 LX45 Spartan-6 FPGA SelectIO Resources User Guide [optional] UG381 (v1.0) June 24, 2009 [optional , for this document. Date Version 06/24/09 1.0 Revision Initial Xilinx release. Spartan-6 , . . . . . . . . . 11 Spartan-6 FPGA SelectIO Banks . . . . . . . . . . . . . . . . . . . . . . . . , Resistors (Split Termination) . . . . . . . . . . . . . . . . . . 12 12 13 13 14 15 Spartan-6 , . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Spartan-6 FPGA
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Spartan-6 LX45 Spartan-6 FPGA LX9 JESD209A JESD79-3 ibis file for spartan6 LX9 Xilinx Spartan-6 LX9

ISERDES

Abstract: ISERDES spartan 6 Interface Data Capture Using ISERDES and OSERDES Author: Maria George Summary This application note , Input Serializer/Deserializer (ISERDES) and Output Serializer/Deserializer (OSERDES) features available , in the delayed strobe domain and recaptured in the FPGA clock domain in the ISERDES. The received , interface using the ISERDES. The 4-bit parallel data has the same frequency of the interface because the OCLK and CLKDIV inputs of the ISERDES in the memory mode are clocked by the same fast clock. The
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XAPP721 SRL16

UG381

Abstract: hitachi sr 2010 receiver Spartan-6 FPGA SelectIO Resources User Guide UG381 (v1.4) December 16, 2010 Xilinx is , pages 16, 17, and 18. Added IBUFDS_DIFF_OUT and IBUFGDS_DIFF_OUT to the Spartan-6 FPGA SelectIO , 3-7 and updated Figure 3-10. Spartan-6 FPGA SelectIO Resources www.xilinx.com UG381 (v1.4) December 16, 2010 Date Version 03/15/10 1.3 Revision Revised Table 1-5, see DS162: Spartan-6 , . UG381 (v1.4) December 16, 2010 www.xilinx.com Spartan-6 FPGA SelectIO Resources Spartan-6 FPGA
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hitachi sr 2010 receiver HDMI verilog code XC6SLX JESD8C-01 xc6slx75 spartan hdmi

JESD79-2c

Abstract: oserdes2 DDR spartan6 Spartan-6 FPGA SelectIO Resources User Guide UG381 (v1.3) March 15, 2010 Xilinx is , respective owners. Spartan-6 FPGA SelectIO Resources www.xilinx.com UG381 (v1.3) March 15, 2010 , . Added IBUFDS_DIFF_OUT and IBUFGDS_DIFF_OUT to the Spartan-6 FPGA SelectIO Primitives section , Table 1-4, see DS162: Spartan-6 FPGA Data Sheet for recommended operating conditions. Added , www.xilinx.com Spartan-6 FPGA SelectIO Resources Spartan-6 FPGA SelectIO Resources www.xilinx.com
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JESD79-2c xc6slx75t XC6SL SPARTAN 6 xc6slx45 pin configuration vhdl spartan ddr3 DSP48A1
Abstract: Spartan-6 FPGA SelectIO Resources User Guide UG381 (v1.6) February 14, 2014 Notice of , to the Spartan-6 FPGA SelectIO Primitives section including updating Figure 1-13. Clarified bank , 3-13, page 96. Spartan-6 FPGA SelectIO Resources www.xilinx.com UG381 (v1.6) February 14, 2014 , , see DS162: Spartan-6 FPGA Data Sheet for recommended operating conditions. Added Pin-Planning to , ) February 14, 2014 www.xilinx.com Spartan-6 FPGA SelectIO Resources Spartan-6 FPGA SelectIO Xilinx
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Abstract: Spartan-6 FPGA SelectIO Resources User Guide UG381 (v1.5) February 7, 2013 Xilinx is , edits on pages 16, 17, and 18. Added IBUFDS_DIFF_OUT and IBUFGDS_DIFF_OUT to the Spartan-6 FPGA , 3-7 and updated Figure 3-10. Spartan-6 FPGA SelectIO Resources www.xilinx.com UG381 (v1.5) February 7, 2013 Date Version 03/15/10 1.3 Revision Revised Table 1-5, see DS162: Spartan-6 , to Figure 3-1. www.xilinx.com Spartan-6 FPGA SelectIO Resources Spartan-6 FPGA SelectIO Xilinx
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XA6SLX45

Abstract: Spartan-6 FPGA 9 XA Spartan-6 Automotive FPGA Family Overview DS170 (v1.0) March 2, 2010 Advance Product Specification General Description The Xilinx Automotive (XA) Spartan®-6 family of FPGAs provides leading , performance, the XA Spartan-6 family offers a new, more efficient, dual-register 6-input look-up table (LUT , custom ASIC products with unprecedented ease of use. XA Spartan-6 FPGAs offer the best solution for , cost-sensitive applications where multiple interfacing standards are required. XA Spartan-6 FPGAs are the
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UG388 XA6SLX45 Spartan-6 FPGA XA6SLX75 XA6SLX16 SPARTAN 6 UG385 Spartan-6 PCB design guide UG380 UG389 UG382 UG393 UG386

XQ6SLX75T

Abstract: XQ6SLX150 offered by the new 6-input LUT architecture. Each Spartan-6Q FPGA slice contains four LUTs and eight , spread-spectrum clock inputs, provided they abide by the input clock specifications listed in the Spartan-6 FPGA , , using up to 3.3V. The Spartan-6 FPGA SelectIO Resources User Guide describes the I/O compatibilities of , drive-strengths and slew-rates, and differential termination resistors. See the Spartan-6 FPGA SelectIO Resources , I-grade only). Pb-Free See the Spartan-6 FPGA data sheet for more information. Package Type 2
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UG394 XQ6SLX75T XQ6SLX150 XQ6SLX75 spartan 6 LX150 XQ6SLX150T SPARTAN-6 GTP DS172 UG383 UG384

traffic light controller vhdl coding

Abstract: 1000BASE-X sfp sgmii -4, Spartan-6, Spartan-3, Spartan-3E, Spartan-3A/3A DSP GMII Resources2 Slices 140­1100 GTs 0-1 LUTs 170­1090 , ) Spartan®-6 FPGA GTP Transceiver Design Files Example Designs Test Bench Constraints File , . Kintex-7, Artix-7, Spartan-6, Virtex-5, Virtex-4 and Spartan-3 devices support GMII at 3.3 V or lower , FPGA Data Sheet: DC and Switching Characteristics. Kintex-7, Spartan-6, Virtex-5, Virtex-4 and Spartan , (DRU). This block uses the Virtex-6 FPGA ISERDES elements in a new asynchronous oversampling mode as
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DS264 ENG-46158 traffic light controller vhdl coding 1000BASE-X sfp sgmii 1000base-x xilinx sgmii specification ieee verilog code for 10 gb ethernet 1000BASE-X

sgmii specification ieee

Abstract: ENG-46158 -5, Virtex-4, Spartan-6, Spartan-3, Spartan-3E, Spartan-3A/3A DSP GMII · Features · Supported physical , (MGT) Spartan®-6 FPGA GTP Transceiver Design Entry Tools Provided with Core Documentation Product , . Kintex-7, Spartan-6, Virtex-5, Virtex-4 and Spartan-3 devices support GMII at 3.3 V or lower. PCS , Switching Characteristics. Kintex-7, Spartan-6, Virtex-5, Virtex-4 and Spartan-3 devices support TBI at 3.3 , the Virtex-6 FPGA ISERDES elements in a new asynchronous oversampling mode as described in XAPP881
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virtex-7 vhdl ethernet spartan 3a vhdl ethernet spartan 3e gtx 970 vhdl code for ethernet mac spartan 3 SPARTAN 6 ethernet

SPARTAN 6 xc6slx45 pin configuration

Abstract: XC6SLX45 10 Spartan-6 Family Overview DS160 (v1.3) November 5, 2009 Advance Product Specification General Description The Spartan®-6 family provides leading system integration capabilities with the , technology that delivers the optimal balance of cost, power, and performance, the Spartan-6 family offers a , unprecedented ease-of-use. Spartan-6 FPGAs offer the best solution for highvolume logic designs, consumer-oriented DSP designs, and cost-sensitive embedded applications. Spartan-6 FPGAs are the programmable
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XC6SLX45 XC6SLX16 XC6SLX9 spartan 6 partial configuration XC6SLX75 DDR3 XC6SLX150T

FIFO36

Abstract: DWH-11 Application Note: Virtex-5 Family R XAPP853 (v1.2) October 6, 2008 Summary QDR II SRAM , logo, Virtex, Spartan, ISE, and other designated brands included herein are trademarks of Xilinx in the , . XAPP853 (v1.2) October 6, 2008 www.xilinx.com 1 R Introduction The QDR I and QDR II memory , , page 3 for clarity. XAPP853 (v1.2) October 6, 2008 www.xilinx.com 2 R Introduction , . XAPP853 (v1.2) October 6, 2008 www.xilinx.com 3 R Design Overview Design Overview
NEC
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FIFO36 DWH-11 ML561 mig ddr virtex DWH-01 DWH-10

XA6SLX16

Abstract: SPARTAN 6 UG385 10 XA Spartan-6 Automotive FPGA Family Overview DS170 (v1.2) December 13, 2011 Product Specification General Description The Xilinx Automotive (XA) Spartan®-6 family of FPGAs provides leading , optimal balance of cost, power, and performance, the XA Spartan-6 family offers a new, more efficient , Spartan-6 FPGAs offer the best solution for flexible and scalable high-volume logic designs , standards are required. XA Spartan-6 FPGAs are the programmable silicon foundation for Targeted Design
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FTG256 XA6SLX100 XA6SLX4 XA6sLx25

xc6slx45 pinout

Abstract: DS160 10 Spartan-6 Family Overview DS160 (v1.4) March 3, 2010 Advance Product Specification General Description The Spartan®-6 family provides leading system integration capabilities with the , technology that delivers the optimal balance of cost, power, and performance, the Spartan-6 family offers a , unprecedented ease of use. Spartan-6 FPGAs offer the best solution for high-volume logic designs, consumer-oriented DSP designs, and cost-sensitive embedded applications. Spartan-6 FPGAs are the programmable
Xilinx
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xc6slx45 pinout XC6SLX4 2 CSG225 I XC6SLX9 2 CSG225 I DSP48A1 UG389 SPARTAN 6 UG393 SPARTAN 6 DS162

XA6SLX75

Abstract: spartan6 10 XA Spartan-6 Automotive FPGA Family Overview DS170 (v1.3) December 13, 2012 Product , optimal balance of cost, power, and performance, the XA Spartan-6 family offers a new, more efficient , use. XA Spartan-6 FPGAs offer the best solution for flexible and scalable high-volume logic designs , standards are required. XA Spartan-6 FPGAs are the programmable silicon foundation for Targeted Design , innovation as soon as their development cycle begins. Summary of XA Spartan-6 FPGA Features â'¢ â
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spartan6 SPARTAN-6 LPDDR KINTEX 7

example ml605 FMC 150

Abstract: XAPP1071 Application Note: Virtex-6 FPGAs Connecting Virtex-6 FPGAs to ADCs with Serial LVDS Interfaces , Summary This application note describes how to utilize the dedicated deserializer (ISERDES) and serializer (OSERDES) functionalities in Virtex®-6 FPGAs to interface with analog-to-digital converters (ADCs , interface connecting a Virtex-6 FPGA to any ADCs or DACs with high-speed serial interfaces. Introduction , , Virtex, Spartan, ISE, and other designated brands included herein are trademarks of Xilinx in the United
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XAPP1071 example ml605 FMC 150 VHDL code for ADC and DAC SPI with FPGA VHDL code for ADC and DAC SPI with FPGA spartan 3 example ml605 Verilog code for ADC and DAC SPI with FPGA UG365
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