IS80C51 SR8199580C51 0000H 20H-2FH 30-7FH 0X000000B XXX00000B 0XXX0000B 00H-07H - Datasheet Archive

 

® ISSI IS80C51 IS80C51 ® ADVANCE INFORMATION DECEMBER 1995 CMOS SINGLE CHIP 8-BIT MICROCONTROLLER FEATURES GENERAL

 

ISSI ® ISSI IS80C51 IS80C51 IS80C51 IS80C51 ® ADVANCE INFORMATION DECEMBER 1995 CMOS SINGLE CHIP 8-BIT MICROCONTROLLER FEATURES GENERAL DESCRIPTION · · · · · · · · · · · The ISSI IS80C51 IS80C51 is a high-performance microcontroller fabricated using high-density CMOS technology. The CMOS IS80C51 IS80C51 is functionally compatible with the NMOS Intel 8051 microcontroller. 4K x 8 ROM 128 x 8 RAM Two 16-bit counter/timers Full duplex serial channel Boolean processor Four 8-bit I/O ports, 32 I/O lines External memory expandable to 128K Most instructions execute in 1 µs CMOS and TTL compatible Maximum speed ranges at Vcc = 5V = 24 MHz Packages available: ­ 40-pin DIP package ­ 44-pin PLCC package The IS80C51 IS80C51 is designed with 4K x 8 ROM; 128 x 8 RAM; 32 I/O lines for either multiprocessor communications, I/O expansion, or full duplex UART; two 16-bit timers/counters; a five-source, two-prioritylevel, nested interrupt structure; and an on-chip oscillator and clock circuit. The IS80C51 IS80C51 can be expanded using standard TTL compatible memory. 40-Pin DIP P0.2 P0.3 INDEX P0.1 P0.1 P0.0 P0.0 38 VCC 39 3 NC 2 P1.2 P1.0 P1.1 6 VCC P1.1 40 P1.2 1 P1.3 P1.0 P1.4 40-Pin DIP 5 4 3 2 1 44 43 42 41 40 7 39 P0.4 P1.3 4 37 P0.2 P1.5 P1.4 5 36 P0.3 P1.6 8 38 P0.5 P1.5 6 35 P0.4 P1.6 7 34 P0.5 P1.7 9 37 P0.6 P1.7 8 33 P0.6 RST/VPD 10 36 P0.7 RST P3.0/RxD 11 35 EA NC 12 34 NC P3.1/TxD 13 33 ALE 9 32 P0.7 P3.0/RxD 10 31 EA P3.1/TxD 11 30 ALE P3.2/INT0 12 29 PSEN P3.3/INT1 13 28 P2.7 P3.2/INT0 14 32 PSEN P3.4/T0 14 27 P2.6 P3.3/INT1 15 31 P2.7 P3.5/T1 15 26 P2.5 P3.6/WR 16 25 P2.4 P3.5/T0 16 30 P2.6 P3.7/RD 17 24 P2.3 P3.6/T1 17 29 P2.5 XTAL2 18 23 P2.2 XTAL1 19 22 P2.1 GND 20 21 P2.0 18 19 20 21 22 23 24 25 26 27 28 P3.6/WR P3.7/RD XTAL1 XTAL2 GND NC P2.0 P2.1 P2.2 P2.3 P2.4 TOP VIEW Figure 1. IS80C51 IS80C51 Pin Configurations This document contains advance information. ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which may appear in this publication. © Copyright 1995, Integrated Silicon Solution, Inc. Integrated Silicon Solution, Inc. ADVANCE INFORMATION SR8199580C51 SR8199580C51 Rev. A 1295 1 ISSI IS80C51 IS80C51 ® P PROGRAM MEMORY ADDRESS DECODER CY AC F0 RS RS OV 1 0 ACC B IPC IEC SBUF SCON TH1 TL1 TH0 TL0 TMOD TCON DPH DPL SP RAM ADDRESS DECODER SPECIAL FUNCTION REGISTER ADDRESS DECODER PARITY ROTATE CONTROL INTERRUPT CONTROL SERIAL PORT TIMER CONTROL PROGRAM CONTROL PCL 128 x 8 RAM PCH REGISTER BANK3 REGISTER BANK2 REGISTER BANK1 REGISTER BANK0 DRIVERS CONTROL PLA CONTROL GND RST DRIVERS CONTROL ENGINE INSTRUCTION DECODER P3 POWER VCC XTAL1 XTAL2 EA ALE PSEN OSC AND TIMING CIRCUIT 4K x 8 ROM PORT 1 P2 P0 PORT 3 PORT 2 PORT 0 Figure 2. IS80C51 IS80C51 Block Diagram 2 Integrated Silicon Solution, Inc. ADVANCE INFORMATION Rev. A 1295 SR8199580C51 SR8199580C51 ISSI IS80C51 IS80C51 ® PIN DESCRIPTION Pin Symbol DIP PLCC I/O Name and Function P1.0-1.7 1-8 2-9 I/O Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pullups. Port 1 pins that have 1s written to them are pulled high by the internal pullups and can be used as inputs. As inputs, Port 1 pins that are externally pulled low will source current because of the internal pullups. RST/VPD 9 10 I Reset: A high on this pin for two machine cycles while the oscillator is running, resets the device. An internal diffused resistor to GND permits a power-on reset using only an external capacitor. A small internal resistor permits power-on reset using only a capacitor connected to VCC. I/O P3.0-P3.7 10 11 12 13 14 15 16 17 11 13 14 15 16 17 18 19 I O I I I I O O Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pullups. Port 3 pins that have 1s written to them are pulled high by the internal pullups and can be used as inputs. As inputs, Port 3 pins that are externally pulled low will source current because of the internal pullups. Port 3 also serves the special features of the IS80C51 IS80C51, as listed below: RxD (P3.0): Serial input port TxD (P3.1): Serial output port (P3.2): External interrupt (P3.3): External interrupt T0 (P3.4): Timer 0 external input T1 (P3.5): Timer 1 external input /WR (P3.6): External data memory write strobe /RD (P3.7): External data memory read strobe XTAL 2 18 20 O Crystal 2: Output from the inverting oscillator amplifier. XTAL 1 19 21 I Crystal 1: Input to the inverting oscillator amplifier and input to the internal clock generator circuits. GND 20 22 I Ground: 0V reference. 21-28 24-31 I/O P2.0-P2.7 10-17 11, 13-19 Port 2: Port 2 is an 8-bit bi-directional I/O port with internal pullups. Port 2 pins that have 1s written to them are pulled high by the internal pullups and can be used as inputs. As inputs, Port 2 pins that are externally pulled low will source current because of the internal pullups. Port 2 emits the high order address byte during fetches from external program memory and during accesses to external data memory that used 16-bit addresses. In this application, it uses strong internal pullups when emitting 1s. During accesses to external data memory that use 8-bit addresses, Port 2 emits the contents of the P2 special function register. (continued) Integrated Silicon Solution, Inc. ADVANCE INFORMATION SR8199580C51 SR8199580C51 Rev. A 1295 3 ISSI IS80C51 IS80C51 ® PIN DESCRIPTION (continued) Pin Symbol DIP PLCC I/O Name and Function /PSEN 29 32 O Program Store Enable: The read strobe to external program memory. When the device is executing code from the external program memory, /PSEN is activated twice each machine cycle except that two /PSEN activations are skipped during each access to external data memory. /PSEN is not activated during fetches from internal program memory. ALE 30 33 I/O Address Latch Enable: Output pulse for latching the low byte of the address during an address to the external memory. In normal operation, ALE is emitted at a constant rate of 1/6 the oscillator frequency, and be used for external timing or clocking. Note that one ALE pulse is skipped during each access external data memory. /EA 31 35 I External Access enable: /EA must be externally held low to enable the device to fetch code from external program memory locations 0000H 0000H to 0FFFH. If /EA is held high, the device executes from internal program memory unless the program counter contains an address greater than 0FFFH. 39-32 43-36 I/O Port 0: Port 0 is an open-drain, bidirectional I/O port. Port 0 pins that have 1s written to them float and can be used as highimpedance inputs. Port 0 is also the multiplexed low-order address and data bus during accesses to external program and data memory. In this application, it uses strong internal pullups when emitting 1s. 40 44 I Power Supply: This is the power supply voltage for operation. P0.0-P0.7 Vcc OPERATING DESCRIPTION The detail description of the IS80C51 IS80C51 included in this description are: · · · · · · 4 Memory map and registers Timers/counters Serial interface Interrupt system Instruction Other information Memory Map and Registers Memory The IS80C51 IS80C51 has separate address spaces for program and data memory. The program memory can be up 64K bytes long. The lower 4K can reside onchip. Figure 3 shows a map of the IS80C51 IS80C51 program memory. The IS80C51 IS80C51 has 128 bytes of on-chip RAM, plus a number of special function registers. The lower 128 bytes can be accessed either by direct addressing or by indirect addressing. Figure 4 shows data memory origination. Integrated Silicon Solution, Inc. ADVANCE INFORMATION Rev. A 1295 SR8199580C51 SR8199580C51 ISSI IS80C51 IS80C51 The 128 bytes of RAM which can be accessed by both direct and indirect addressing can be divided into three segments as listed below and shown in Figure 5. 1. Register Banks 0-3: locations 0 through 1FH(32 bytes). The device after reset defaults to register bank 0. To use the other register banks, the user must select them in software. Each register bank contains eight 1-byte registers 0-7. Reset initialize the stack point to location 07h, and it is incremented once to start from 08H, which is the first register of the second bank. FFFF 2. Bit Addressable Area: 16 bytes have been assigned for this segment 20H-2FH 20H-2FH. Each one of the 128 bits of this segment can be directly addressed (0-7FH). The bits can be referred to in two ways, both of which are acceptable by most assemblers. One way is to reference to bytes 20H-2FH 20H-2FH. Thus, bits 0-7 can also be referred to as bits 20.0-20.7, and bits 8-FH are the same as 21.0-21.7, and so on. Each of the 16 bytes in this segment can also be addressed as a byte. 3. Scratch Pad Area: 30-7FH 30-7FH are available to the user as data RAM. However, if the data pointer has been initialized to this area, enough bytes should be left aside to prevent SP data destruction. 8 BYTES FFFF 78 0FFF 0000 0000 5F 57 4F 47 38 4K BYTE INTERNAL 67 40 1000 6F 60 48 OR 77 68 50 64K BYTES EXTERNAL 7F 70 58 60K BYTES EXTERNAL ® 3F 30 37 .7F 28 Figure 3. Program Memory Access Range 20 SCRATCH PAD AREA 0 . 2F 27 18 BANK3 1F 10 BANK2 17 08 BANK 1 0F 00 BANK 0 BIT ADDRESSABLE SEGMENT 07 REGISTER BANKS Figure 5. 128 Bytes of RAM Direct and Indirect Addressable 64K BYTES EXTERNAL SFRs DIRECT ADDRESS ONLY AND DIRECT AND INDIRECT ADDRESS Figure 4. Data Memory Access Range Integrated Silicon Solution, Inc. ADVANCE INFORMATION SR8199580C51 SR8199580C51 Rev. A 1295 5 ISSI IS80C51 IS80C51 ® SPECIAL FUNCTION REGISTER Symbol Description Direct Address ACC* Accumulator E0H E7 E6 E5 E4 E3 E2 E1 E0 00H B register F0H F7 F6 F5 F4 F3 F2 F1 F0 00H DPH Data pointer high 83H 00H DPL Data pointer low 82H 00H IE* Interrupt enable A8H AF EA AE - AD - AC AB AA A9 A8 ES ET1 EX1 ET0 EX0 0X000000B 0X000000B IP* Interrupt priority B8H BF - BE - BD - BC BB BA B9 B8 PS PT1 PX1 PT0 PX0 XXX00000B XXX00000B FFH B* Bit Address, Symbol, or Alternative Port Function Reset Value P0* Port 0 80H 87 86 85 84 83 82 81 80 P0.7 P0.6 P0.5 P0.4 P0.3 P0.2 P0.1 P0.0 P1* Port 1 90H 97 96 95 94 93 92 91 90 P1.7 P1.6 P1.5 P1.4 P1.3 P1.2 P1.1 P1.0 FFH P2* Port 2 A0H A7 A6 A5 A4 A3 A2 A1 A0 P2.7 P2.6 P2.5 P2.4 P2.3 P2.2 P2.1 P2.0 FFH Port 3 B0H B7 B6 B5 B4 B3 B2 B1 B0 P3.7 P3.6 P3.5 P3.4 P3.3 P3.2 P3.1 P3.0 FFH Power control 87H P3* PCON SMOD - D7 CY D6 AC - - GF1 GF0 PD IDL D5 D4 D3 D2 F0 RS1 RS0 OV D1 - D0 P 0XXX0000B 0XXX0000B PSW* Program status word D0H SBUF Serial data buffer 99H Serial controller 98H SP Stack pointer 81H TCON* Timer control 88H TH0 Timer high 0 8CH 00H TH1 Timer high 1 8DH 00H TL0 Timer low 0 8AH 00H TL1 Timer low 1 8BH 00H TMOD Timer mode 89H SCON* 00H XXXXXXXXB 9F 9E 9D 9C 9B 9A 99 SM0 SM1 SM2 REN TB8 RB8 TI 98 RI 00H 07H 8F 8E 8D 8C 8B 8A 89 88 TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 GATE C/T M1 M0 GATE C/T M1 M0 00H "*" denotes bit addressable 6 Integrated Silicon Solution, Inc. ADVANCE INFORMATION Rev. A 1295 SR8199580C51 SR8199580C51 ISSI IS80C51 IS80C51 The detail description of each bit is as follows: IE PSW EA CY AC F0 CY AC F0 PSW.7 PSW.6 PSW.5 RS1 RS0 OV - P PSW.4 PSW.3 PSW.2 PSW.1 PSW.0 RS1 RS0 OV - P Carry flag Auxiliary carry flag Flag 0 available to the user for general purpose Register bank selector bit 1 Register bank selector bit 0(1) Overflow flag Usable as a general purpose flag Parity flag. Set/clear by hardware each instruction cycle to indicate an odd/even number of "1" bus in the accumulator Note: 1. The value presented by RS0 and RS1 selects the corresponding register bank. RS1 RS0 Register Bank 0 1 0 1 0 1 2 3 00H-07H 00H-07H 08H-0FH 08H-0FH 10H-17H 10H-17H 18H-1FH 18H-1FH - EA IE.7 - IE.6 - IE.5 ES IE.4 ET1 IE.3 EX1 IE.2 ET0 IE.1 EX0 IE.0 Address 0 0 1 1 - - GF1 GF0 PD IDL SMOD Double baud rate bit. If Timer 1 is used to generate baud rate and SMOD=1, the baud rate is doubled when the serial port is used in modes 1, 2, or 3. - Not implemented, reserve for future use. - Not implemented, reserve for future use. - Not implemented, reserve for future use. GF1 General purpose flag bit. GF0 General purpose flag bit. PD Power down bit. Setting this bit activates power down operation in the IS80C51 IS80C51. IDL Idle mode bit. Setting this bit activate idle mode operation in the IS80C51 IS80C51. If 1s are written to PD and IDL at the same time, PD takes precedence. Integrated Silicon Solution, Inc. ADVANCE INFORMATION SR8199580C51 SR8199580C51 Rev. A 1295 - ES ET1 EX1 ET0 EX0 Disable all interrupts. If EA=0, no interrupt will be acknowledged. If EA=1, each interrupt source is individually enabled or disabled by setting or clearing its enable bit. Not implemented, reserve for future use. Not implemented, reserve for future use. Enable or disable the serial port interrupt. Enable or disable the timer 1 overflow interrupt. Enable or disable external interrupt 1. Enable or disable the timer 0 overflow interrupt. Enable or disable external interrupt 0. IP - - - IP.7 - PCON SMOD - ® IP.6 - IP.5 PS IP.4 PT1 IP.3 PX1 IP.2 PT0 IP.1 PX0 IP.0 - PS PT1 PX1 PT0 PX0 Not implemented, reserve for future use. Not implemented, reserve for future use. Not implemented, reserve for future use. Defines the serial port interrupt priority level. Defines the timer 1 interrupt priority level. Defines the external interrupt 1 priority level Defines the timer 0 interrupt priority level. Defines the external interrupt 0 priority level 7 ISSI IS80C51 IS80C51 TCON TF1 TR1 TF0 TMOD TR0 IE1 IT1 Timer 1 IE0 IT0 TF1 TCON.7 Timer 1 overflow flag. Set by hardware when the timer/counter 1 overflows. Cleared by hardware as processor vectors to the interrupt service routine. TR1 TCON.6 Timer 1 run control bit. Set/cleared by software to turn timer/counter 1 ON/OFF. TF0 TCON.5 Timer 0 overflow flag. Set by hardware when the timer/counter 0 overflows. Cleared by hardware as processor vectors to the interrupt service routine. TR0 TCON.4 Timer 0 run control bit. Set/cleared by software to turn timer/counter 0 ON/OFF. IE1 TCON.3 External interrupt 1 edge flag. Set by software when external interrupt edge is detected. Cleared by hardware when interrupt is processed. IT1 TCON.2 Interrupt 1 type control bit. Set/ cleared by software specify falling edge/low level triggered external interrupt. IE0 TCON.1 External interrupt 0 edge flag. Set by software when external interrupt edge is detected. Cleared by hardware when interrupt is processed. IT0 TCON.0 Interrupt 0 type control bit. Set/ cleared by software specify falling edge/low level triggered external interrupt. 8 ® Timer 0 GATE C/T M1 M0 GATE C/T M1 M0 GATE C/T M1 M0 When TRx (in TCON) is set and GATE=1, TIMER/COUNTERx will run only while INTx pin is high (hardware control). When GATE=0, TIMER/COUNTERx will run only while TRx=1 (software control). Timer or counter selector. Cleared for timer operation (input from internal system clock). Set for counter operation (input from Tx input pin). Mode selector bit.(2) Mode selector bit.(2) (2) M1 M0 Operating mode 0 0 Mode 0. (13-bit timer) 0 1 Mode 1. (16-bit timer/counter) 1 0 Mode 2. (8-bit auto-load timer/counter) 1 1 Mode 3. (TL0 is an 8-bit timer/counter controller by the standard timer 0 control bits. TH0 is an 8-bit timer and is controlled by timer 1 controller bits.) 1 1 Mode 3. (Timer/counter 1 stopped). Integrated Silicon Solution, Inc. ADVANCE INFORMATION Rev. A 1295 SR8199580C51 SR8199580C51 ISSI IS80C51 IS80C51 SCON ® Timers/counters SM0 SM1 SM2 REN TB8 RB8 TI RI SM0 SCON.7 Serial port mode specifier.(3) SM1 SCON.6 Serial port mode specifier.(3) SM2 SCON.5 Enable the multiprocessor communication feature in mode 2 and 3. In mode 2 or 3, if SM2 is set to 1 then RI will not be activated if the received 9th data bit (RB8) is 0. In mode 1, if SM2=1 then RI will not be activated if valid stop bit was not receive. In mode 0, SM2 should be 0. REN SCON.4 Set/cleared by software to enable/ disable reception. TB8 SCON.3 The 9th bit that will be transmitted in mode 2 and 3. Set/cleared by software. RB8 SCON.2 In modes 2 and 3, RB8 is the 9th data bit that was received. In mode 1, if SM2=0, RB8 is the stop bit that was received. In mode 0, RB8 is not used. TI SCON.1 Transmit interrupt flag. Set by hardware at the end of the 8th bit time in mode 0, or at the beginning of the stop bit in the other modes. Must be cleared by software. RI SCON.0 Receive interrupt flag. Set by hardware at the end of the 8th bit time in mode 0, or halfway through the stop bit time in the other modes (except see SM2). Must be cleared by software. (3) SM0 SM1 MODE Description Baud rate 0 0 0 Shift register Fosc/12 0 1 1 8-bit UART 0 2 9-bit UART 1 3 9-bit UART Counter 1/Timer 1: Counter 1/ timer 1 can be configured in one of four modes: Mode 0: Provides an 8-bit counter with a divideby-32 prescaler or an 8-bit timer with a divide-by-32 prescaler. A read/write of TH1 accesses counter 1's bits 12-5. A read/write of TL1 accesses counter 1's bits 7-0. TL1 bits 4-0 are the prescaler (counter 1's 4-0) while bits 7-5 are indeterminate and should be ignored. The programmer should clear the prescaler ( counter 1's bits 4-0) before setting the run flag. Mode 1: Configures counter 1 as a 16-bit timer/ counter. Mode 2: Configures counter 1 as an 8-bit autoreload value. TH1 holds the reload value. TL1 is incremented. The value in TH1 is reload onto TL1 when TL1 overflows from all ones. Mode 3: When counter 1's mode is reprogrammed to mode 3 ( from mode 0, 1 or 2), it disables the incrementing of the counter. This mode is provided as an alternative to use TR1 bit (TCON.6) to start and stop counter 1. The serial port receives a pulse each time that counter 1 overflows. The standard UART modes divide this pulse rate to generate the transmission rate. Fosc/64 or Fosc/32 1 The operating mode is listed below. Variable 1 The IS80C51 IS80C51 contains two 16-bit counters for measuring time intervals, measuring pulse widths, counting events and generating precise, periodic interrupt request. Variable Integrated Silicon Solution, Inc. ADVANCE INFORMATION SR8199580C51 SR8199580C51 Rev. A 1295 9 ISSI IS80C51 IS80C51 3. The function of TR1 can be done by placing counter 1 in mode 3, so only the function of TF1 is actually given up by counter 1. In mode 3, TL0 is configured as an 8-bit timer/counter and is controlled, as usual, by the GATE (TMOD. 3), C/ (TMOD.2), TR0 (TCON.4) and TF0 (TCON.5) control bits. The use of the timers/counters is determined by two 8-bit registers, TMOD and TCON is shown in SFR. The counter input circuit is shown in Figures 6 and 7. Counter 0/ Timer 0: Counter 0 can also be configured in one of four modes: Mode 0-2: Mode 0-2 are the same as for counter 1. Mode 3: In mode 3, the configure of TH0 is not affected by the bits in TMOD or TCON. It is configured solely as an 8-bit timer that is enabled for incrementing by TCON's TR1 bit. Upon TH0's overflow the TF1 flag gets set. Thus, neither TR1 nor TF1 is available to counter 1 when counter 0 is in mode TMOD.3 GATE GATE ® TMOD.2 C/T TCON.4 TR0 TIMER/ COUNTER TCON.5 TF0 RUN INTERRUPT REQUEST COUNTER 0 MODE 0: 8-BIT TIMER/COUNTER WITH PRESCALER MODE 1: 16-BIT 16-BIT TIMER/COUNTER MODE 2: 8-BIT AUTO-RELOAD TIMER/COUNTER MODE 3: 16-BIT 16-BIT TIMER/COUNTER (TL0) INT0 T0 XTAL1 DIVIDE 12 Figure 6. Timer/event Counter 0 Control and Status Flag Circiut TMOD.1 M1 TMOD.2 M0 TMOD.7 GATE GATE TMOD.6 C/T TIMER/COUNTER 0 IN MODE 3 TCON.6 TR1 RUN TCON.7 TF1 INTERRUPT REQUEST PULSE TO SERIAL PORT COUNTER 1 MODE 0: 8-BIT TIMER/COUNTER WITH PRESCALER MODE 1: 16-BIT 16-BIT TIMER/COUNTER MODE 2: 8-BIT AUTO-RELOAD TIMER/COUNTER MODE 3: PREVENTS INCREMENTING OF C/T INT1 T1 XTAL1 COUNTER 0 DIVIDE 12 8-BIT TIMER (TH0) Figure 7. Timer/event Counter 1 Control and Status Flag Circiut 10 Integrated Silicon Solution, Inc. ADVANCE INFORMATION Rev. A 1295 SR8199580C51 SR8199580C51 ISSI IS80C51 IS80C51 Serial Interface: The IS80C51 IS80C51 has serial I/O port that is useful for serial linking peripheral devices as well as multiple IS80C51s through standard asynchronous protocol with full-duplex operations. The data for transmission and from reception reside in the serial port buffer register (SBUF). The serial port control and the monitoring of its status is provided by the serial port control register ( SCON). The contents of the 8-bit SCON register are shown in SFR. The IS80C51 IS80C51 has serial channel useful for serially linking UART (universal asynchronous receiver/ transmitter) devices and for expanding I/O. The full- ® duplex serial I/O port can be programmed to function in one of four operating modes: Mode 0: Synchronous I/O expansion using or CMOS shift registers. Mode 1: UART interface with 10-bit frame variable transmission rate. Mode 2: UART interface with 11-bit frame fixed transmission rate. Mode 3: UART interface with 11-bit frame variable transmission rate. TTL and and and The serial interface circuit is shown in Figures 8 and 9. The use of the serial interface is determined by TCON and PCON registers is shown in SFR. TRANSMIT INTERRUPT SBUF (XMIT) SCON (SERIAL CONTROL) CONTROL AND TIMING CIRCUIT XTAL1 DIVIDE 12 DATA (TRANSMIT/RECEIVE) INTERNAL DATA BUS SBUF (RCVR) INPUT SHIFT REGISTER RECEIVER INTERRUPT RxD (RECEIVE DATA) Figure 8. Serial Port: Synchronous Mode 0 Integrated Silicon Solution, Inc. ADVANCE INFORMATION SR8199580C51 SR8199580C51 Rev. A 1295 11 ISSI IS80C51 IS80C51 ® TRANSMIT INTERRUPT 9TH DATA BIT SCON (SERIAL CONTROL) INTERNAL DATA BUS CONTROL AND TIMING CIRCUIT XTAL1 DATA (TRANSMIT/RECEIVE) SBUF (XMIT) 9TH DATA BIT SBUF (RCVR) DIVIDE 4 INPUT SHIFT REGISTER DIVIDE 16 DIVIDE 2 RECEIVER INTERRUPT RxD (RECEIVE DATA) TIMER 1 OVERFLOW Figure 9. Serial Port: UART Mode 1, 2, and 3 Interrupt System External events and the real-time driven on-chip peripherals require service by the CPU asynchronous to the execution of any particular section code. To tie the asynchronous activities of these functions to normal program execution, a sophisticated multiple- Interrupt Source source, two-priority-level, nested interrupt system is provided. The interrupt system is shown in Figure 10. The interrupt request flag and program memory location of interrupt service program is shown in the table below: Request Flag Bit Location Start Address External Request 0 IE0 TCON.1 3 (0003H 0003H) Internal Timer 0/Counter 0 TF0 TCON.5 11 (000BH 000BH) External Request 1 IE1 TCON.3 19 (0013H 0013H) Internal Timer 1/Counter 1 TF1 TCON.7 27 (001BH 001BH) Internal Serial Port (XMIT) TI SCON.1 35 (0023H 0023H) INTERNAL SERIAL PORT (RCVR) 12 RI SCON.0 35 (0023H 0023H) Integrated Silicon Solution, Inc. ADVANCE INFORMATION Rev. A 1295 SR8199580C51 SR8199580C51 ISSI IS80C51 IS80C51 ® POLLING HARDWARE TCON1 INT0 IE.0 IE.7 EXTERNAL INT RQST 0 IE0 EX0 PX0 TCON5 IE.1 IP.1 TF0 ET0 PT0 TCON7 IE.2 IP.2 EXTERNAL INT RQST 1 TF1 EX1 PX1 TCON7 IE.3 IP.3 TF1 ET1 PT1 SCON 0 INTERNAL T1 SERIAL SCON 1 PORT Rx IE.4 IP.4 INTERNAL TIMER 0 INT1 HIGH PRIORITY INTERRUPT REQUEST IP.0 SOURCE I.D. VECTOR INTERNAL TIMER 1 ES EA LOW PRIORITY INTERRUPT REQUEST PS SOURCE I.D. VECTOR Figure 10. Interrupt System Integrated Silicon Solution, Inc. ADVANCE INFORMATION SR8199580C51 SR8199580C51 Rev. A 1295 13 ISSI IS80C51 IS80C51 ® INSTRUCTION DEFINITIONS ACALL addr11 Function: Bytes: Cycles: Encoding: Absolute call 2 2 a10 a9 a8 1 0 0 1 a7 a6 a5 a4 a3 a2 a1 a0 Operation: ACALL (PC) (SP) (SP) (SP) (SP) (PC10-0 PC10-0) ADD A, Function: Add ADD Bytes: Cycles: Encoding: A,Rn 1 1 0 Operation: ADD Bytes: Cycles: Encoding: Operation: ADD Bytes: Cycles: Encoding: ADD Bytes: Cycles: Encoding: 0 0 1 r r r (A) + (Rn) 1 0 (A) 0 1 0 1 direct address (A) + (direct) A,@Ri 1 1 0 1 0 (A) 0 1 1 i (A) + (Ri) A, #data 2 1 0 Operation: 1 A, direct 2 1 0 Operation: 0 (A) 0 14 (PC) + 2 (SP) + 1 (PC7-0) (SP) + 1 (PC15-8 PC15-8) page address (A) 0 1 0 0 1 0 0 immediate data (A) + #data Integrated Silicon Solution, Inc. ADVANCE INFORMATION Rev. A 1295 SR8199580C51 SR8199580C51 ISSI IS80C51 IS80C51 ADDC ® A, Function: Add with carry ADDC Bytes: Cycles: Encoding: A,Rn 1 1 0 Operation: ADDC Bytes: Cycles: Encoding: ADDC Bytes: Cycles: Encoding: ADDC Bytes: Cycles: Encoding: AJMP Function: Bytes: Cycles: Encoding: 0 1 1 r r r 0 1 0 1 direct address (A) + (direct) + (C) A,@Ri 1 1 0 1 1 (A) 0 1 1 i (A) + (Ri) + (C) A, #data 2 1 (A) 0 1 1 0 1 0 0 immediate data (A) + #data + (C) addr11 Absolute jump 2 2 a10 a9 a8 0 Operation: (PC) (PC10-0 PC10-0) Integrated Silicon Solution, Inc. ADVANCE INFORMATION SR8199580C51 SR8199580C51 1 (A) + (Rn) + (C) (A) 0 Operation: 1 A,direct 2 1 0 Operation: 1 (A) 0 Operation: 0 Rev. A 1295 0 0 1 a7 a6 a5 a4 a3 a2 a1 a0 (PC) + 2 page address 15 ISSI IS80C51 IS80C51 ® ANL , Function: Logcal-AND for byte variables ANL Bytes: Cycles: Encoding: A,Rn 1 1 0 Operation: ANL Bytes: Cycles: Encoding: ANL Bytes: Cycles: Encoding: ANL Bytes: Cycles: Encoding: ANL Bytes: Cycles: Encoding: ANL Bytes: Cycles: Encoding: 16 r r r (A) & (Rn) 0 1 1 0 1 0 1 direct address (A) & (direct) 0 1 (A) 0 1 1 i (A) & (Ri) A, #data 2 1 1 0 1 (A) 0 1 0 0 immediate data 0 direct address 1 direct address (A) & #data direct,A 2 1 1 0 1 (A) 0 0 1 (direct) & (A) direct, #data 3 2 0 Operation: 1 A,@Ri 1 1 0 Operation: 1 (A) 0 Operation: 1 A,direct 2 1 0 Operation: 0 (A) 0 Operation: 1 1 0 (direct) 1 0 0 1 immediate data (direct) & #data Integrated Silicon Solution, Inc. ADVANCE INFORMATION Rev. A 1295 SR8199580C51 SR8199580C51 ISSI IS80C51 IS80C51 ANL ® C, Function: Logcal-AND for bit variables ANL Bytes: Cycles: Encoding: C, bit 2 2 1 Operation: ANL Bytes: Cycles: Encoding: 0 0 (C) 0 0 1 0 bit address 0 bit address (C) & (bit) C, /bit 2 2 1 Operation: CJNE 0 0 1 1 (C) 0 0 0 (C) & /(bit) ,rel Function: Compare and jump if not equal CJNE Bytes: Cycles: Encoding: A,direct,rel 3 2 1 Operation: CJNE Bytes: Cycles: Encoding: 1 1 1 0 1 direct address rel. address and (C) 0 and (C) 1 A, #data,rel 3 2 0 1 1 0 1 0 0 (PC) (PC) + 3 IF #data < (A) THEN (PC) (PC) + rel OR IF #data > (A) THEN (PC) (PC) + rel Integrated Silicon Solution, Inc. ADVANCE INFORMATION SR8199580C51 SR8199580C51 0 (PC) (PC) + 3 IF (direct) < (A) THEN (PC) (PC) + rel OR IF (direct) > (A) THEN (PC) (PC) + rel 1 Operation: 0 Rev. A 1295 immediate data rel. address and (C) 0 and (C) 1 17 ISSI IS80C51 IS80C51 CJNE ,rel (continued) CJNE Bytes: Cycles: Encoding: Rn, #data,rel 3 2 1 Operation: CJNE Bytes: Cycles: Encoding: Operation: 0 1 1 1 r r r (PC) (PC) + 3 IF #data < (Rn) THEN (PC) (PC) + rel OR IF #data > (Rn) THEN (PC) (PC) + rel immediate data rel. address and (C) 0 and (C) 1 @Ri, #data,rel 3 2 1 CLR ® 0 1 1 0 1 1 i (PC) (PC) + 3 IF #data < (Ri) THEN (PC) (PC) + rel OR IF #data > (Ri) THEN (PC) (PC) + rel immediate data rel. address and (C) and (C) 1 0 A Function: Bytes: Cycles: Encoding: Clear accumulator 1 1 1 1 1 0 0 1 0 0 Operation: (A) 0 18 Integrated Silicon Solution, Inc. ADVANCE INFORMATION Rev. A 1295 SR8199580C51 SR8199580C51 ISSI IS80C51 IS80C51 ® CLR bit Function: CLR Bytes: Cycles: Encoding: Clear bit C 1 1 1 Operation: CLR Bytes: Cycles: Encoding: CPL 0 (C) bit 2 1 1 Operation: 1 1 0 0 0 1 1 0 0 0 1 0 0 0 (bit) bit address 0 A Function: Bytes: Cycles: Encoding: Complement accumulator 1 1 1 1 1 1 0 1 0 0 0 0 1 1 0 0 1 0 Operation: (A) /(A) CLR bit Function: CLR Bytes: Cycles: Encoding: Complement bit C 1 1 1 Operation: CLR Bytes: Cycles: Encoding: 1 (C) bit 2 1 1 Operation: 0 0 1 /(C) 1 (bit) 1 /(bit) Integrated Silicon Solution, Inc. ADVANCE INFORMATION SR8199580C51 SR8199580C51 Rev. A 1295 bit address 19 ISSI IS80C51 IS80C51 DA A Function: Bytes: Cycles: Encoding: Decimal-adjust accumulator for addition 1 1 1 Operation: DEC 1 0 1 0 1 0 0 -contents of accumulator are BCD IF [[(A3-0) > 9] || [(AC) = 1]] THEN (A3-0) (A3-0) + 6 AND IF [[(A7-4) > 9] || [(C) = 1]] THEN (A7-4) (A7-4) + 6 byte Function: Decrement DEC Bytes: Cycles: Encoding: A 1 1 0 Operation: 0 0 1 (A) DEC Bytes: Cycles: Encoding: 0 1 0 0 r r 0 1 Rn 1 1 0 Operation: DEC Bytes: Cycles: Encoding: Operation: DEC Bytes: Cycles: Encoding: 0 (A) - 1 1 1 r (Rn) - 1 direct 2 1 0 0 1 (direct) 0 1 direct address (direct) - 1 @Ri 1 1 0 Operation: 0 (Rn) 0 20 ® 0 0 (Ri) 1 0 1 1 i (Ri) - 1 Integrated Silicon Solution, Inc. ADVANCE INFORMATION Rev. A 1295 SR8199580C51 SR8199580C51 ISSI IS80C51 IS80C51 DIV ® AB Function: Divide Bytes: Cycles: Encoding: 1 4 1 Operation: DJNE 0 0 0 0 (A)15-8 (B)7-0 1 0 0 (A)/(B) MOD(A)/(B) , Function: Decrease and jump if not zero DJNE Bytes: Cycles: Encoding: Rn,rel 2 2 1 Operation: DJNE Bytes: Cycles: Encoding: 0 1 1 0 1 r r r rel. address 0 1 0 1 direct address rel. address (PC) (PC) + 2 (direct) (direct) - 1 IF (direct) > 0 or (direct) < 0 THEN (PC) (PC) + rel Integrated Silicon Solution, Inc. ADVANCE INFORMATION SR8199580C51 SR8199580C51 1 (PC) (PC) + 2 (Rn) (Rn) - 1 IF (Rn) > 0 or (Rn) < 0 THEN (PC) (PC) + rel direct,rel 3 2 1 Operation: 1 Rev. A 1295 21 ISSI IS80C51 IS80C51 INC byte Function: Increment INC Bytes: Cycles: Encoding: A 1 1 0 Operation: 0 0 0 (A) INC Bytes: Cycles: Encoding: 0 1 0 0 r r 0 1 Rn 1 1 0 Operation: INC Bytes: Cycles: Encoding: Operation: INC Bytes: Cycles: Encoding: INC 0 (A) + 1 0 1 r (Rn) + 1 direct 2 1 0 0 0 (direct) 0 1 direct address (direct) + 1 @Ri 1 1 0 Operation: 0 (Rn) 0 0 0 0 0 1 1 i (Ri) (Ri) + 1 DPTR Function: Bytes: Cycles: Encoding: Increment data pointer 1 2 1 Operation: 22 ® 0 (DPTR) 1 0 0 0 1 1 (DPTR) + 1 Integrated Silicon Solution, Inc. ADVANCE INFORMATION Rev. A 1295 SR8199580C51 SR8199580C51 ISSI IS80C51 IS80C51 JB bit,rel Function: Bytes: Cycles: Encoding: Jump if bit set 3 2 0 Operation: JBC 0 1 0 Bytes: Cycles: Encoding: 0 0 0 bit address rel. address bit address rel. address (PC) (PC) + 3 IF (bit) = 1 THEN (PC) (PC) + rel Jump if bit set and clear bit 3 2 0 Operation: 0 0 1 0 0 0 0 (PC) (PC) + 3 IF (bit) = 1 THEN (bit) 0 (PC) (PC) + rel rel Function: Bytes: Cycles: Encoding: Jump carry if bit set and clear bit 2 2 0 Operation: 1 0 0 0 0 0 0 rel address (PC) (PC) + 2 IF (C) = 1 THEN (PC) (PC) + rel Integrated Silicon Solution, Inc. ADVANCE INFORMATION SR8199580C51 SR8199580C51 0 bit,rel Function: JC ® Rev. A 1295 23 ISSI IS80C51 IS80C51 JMP @A+DPTR Function: Bytes: Cycles: Encoding: Jump indirect 1 2 0 Operation: JNB Bytes: Cycles: Encoding: 1 1 (PC) 0 0 1 1 (A) + (DPTR) Jump if bit not set 3 2 0 Operation: 0 1 1 0 0 0 0 bit address rel. address (PC) (PC) + 3 IF (bit) = 0 THEN (PC) (PC) + rel rel Function: Bytes: Cycles: Encoding: Jump if carry not set 2 2 0 Operation: 24 1 bit,rel Function: JNC ® 1 0 1 0 0 0 0 rel. address (PC) (PC) + 2 IF (C) = 0 THEN (PC) (PC) + rel Integrated Silicon Solution, Inc. ADVANCE INFORMATION Rev. A 1295 SR8199580C51 SR8199580C51 ISSI IS80C51 IS80C51 JNZ rel Function: Bytes: Cycles: Encoding: Jump if accumulator not zero 2 2 0 Operation: JZ ® 1 1 1 0 0 0 0 rel. address (PC) (PC) + 2 IF (A) not equal to 0 THEN (PC) (PC) + rel rel Function: Bytes: Cycles: Encoding: Jump if accumulator zero 2 2 0 Operation: LCALL Function: Bytes: Cycles: Encoding: 1 0 0 0 0 rel. address addr16 Long call 3 2 0 (PC) (SP) (SP) (SP) (SP) (PC) 0 1 ADVANCE INFORMATION 0 0 1 0 addr15-addr8 addr7-addr0 (PC) + 3 (SP) + 1 (PC7-0) (SP) + 1 (PC15-8 PC15-8) addr15-0 Integrated Silicon Solution, Inc. SR8199580C51 SR8199580C51 0 (PC) (PC) + 2 IF (A) = 0 THEN (PC) (PC) + rel 0 Operation: 1 Rev. A 1295 25 ISSI IS80C51 IS80C51 LJMP addr16 Function: Long jump Bytes: Cycles: Encoding: 3 2 0 Operation: MOV 0 0 0 (PC) 0 0 1 0 addr15-addr8 addr7-addr0 addr15-0 , Function: Move byte variable MOV Bytes: Cycles: Encoding: A,Rn 1 1 1 Operation: MOV Bytes: Cycles: Encoding: Operation: MOV Bytes: Cycles: Encoding: MOV Bytes: Cycles: Encoding: MOV Bytes: Cycles: Encoding: 1 r r r 1 0 1 1 1 i 1 0 0 r r (Rn) 1 1 0 0 direct address (direct) A,@Ri 1 1 1 1 0 (A) 0 (Ri) A, #data 2 1 1 1 1 (A) 0 immediate data #data Rn,A 1 1 1 Operation: 0 (A) 0 Operation: 1 A,direct 2 1 1 Operation: 1 (A) 1 26 ® (Rn) 1 1 1 1 r (A) Integrated Silicon Solution, Inc. ADVANCE INFORMATION Rev. A 1295 SR8199580C51 SR8199580C51 ISSI IS80C51 IS80C51 MOV Bytes: Cycles: Encoding: Rn,direct 2 2 1 Operation: MOV Bytes: Cycles: Encoding: 0 MOV Bytes: Cycles: Encoding: MOV Bytes: Cycles: Encoding: MOV Bytes: Cycles: Encoding: MOV Bytes: Cycles: Encoding: MOV Bytes: Cycles: Encoding: 1 r direct address r r r immediate data 0 1 0 1 direct address 1 1 r r r direct address 1 0 1 dir. addr. (src) 1 1 i direct address 1 0 1 direct address 1 #data 1 1 1 A 0 0 0 (direct) (Rn) direct,direct 3 2 0 0 0 (direct) 0 dir. addr. (dest) (direct) direct,@Ri 2 2 0 0 0 (direct) 0 (Ri) direct, #data 3 2 1 1 1 (direct) Integrated Silicon Solution, Inc. ADVANCE INFORMATION SR8199580C51 SR8199580C51 r direct,Rn 2 2 0 Operation: r (direct) (direct) 1 Operation: 1 direct,A 2 1 1 Operation: 1 (Rn) 1 Operation: 0 Rn, #data 2 1 1 Operation: 1 (Rn) 0 Operation: ® Rev. A 1295 0 immediate data #data 27 ISSI IS80C51 IS80C51 MOV Bytes: Cycles: Encoding: Ri, A 1 1 1 Operation: MOV Bytes: Cycles: Encoding: MOV Bytes: Cycles: Encoding: MOV 1 1 0 1 1 i 1 1 i direct address 1 i immediate data (A) @Ri,direct 2 2 0 1 0 (Ri) 0 (direct) @Ri, #data 2 1 0 Operation: 1 (Ri) 1 Operation: ® 1 1 1 (Ri) 0 1 #data , Function: Move bit data MOV Bytes: Cycles: Encoding: C, bit 2 1 1 Operation: MOV Bytes: Cycles: Encoding: 28 1 0 (C) 0 0 1 0 bit address 0 1 0 bit address (bit) bit,C 2 2 1 Operation: 0 (bit) 0 0 1 0 (C) Integrated Silicon Solution, Inc. ADVANCE INFORMATION Rev. A 1295 SR8199580C51 SR8199580C51 ISSI IS80C51 IS80C51 MOV ® DPTR, #data16 Function: Bytes: Cycles: Encoding: Load data pointer with a 16-bit constant 3 2 1 Operation: MOVC 0 0 1 0 (DPTR) DPH+_DPL 0 0 0 immed. data15-8 immed. data7-0 (#data15-0) #data15-8+_#data7-0 A, @A + Function: Move code byte MOVC Bytes: Cycles: Encoding: A, @A + DPTR 1 2 1 Operation: MOVC Bytes: Cycles: Encoding: 0 MOV X 1 (A) 0 0 1 1 (A) + (DPTR) A, @A + PC 1 2 1 Operation: 0 0 0 0 0 0 1 1 (PC) + 1 (A) + (PC) (PC) (A) , Function: Move external MOVX Bytes: Cycles: Encoding: A,@Ri 1 2 1 Operation: (A) 1 1 0 Integrated Silicon Solution, Inc. ADVANCE INFORMATION SR8199580C51 SR8199580C51 Rev. A 1295 0 0 1 i (Ri) 29 ISSI IS80C51 IS80C51 MOV X , (continued) MOVX Bytes: Cycles: Encoding: A,@DPTR 1 2 1 Operation: MOVX Bytes: Cycles: Encoding: Operation: MOVX Bytes: Cycles: Encoding: 1 0 0 0 0 0 0 1 i 0 0 0 1 0 0 (DPTR) @Ri,A 1 2 1 1 1 (Ri) 0 (A) @DPTR, A 1 2 1 Operation: 1 (A) 1 MUL ® 1 1 1 (DPTR) 0 (A) AB Function: Bytes: Cycles: Encoding: Multiply 1 4 1 Operation: 0 1 0 0 (A)15-8 (B)7-0 (A) X (B) NOP Function: Bytes: Cycles: Encoding: No operation 1 1 0 Operation: 30 (PC) 0 0 0 0 0 0 0 (PC) + 1 Integrated Silicon Solution, Inc. ADVANCE INFORMATION Rev. A 1295 SR8199580C51 SR8199580C51 ISSI IS80C51 IS80C51 ORL ® , Function: Logical-or for byte variables ORL Bytes: Cycles: Encoding: A,Rn 1 1 0 1 0 0 1 r r r 0 0 0 1 0 1 Operation: (A) ORL Bytes: Cycles: Encoding: (A) || (Rn) A,direct 2 1 0 Operation: ORL Bytes: Cycles: Encoding: ORL Bytes: Cycles: Encoding: ORL Bytes: Cycles: Encoding: ORL Bytes: Cycles: Encoding: (A) || (direct) 0 0 1 1 i 0 0 immediate data 0 direct address 1 direct addr. (A) || (Ri) 1 0 0 (A) 0 1 (A) || #data direct,A 2 1 1 0 0 (direct) 0 0 1 (direct) || (A) direct, #data 3 2 1 0 0 (direct) Integrated Silicon Solution, Inc. ADVANCE INFORMATION SR8199580C51 SR8199580C51 0 A, #data 2 1 0 Operation: 1 (A) 0 Operation: direct address A,@Ri 1 1 0 Operation: (A) 0 Operation: 1 Rev. A 1295 0 0 1 immediate data (direct) || #data 31 ISSI IS80C51 IS80C51 ORL C, Function: Logical-or for bit variables ORL Bytes: Cycles: Encoding: C, bit 2 2 0 Operation: ORL Bytes: Cycles: Encoding: Operation: POP 1 1 1 (C) 0 0 1 0 bit address 0 bit address 0 0 direct address 0 0 direct address (C) || (bit) C, bit 2 2 1 0 1 0 (C) 0 0 0 (C) || /(bit) direct Function: Bytes: Cycles: Encoding: Pop from stack 2 2 1 Operation: PUSH Function: Bytes: Cycles: Encoding: Operation: 1 0 1 0 0 (direct) (SP) (SP) (SP) - 1 direct Push onto stack 2 2 1 32 ® 1 0 0 0 0 (SP) (SP) + 1 (SP) (direct) Integrated Silicon Solution, Inc. ADVANCE INFORMATION Rev. A 1295 SR8199580C51 SR8199580C51 ISSI IS80C51 IS80C51 ® RET Function: Bytes: Cycles: Encoding: Return from subroutine 1 2 0 Operation: 0 1 0 (PC15-8 PC15-8) (SP) (PC7-0) (SP) 0 0 1 0 1 0 (SP) (SP) - 1 (SP) (SP) - 1 RETI Function: Bytes: Cycles: Encoding: Return from interrupt 1 2 0 Operation: RL 0 1 1 (PC15-8 PC15-8) (SP) (PC7-0) (SP) 0 (SP) (SP) - 1 (SP) (SP) - 1 A Function: Bytes: Cycles: Encoding: Rotate accumulator left 1 1 0 Operation: 0 1 0 0 0 1 1 (An+1) (An) n=0-6 (A0) (A7) Integrated Silicon Solution, Inc. ADVANCE INFORMATION SR8199580C51 SR8199580C51 0 Rev. A 1295 33 ISSI IS80C51 IS80C51 RLC A Function: Rotate accumulator left through the carry flag Bytes: Cycles: Encoding: 1 1 0 Operation: RR 0 1 1 (An+1) (A0) (C) 0 0 1 1 (An) n=0-6 (C) (A7) A Function: Rotate accumulator right Bytes: Cycles: Encoding: 1 1 0 0 Operation: RRC 0 0 0 0 1 1 (An+1) n=0-6 (A0) (An) (A7) A Function: Bytes: Cycles: Encoding: Rotate accumulator right through the carry flag 1 1 0 Operation: (An) (A7) (C) 34 ® 0 0 1 0 0 1 1 (An+1) n=0-6 (C) (A0) Integrated Silicon Solution, Inc. ADVANCE INFORMATION Rev. A 1295 SR8199580C51 SR8199580C51 ISSI IS80C51 IS80C51 SETB ® Function: Set bit SETB Bytes: Cycles: Encoding: C 1 1 1 Operation: 0 1 (C) SETB Bytes: Cycles: Encoding: 1 0 0 1 1 0 0 1 0 bit address 0 0 0 0 rel. address r r bit 2 1 1 Operation: SJMP 1 0 1 1 (bit) 1 rel Function: Bytes: Cycles: Encoding: Short jump 2 2 1 0 Operation: 0 (PC) + 2 (PC) + rel (PC) (PC) SUBB 0 A, Function: Add with carry SUBB Bytes: Cycles: Encoding: A,Rn 1 1 1 Operation: (A) 0 0 1 Integrated Silicon Solution, Inc. ADVANCE INFORMATION SR8199580C51 SR8199580C51 Rev. A 1295 1 r (A) - (Rn) - (C) 35 ISSI IS80C51 IS80C51 SUBB SUBB Bytes: Cycles: Encoding: A, (continued) A,direct 2 1 1 Operation: SUBB Bytes: Cycles: Encoding: SUBB Bytes: Cycles: Encoding: SWAP Function: Bytes: Cycles: Encoding: 36 1 0 0 1 0 1 direct address (A) - (direct) - (C) 0 1 (A) 0 1 1 i (A) - (Ri) - (C) A, #data 2 1 0 0 1 (A) 0 1 0 0 immediate data (A) - #data - (C) A Swap nibbles within the accumulator 1 1 1 Operation: 0 A,@Ri 1 1 1 Operation: 0 (A) 1 Operation: ® 1 0 (A3-0) 0 0 1 0 0 (A7-4) Integrated Silicon Solution, Inc. ADVANCE INFORMATION Rev. A 1295 SR8199580C51 SR8199580C51 ISSI IS80C51 IS80C51 XCH ® A, Function: Exchange accumulator with byte variable XCH Bytes: Cycles: Encoding: A,Rn 1 1 1 Operation: XCH Bytes: Cycles: Encoding: XCH Bytes: Cycles: Encoding: 0 1 r r r 1 0 1 1 1 i 1 1 i (Rn) A,direct 2 1 1 0 0 (A) 0 direct address (direct) A,@Ri 1 1 1 Operation: 0 (A) 1 Operation: 1 1 0 0 (A) 0 (Ri) XCHD A,@Ri Function: Bytes: Cycles: Encoding: Exchange digit 1 1 1 Operation: 1 0 1 (A3-0) Integrated Silicon Solution, Inc. ADVANCE INFORMATION SR8199580C51 SR8199580C51 Rev. A 1295 1 (Ri3-0) 37 ISSI IS80C51 IS80C51 XRL , Function: Logical exclusive-or for byte variables XRL Bytes: Cycles: Encoding: A,Rn 1 1 0 Operation: XRL Bytes: Cycles: Encoding: Operation: XRL Bytes: Cycles: Encoding: XRL Bytes: Cycles: Encoding: XRL Bytes: Cycles: Encoding: XRL Bytes: Cycles: Encoding: 1 1 r r r (A) XOR (Rn) 0 0 1 0 1 direct address (A) XOR (direct) 1 1 0 (A) 0 1 1 i (A) XOR (Ri) A, #data 2 1 1 1 0 (A) 0 1 0 0 immediate data (A) XOR #data direct,A 2 1 1 1 0 (direct) 0 0 1 0 direct address (direct) XOR (A) direct, #data 3 2 0 Operation: 1 A,@Ri 1 1 0 Operation: 0 (A) 0 Operation: 1 A,direct 2 1 0 Operation: 1 (A) 0 38 ® 1 0 (direct) 0 0 0 1 1 direct address immediate data (direct) XOR #data Integrated Silicon Solution, Inc. ADVANCE INFORMATION Rev. A 1295 SR8199580C51 SR8199580C51 ISSI IS80C51 IS80C51 ® ADDITIONAL INFORMATION Idle mode Power down mode In idle mode, the CPU puts itself to sleep while all the on-chip perpherals remain active. The mode is invoked by software. The content of the on-chip RAM and all the Special Function Register remain unchanged during this mode. The idle mode can be terminated by any enabled interrupt or by a hardware reset. In the power down mode the oscillator is stopped, and the instruction that invokes power down is the last instruction executed. The on-chip RAM and special function register retain their values until the power down mode is terminated. It should be noted that when idle is terminated by a hardware reset, the device normally resumes program exection, from where it left off, up to two machine cycles before the internal reset algorithm takes control. On-chip hardware inhibits access to internal RAM in this event, but access to the port pins is not inhibited. To eliminate the possibility of an unexpected write to a port pin when idle is terminated by reset, the instruction following the one that invokes idle should not be one that writes to a port pin or to external memory. The status of external pins is shown in the following table. The only exit from power down mode is a hardware reset. Reset redefines the SFR but does not change the on-chip RAM. The reset should not be activated before VCC is restored to its normal operating level and must be held active long enough to allow the oscillator to restart and stabilize. The status of the external pins during idle and power-down mode is shown in the following table. Mode Memory ALE PSEN PORT 0 PORT 1 PORT 2 PORT 3 Idle Internal 1 1 Data Data Data Data Idle External 1 1 Float Data Address Data Power-down Internal 0 0 Data Data Data Data Power-down External 0 0 Float Data Data Data Integrated Silicon Solution, Inc. ADVANCE INFORMATION SR8199580C51 SR8199580C51 Rev. A 1295 39 ISSI IS80C51 IS80C51 ® ROM verification The address of the program memory location to be read is applied to Port 1 and pins P2.3-P2.0. The other pins should be held at the "Verify" level indicate in Figure 11. The contents of the addressed locations will come out on Port 0. External pullups are required on Port 0 for this operation. Figure 11 shows the setup for verify the program memory. +5V A7-A0 P1 A11-A8 A11-A8 P2.3 ­P2.0 1 EA 1 ALE 0 PSEN 0 P2.7 0 P2.6 1 10K x 8 RST 1 Vcc DUMP P0 PGM DATA XTAL1 XTAL2 GND Figure 11. ROM verification (Note: DUMP is internal pad.) 40 Integrated Silicon Solution, Inc. ADVANCE INFORMATION Rev. A 1295 SR8199580C51 SR8199580C51 ISSI IS80C51 IS80C51 ® ABSOLUTE MAXIMUM RATINGS(1) Symbol VTERM TBIAS TSTG PT Parameter Terminal Voltage with Respect to GND Temperature Under Bias Storage Temperature Power Dissipation Value ­2.0 to +7.0 0 to +70 ­65 to +125 1.5 Unit V °C °C W Note: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. OPERATING RANGE(1) Range Commercial Ambient Temperature 0°C to +70°C VCC 5V ± 10% Oscillator Frequency 3.5 to 24 MHz Note: 1. Operating ranges define those limits between which the functionality of the device is guaranteed. Integrated Silicon Solution, Inc. ADVANCE INFORMATION SR8199580C51 SR8199580C51 Rev. A 1295 41 ISSI IS80C51 IS80C51 ® DC CHARACTERISTICS (TA = 0°C to 70°C; Vcc = 4.75V to 5.25V; GND = 0V) Symbol Parameter Test conditions VIL Input low voltage VIL1 Input low voltage VIH Input high voltage (All except XTAL 1, RST) VIH1 Input high voltage (XTAL 1) VSCH+ RST positive schmitt-trigger threshold voltage VSCH­ RST negative schmitt-trigger threshold voltage VOL(1) Output low voltage IOL = 100 µA (Ports 1, 2, and 3) IOL = 1.6 mA IOL = 3.5 mA (1) VOL1 Output low voltage IOL = 200 µA (Port 0, ALE, PSEN) IOL = 3.2 mA IOL = 7.0 mA VOH Output high voltage IOH = ­10 µA (Port 1, 2, 3, ALE, PSEN) Vcc = 4.5V~5.5V IOL = ­25 µA IOL = ­60 µA VOH1 Output high voltage IOH = ­80 µA (Port 0, ALE, PSEN) Vcc = 4.5~5.5V IOH = ­300 µA IOH = ­800 µA IIL Logical 0 input current (Port 1, 2, 3) VIN = 0.45V Ili Input leakage current (Port 0) 0.45V < VIN < Vcc ITL Logical 1-to-0 transition current VIN = 2.0V (Port 1, 2, 3) RRST RST pulldown resister Min Max ­0.5 0.2Vcc ­ 0.1 ­0.5 0.2Vcc ­ 0.3 0.2Vcc + 0.9 Vcc + 0.5 Unit V V V 0.7Vcc 0.7Vcc Vcc + 0.5 Vcc + 0.5 V V 0 0.3Vcc V - - - - - - 0.9Vcc 0.3 0.45 1.0 0.3 0.45 1.0 - V V V V V V V 0.75Vcc 2.4 0.9Vcc - - - V V V 0.75Vcc 2.4 - ­10 - - - ­50 +10 ­650 V V µA µA µA 50 300 Kohm Notes: 1. Under steady state (non-transient) conditions, Iol must be externally limited as follows: 10 mA Maximum IOL per port pin: Maximum IOL per 8-bit port Port 0: 26 mA Port 1, 2, 3: 15 mA Maximum total IOL for all output pins: 71 mA If Iol exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink greater than the listed test conditions. 42 Integrated Silicon Solution, Inc. ADVANCE INFORMATION Rev. A 1295 SR8199580C51 SR8199580C51 ISSI IS80C51 IS80C51 ® POWER SUPPLY CHARACTERISTICS Symbol Icc Parameter Power supply current(1) Active mode Test conditions Min Idle mode Power-down mode Unit - - - - - - - - - 12 MHz 16 MHz 20 MHz 24 MHz 12 MHz 16 MHz 20 MHz 24 MHz Max 50 50 50 50 50 50 50 50 50 mA mA mA mA mA mA mA mA mA Note: 1. See Figures 12, 13, 14, and 15 for Icc test conditiions. Vcc Vcc Icc RST Icc Vcc RST Vcc Vcc Vcc NC CLOCK SIGNAL XTAL2 P0 NC CLOCK SIGNAL XTAL1 GND EA XTAL2 P0 XTAL1 GND Figure 12. Active Mode EA Figure 13. Idle Mode Vcc Icc RST Vcc Vcc NC XTAL2 P0 XTAL1 GND EA Figure 14. Power-down Mode Integrated Silicon Solution, Inc. ADVANCE INFORMATION SR8199580C51 SR8199580C51 Rev. A 1295 43 ISSI IS80C51 IS80C51 tCLCX Vcc ­ 0.5V 0.45V ® tCHCX 0.7Vcc 0.2Vcc ­ 0.1 tCHCL tCLCH tCLCL Figure 15. Icc Test Conditions Clock signal waveform for Icc tests in active and idle mode ( tCLCH = tCHCL = 5 ns) AC CHARACTERISTICS (TA = 0°C to 70°C; Vcc = 4.75V to 5.25V; GND = 0V; CL for Port 0, ALE and PSEN; Outputs = 100 pF; CL for other outputs = 80 pF) External Memory Characteristics Symbol 1/tCLCL tLHLL tAVLL tLLAX tLLIV tLLPL tPLPH tPLIV tPXIX tPXIZ tAVIV tPLAZ tRLRH tWLWH tRLDV tRHDX tRHDZ tLLDV tAVDV tLLWL tAVWL tQVWX tWHQX tQVWH tRLAZ tWHLH 44 Parameter Oscillator frequency ALE pulse width Address valid to ALE low Address hold after ALE low ALE low to valid instr in ALE low to PSEN low PSEN pulse width PSEN low to valid instr in Input instr hold after PSEN Input instr float after PSEN Address to valid instr in PSEN low to address float RD pulse width WR pulse width RD low to valid data in Data hold after RD Data float after RD ALE low to valid data in Address to valid data in ALE low to RD or WR low Address to RD or WR low Data valid to WR transition Data hold after WR Data valid to WR high RD low to address float RD or WR high to ALE high 12 MHz Clock Min Max - - 127 - 28 - 48 - - - 43 - 205 - - - 0 - - - - 312 - 10 400 - 400 - - 252 0 - - 97 - 517 - - 200 300 - - 23 - - - - - - 0 43 123 24 MHz Clock Min Max - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Variable Oscillator Min Max Unit 3.5 24 MHz 2tCLCL­40 - ns tCLCL­55 - ns tCLCL­35 - ns - 4tCLCL­75 ns tCLCL­40 - ns 3tCLCL­45 - ns - 3tCLCL­105 ns 0 - ns - tCLCL­20 ns - 5tCLCL­105 ns - 10 ns 6tCLCL­100 - ns 6tCLCL­100 - ns - 5tCLCL­95 ns 0 - ns - 2tCLCL­70 ns - 8tCLCL­90 ns - 9tCLCL­90 ns 3tCLCL­50 3tCLCL+50 ns 4tCLCL­90 - ns tCLCL­60 - ns tCLCL­40 - ns 7tCLCL­70 - ns - 0 ns tCLCL­40 tCLCL+40 ns Integrated Silicon Solution, Inc. ADVANCE INFORMATION Rev. A 1295 SR8199580C51 SR8199580C51 ISSI IS80C51 IS80C51 ® Serial Port Timing: Shift Register Mode 12 MHz Clock Min Max 1.0 - 24 MHz Clock Min Max - - Variable Oscillator Min Max 12tCLCL - Symbol tXLXL Parameter Serial port clock cycle time Unit us tQVXH Output data setup to clock rising edge 700 - - - 10tCLCL­133 - ns tXHQX Output data hold after clock rising edge 50 - - - 2tCLCL­50 - ns tXHDX Input data hold after clock rising edge 0 - - - 0 - ns tXHDV Clock rising edge to input data valid - 700 - - - 10tCLCL­133 ns External Clock Drive Symbol 1/tCLCL Parameter Oscillator Frequency Min 3.5 Max 24 Unit MHz tCHCX High time 20 - ns tCLCX Low time 20 - ns tCLCH Rise time - 20 ns tCHCL Fall time - 20 ns Min 4 Max 6 Unit MHz ROM Verification Characteristics Symbol 1/tCLCL Parameter Oscillator tAVQV Address to data valid - 48tCLCL tELQV ENABLE low to data valid - 48tCLCL tEHQZ Data float after ENABLE 0 48tCLCL Integrated Silicon Solution, Inc. ADVANCE INFORMATION SR8199580C51 SR8199580C51 Rev. A 1295 45 ISSI IS80C51 IS80C51 ® TIMING WAVEFORMS tLHLL ALE tLLPL tPLPH tPLIV tAVLL PSEN tPLAZ tLLAX PORT 0 A7-A0 tPXIX tPXIZ INSTR IN A7-A0 tLLIV tAVIV PORT 2 A15-A8 A15-A8 A15-A8 A15-A8 Figure 16. External Program Memory Read Cycle ALE tWHLH PSEN tLLDV tLLWL RD PORT 0 tAVLL tRLAZ tLLAX tRLRH tRLDV A7-A0 FROM RI OR DPL tRHDZ tRHDX DATA IN A7-A0 FROM PCL INSTR IN tAVWL tAVDV PORT 2 A15-A8 A15-A8 FROM DPH A15-A8 A15-A8 FROM PCH Figure 17. External Data Memory Read Cycle 46 Integrated Silicon Solution, Inc. ADVANCE INFORMATION Rev. A 1295 SR8199580C51 SR8199580C51 ISSI IS80C51 IS80C51 ® ALE tWHLH PSEN tLLWL WR tWLWH tAVLL PORT 0 tWHQX tQVWX tLLAX A7-A0 FROM RI OR DPL DATA OUT A7-A0 FROM PCL INSTR IN tAVWL PORT 2 A15-A8 A15-A8 FROM DPH A15-A8 A15-A8 FROM PCH Figure 18. External Data Memory Write Cycle INSTRUCTION 0 1 2 3 4 5 6 7 8 ALE tXLXL CLOCK tXHQX tQVXH DATAOUT tXHDX tXHDV DATAIN VALID VALID VALID SET TI VALID VALID VALID VALID VALID SET RI Figure 19. Shift Register Mode Timing Waveforms Integrated Silicon Solution, Inc. ADVANCE INFORMATION SR8199580C51 SR8199580C51 Rev. A 1295 47 ISSI IS80C51 IS80C51 tCLCX Vcc ­ 0.5V 0.45V ® tCHCX 0.7Vcc 0.2Vcc ­ 0.1 tCHCL tCLCH tCLCL Figure 20. External Clock Drive Waveform P1.0-P1.7 P2.0-P2.3 ADDRESS PORT 0 DATA OUT tAVQV tELQV tEHQZ P2.7 Figure 21. ROM Verification Waveforms Vcc - 0.5V 0.45V 0.2Vcc + 0.9V 0.2Vcc - 0.1V Figure 22. AC Test Point Note: 1. AC inputs during testing are driven at VCC ­ 0.5V for logic "1" and 0.45V for logic "0". Timing measurements are made at VIH min for logic "1" and max for a logic "0". 48 Integrated Silicon Solution, Inc. ADVANCE INFORMATION Rev. A 1295 SR8199580C51 SR8199580C51 ISSI IS80C51 IS80C51 ® ORDERING INFORMATION Order Part Number Package IS80C51PL IS80C51PL PLCC ­ Plastic Leaded Chip Carrier IS80C51W IS80C51W 600-mil Plastic DIP Integrated Silicon Solution, Inc. ADVANCE INFORMATION SR8199580C51 SR8199580C51 Rev. A 1295 49