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Part : IRQ-5/20-T110N-C Supplier : muRata Manufacturer : Avnet Stock : - Best Price : $74.29 Price Each : $84.49
Part : IRQ-5/20-T110NF-C Supplier : muRata Manufacturer : Avnet Stock : - Best Price : $77.29 Price Each : $87.89
Part : IRQ-5/20-T110NVF-C Supplier : muRata Manufacturer : Avnet Stock : - Best Price : $79.29 Price Each : $90.19
Part : IRQ-5/20-T110P-C Supplier : muRata Manufacturer : Avnet Stock : - Best Price : $74.29 Price Each : $84.49
Part : IRQ-5/20-T110PF-C Supplier : muRata Manufacturer : Avnet Stock : - Best Price : $77.29 Price Each : $87.89
Part : TM18VP6FF100IRQ8 Supplier : Banner Engineering Manufacturer : Allied Electronics & Automation Stock : 42 Best Price : $85.68 Price Each : $92.27
Part : TM18VP6FF25IRQ8 Supplier : Banner Engineering Manufacturer : Allied Electronics & Automation Stock : 5 Best Price : $74.56 Price Each : $78.48
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IRQ15

Catalog Datasheet MFG & Type PDF Document Tags

IRQ11

Abstract: Vadem Purposes Signals *RIO *LED A_GPIO - - A_*VS1 *INTR or IRQ15 (or A_GPIO or B_GPIO) A *INTR or IRQ15 or A_GPIO or B_GPIO *INTR or IRQ15 (or A_GPIO or B_GPIO) A IRQ12 IRQ12 , Socket - v - v - v - v *RIO *INTR or IRQ15 (or A_GPIO or B_GPIO) C *INTR or IRQ15 (or A_GPIO or B_GPIO) C IRQ15 (or A_GPIO or B_GPIO) C IRQ15 (or A_GPIO or B_GPIO) C *INTR or IRQ15 (or A_GPIO or B_GPIO) C *INTR or IRQ15 (or A_GPIO or B_GPIO) C
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VG-469 IRQ11 Vadem AMPHUS

ck32k

Abstract: : IRQ15SR, IRQ15SF =B'01 Interrupt requests are generated on falling edges of IRQ15. tmp = ISR IRQ15F = , requests are generated on falling edges of IRQ15. tmp = ISR IRQ15F = 0 in ISR Clear the IRQ15 status , (IRQ15 interrupt), ensure that bit IRQ15E in the IER and bit SSI15 in the SSIER are both set to 1 and , '000013C REJ06B0678-0100/Rev.1.00 March 2008 Destination Interrupt Function init irq15_int Page 8 of 21 , time in the SEC, MIN, and HOUR members of the TIME structure. main irq15_int main init
Renesas Technology
Original
ck32k H8SX/1663F H8SX/1663 REJ06B0678-0100/R

321-OPTO

Abstract: array Opto Sensor 0 0 0 0 0 0 COM1 IRQ15 COM2 2F8 0 X 0 0 0 0 0 COM2 IRQ15 COM3 348 0 0 X 0 X X 0 IRQ2 IRQ15 COM4 340 0 0 X 0 X X X IRQ5 IRQ15 COM5 248 0 X X 0 X X 0 IRQ10 IRQ15 COM6 240 0 X X 0 X X X IRQ11 IRQ15 X = Jumper
Opto 22
Original
321-OPTO array Opto Sensor AC39 43044S

XTAL 4.00

Abstract: /(IRQ15) TMR x 2 channels P10/PO8/TIOCA0 P11/PO9/TIOCB0 P12/PO10/TIOCC0/TCLKA P13/PO11/TIOCD0 , CPU Clock pulse generator PF7/ PF6/AS PF5/RD PF4/HWR PF3/LWR PF2/LCAS/IRQ15/DQML* PF1/UCAS , /(IRQ15) TMR x 2 channels P10/PO8/TIOCA0 P11/PO9/TIOCB0 P12/PO10/TIOCC0/TCLKA P13/PO11/TIOCD0 , PG0/CS0 Port E Port F PF7/ PF6/AS PF5/RD PF4/HWR PF3/LWR PF2/LCAS/IRQ15/DQML* PF1/UCAS , /TIOCB5/(IRQ15) TMR x 2 channels P10/TIOCA0 P11/TIOCB0 P12/TIOCC0/TCLKA P13/TIOCD0/TCLKB P14
Renesas Technology
Original
XTAL 4.00 PB7/A15 PB6/A14 PB5/A13 PB4/A12 PB3/A11 PB2/A10

VG-468

Abstract: VG-469 A_CDATA[0.15] LA[17.23] IRQ3 IRQ4 IRQ5 IRQ7 IRQ9 IRQ10 IRQ11 IRQ12 IRQ14 IRQ15/*RIO A , IRQ5 IRQ7 IRQ9 IRQ10 IRQ11 IRQ12 IRQ14 IRQ15/*RIO *ZWS *IOCS16 *MEMCS16 IOCHRDY *ZWS , B_*REG A_*CD1 A_*REG IRQ15 VCC/B_*CD1 A_*VS2 B_*CD1/*REG B_*VS2 B_*REG/VCC *SPKROUT B , /SD14 1-2 JP20 *INTR R*SPKOUT A_*VS1 A_GPI B_GPI B_*CD1 B_*REG A_*CD1 A_*REG IRQ15 , _*VS1 *INTR *BSPKROUT PWRGOOD GND/B_D10 B_D10/B_*VS1 GND/B_*VS2 *RIO/A_*VS2 IRQ15/*RIO A_*REG
Vadem
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VG-468 SI9953 VG469 BCDATA11 80-FFH 2N3904 A14 VG-468/469 IRQ15/ SD14/GND GND/SD14 469REF 74HCT04
Abstract: VCC EXTAL XTAL Vss PF7/ PLLVss RES PLLVcc PF6/AS PF5/RD PF4/HWR PF3/LWR PF2/IRQ15/LCAS , )/EDACK2 P83/(IRQ3)/RxD3/ETEND3 P27/PO7/TIOCB5/(IRQ15) P26/PO6/TIOCA5/(IRQ14) P25/PO5/TIOCB4/(IRQ13 , VCC EXTAL XTAL Vss PF7/ PLLVss RES PLLVcc PF6/AS PF5/RD PF4/HWR PF3/LWR PF2/IRQ15/LCAS , /EDACK3 P84/(IRQ4)/EDACK2 P83/(IRQ3)/RxD3/ETEND3 P27/PO7/TIOCB5/(IRQ15) P26/PO6/TIOCA5/(IRQ14) P25 , EXTAL XTAL Vss PF7/ PLLVss RES PLLVcc PF6/AS PF5/RD PF4/HWR PF3/LWR PF2/IRQ15/LCAS PF1/IRQ14 Renesas Technology
Original
LQFP-144 PA0/A16 PA1/A17 PA2/A18 PA3/A19 PA4/A20/IRQ4

TP52

Abstract: PAL22V10 19 18 17 16 15 14 CS IRQ10 IRQ11 IRQ12 IRQ14 IRQ15 DRQ0 DRQ1 DRQ3 IOWZ IORZ SA5 DACK0 DACK1 DACK3 CS TC IORZ VCC1 IRQ10 IRQ11 IRQ12 IRQ14 IRQ15 DRQ0 DRQ1 DRQ3 , 26 27 28 29 30 31 32 IOWZ IRQ10 IRQ11 IRQ12 IRQ15 IRQ14 DACK0 DRQ0 D AEN , 5 TP14 6 TP15 7 TP16 8 1 2 TP60 1 3 TP61 1 1 D IRQ15
Texas Instruments
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TIR2000 PAL22V10 TP52 SA10 SA11 SA12 SA13

ncp72

Abstract: /PO7/ TIOCB5/ EDRAK1/(IRQ15) 60 P60/TMRI0/ DREQ0/IRQ8 61 P61/TMRI1/ DREQ1/IRQ9 62 FWE*1 Vss* 63 64 65 , / TIOCB5/ EDRAK1/(IRQ15) P60/TMRI0/ DREQ0/IRQ8 P61/TMRI1/ DREQ1/IRQ9 FWE*1 Vss* 2 Flash Memory EXPE = 0 , / TIOCA5/ EDRAK0/(IRQ14) P27/PO7/ TIOCB5/ EDRAK1/(IRQ15) P60/TMRI0/ DREQ0/IRQ8 P61/TMRI1/ DREQ1/IRQ9 FWE*1 , / TIOCA5/ EDRAK0/(IRQ14) P27/PO7/ TIOCB5/ EDRAK1/(IRQ15) P60/TMRI0/ DREQ0/IRQ8 P61/TMRI1/ DREQ1/IRQ9 FWE*1 , ) NC NC OE CE WE Vss NC P27/PO7/ TIOCB5/(IRQ15) NC P60/TMRI0/ DREQ0/IRQ8 P61/TMRI1
Hitachi Semiconductor
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ncp72 P65/TMO1/ P64/TMO0/ P63/TMCI1/ P62/TMCI0/ P51/R P50/T

H8S-2377

Abstract: /RxD4/ (IRQ12) 56 P25/PO5/ TIOCB4/ (IRQ13) 57 P26/PO6/ TIOCA5/(IRQ14) 58 P27/PO7/ TIOCB5/(IRQ15) 59 P83 , /(IRQ15) P83/(IRQ3)/ RxD3/ETEND3*2 P84/(IRQ4)/ EDACK2* 2 2 Flash Memory Programmer Mode NC Mode 4 , / TIOCA5/(IRQ14) P27/PO7/ TIOCB5/(IRQ15) P83/(IRQ3)/ RxD3/ETEND3*2 P84/(IRQ4)/ EDACK2* 2 2 EXPE = 1 P17 , /(IRQ14) P27/PO7/ TIOCB5/(IRQ15) P83/(IRQ3)/ RxD3/ETEND3*2 P84/(IRQ4)/ EDACK2* 2 2 EXPE = 0 P17/PO15 , / TIOCB5/(IRQ15) P83/(IRQ3)/ RxD3 P84/(IRQ4) Vss NC NC OE CE WE Vss NC NC NC
Hitachi Semiconductor
Original
H8S-2377 PD7/D15 PD6/D14 PD5/D13 PD4/D12 PD3/D11 PD2/D10

um9008

Abstract: PA6 GF 30 32 33 34 35 36 IO16IRQ10 IRQ11 IRQ12 IRQ15 IRQ3 IRQ4 IRQ5 IRQ9 IRQ10 IRQ11 IRQ12 IRQ15 X2 X1 EECS BPCS LILED TPTX+ TPTXTPRX+ TPRXBNCEN GF2 C1 C2 C3 C4 C5 C6 C7 C8 C9 , IRQ12 IRQ15 MD[0.7] 10K 20 22 27 1 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11
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um9008 PA6 GF 30 PA6 GF 25 PA6 GF 50 PA6 GF 15 PA6 GF 40 AENIOCHRDYMEMWMEMRIO16- VCC16 GF-36 IOCHRDYAENSA19 93C46 UM9008

VG-469 Reference Design #4

Abstract: 3941S-A *IOCS16 IRQ10 IRQ11 IRQ12 IRQ15 IRQ14 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 *MEMCS16 *IOCS16 IRQ10 IRQ11 IRQ12 IRQ15 IRQ14 + C1 33uF + C2 , IRQ12 IRQ15 100 OHM 100 OHM BSD7 100 IRQ4 IRQ7 IRQ10 IRQ12 IRQ15 R15 R16 R17 , IRQ12 IRQ15 R107 100K IRQ4 IRQ7 IRQ10 IRQ12 IRQ15 RSD7 RSD8 RSD9 VCC RSD10 RSD11 , IRQ5 IRQ7 IRQ9 IRQ10 IRQ11 IRQ12 IRQ14 IRQ15 *ZWS *IOCS16 *MEMCS16 IOCHRDY *VSENBL *SIOR
Vadem
Original
SI9933 VG-469 Reference Design #4 3941S-A CON40A BSA16 R113B BLA20 IN5818 MIC2558 LT1117

D001h

Abstract: PC87410 Logic low IRQ15 O TRI-STATE 8 mA Slew Rate Control The output of this pin is equivalent to ISA IRQ15 if HEADER is ``Not connected'' or Logic High However this pin will go to TRI-STATE if , care'') and the setting of channel 0 1 I O base register setting is ``don't care'' IRQ14 IRQ15 , register setting is ``don't care'' IRQ14 off IRQ15 off INTA inversion of CH0 INT if CH0 INT is not , Channel 1 I O is set at ``secondary IDE port'' IRQ15 same value of CH1 INT if CH1 INT is not masked by
National Semiconductor
Original
PC87410 D001h PC87410VLK VLK100A C1995 D-82256

SW-DIP-8

Abstract: sw-dip8 1 -RESET_784 R5 X2 IRQ10 IRQ11 IRQ12 IRQ14 IRQ15 +5V R4 Solder Side IRQ10 IRQ11 IRQ12 IRQ14 IRQ15 IRQ7 IRQ9 C CON_AT36B C20 1 TP10 GND 2 2 2 2 , IRQ10 IRQ11 IRQ12 IRQ15 IRQ14 IRQ10 IRQ11 IRQ12 IRQ15 IRQ14 SBHE LA23 LA22 LA21 LA20 , IRQ12 IRQ15 IRQ14 -DACK0 DREQ0 -DACK5 DREQ5 -DACK6 DREQ6 -DACK7 DREQ7 +5V -MASTER GND 2
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XC9572XL XR16L784 SW-DIP-8 sw-dip8 SW-DIP TP1230 U4 SW-DIP-8 1N914 LT1086CM-3 LT1086CM

IT8888F

Abstract: it8888 # DACK0# IRQ15 IRQ14/ROMCS# IRQ12 IRQ11 IRQ10 IRQ9 IRQ7 IRQ6 IRQ5 IRQ4 IRQ3 53 54 55 56 57 58 59 60 61 62 63 IRQ15 IRQ14/ROMCS# IRQ12 IRQ11 IRQ10 IRQ9 IRQ7 IRQ6 IRQ5 IRQ4 , # DACK5# DACK3# DACK2# DACK1# DACK0# OFF ON Enable SM Boot-ROM Disable SM Boot-ROM IRQ15 C , MEMCS16# IOCS16# IRQ10 IRQ11 IRQ12 IRQ15 IRQ14 DACK0# DRQ0 DACK5# DRQ5 DACK6# DRQ6 DACK7# DRQ7 VCC MASTER# GND MEMCS16# IOCS16# IRQ10 IRQ11 IRQ12 IRQ15 IRQ14 DACK0# DRQ0 DACK5
ITE Tech
Original
IT8888F it8888 271024 EPROM 271024 AD10 AD11 IT8888 IT8888-090998 CON18X2 RP10-10K 318MH

SW-DIP-8

Abstract: sw-dip8 4 3 DRV_RESET D[0.7] D7 D6 D5 D4 D3 D2 D1 D0 2 2 2 2 2 IRQ10 IRQ11 IRQ12 IRQ14 IRQ15 JP6 JP7 JP8 JP9 JP10 D IRQ7 IRQ9 IRQ10 IRQ11 IRQ12 IRQ14 IRQ15 C 1 .1_1206 C17 .1_1206 C16 .1_1206 1 C14 1 2 10_10V_TANT C15 TAB , IRQ12 IRQ15 IRQ14 IRQ10 IRQ11 IRQ12 IRQ15 IRQ14 SBHE LA23 LA22 LA21 LA20 LA19 LA18 , -IO_CHRDY AEN Component Side -MEM CS16 -I/O CS16 IRQ10 IRQ11 IRQ12 IRQ15 IRQ14 -DACK0 DREQ0
Exar
Original
MAX485CPA AT62B SWDIP-8 Header3X2

60N01

Abstract: S IO v cc SCLK CS PNPSO PNPS1 SOUT GND ]14 0 4 ]15 D5 ]16 06 ] " 07 ] « IRQ15 ]19 IRQ3 ]20 IRQ4 ]21 Vcc ]22 IRQS ]23 IRQ6 ]24 IRQ7 ]25 IRQ15 Simple 3-pin interface to SGS-Thomson's EEPROM 2K
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OCR Scan
60N01 TL16PNP550A TL16C550C TL16C450 PNP550A 6PNP550AFN IRQ9-IRQ12

BCD6

Abstract: CLPD6701 IRQ15 24 7 18 9 23 22 21 20 17 16 15 14 1 +3V R110 0/NA 0603B 7,18 SERIRQ 7,18 7,18 PIRQB# PIRQA# 1 1 C227 0.1U 0603B GND IRQ3 IRQ4 IRQ5 IRQ7 IRQ11 IRQ14 IRQ15 7,15,18,19 7,15,18,19 7 , B_A17 B_A18 B_A19 B_A20 B_A21 B_A22 B_A23 B_A24 B_A25 IRQ15/RI_OUT IRQ14/CLKRUN# IRQ12/GND IRQ11/GND
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BCD6 CLPD6701 cl-pd6701 c596 ACA10 ACA11 ACA12 ACA13 ACA14 ACA15

92c178

Abstract: OPTi 82C700 SA2+PP WR2 SA1+PP WR1 SA0+PP WR0 IRQ9 GND IRQ3 IRQ4 IRQ5 VCC_ISA IRQ6 IRQ7 IRQ14 IRQ15 IRQ12 , AD16 I/O PCI 100 IRQ15 PAR I/O PCI 101 IRQ14 I ISA 53 SERR# OD , IRQ15 100 SD5 143 AD3 33 DACK7#+GNT1#+AEN2 24 LOCK# 55 SD6 144 AD4 , 82C825 Signal Name Pin No. Type IRQ15 100 I DRD# 8 I/O Selected By
OPTi
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92c178 OPTi 82C700 Manual ttl 74138 74138 decoder SA21D 3-8 decoder 74138

P-51

Abstract: GND GND IRQ15 IRQ14 IRQ12 IRQ11 IRQ10 IRQ9 IRQ7 IRQ6 IRQ5 IRQ4 IRQ3 45 EISA signals , (from IRQ3 to IRQ15). In this example a standard 8051 uses P0, P2, and control strobes to control a , / IOCS16 IRQ10 IRQ11 IRQ12 IRQ15 IRQ14 DACK0/ DRQ0 DACK5/ DRQ5 DACK6/ DRQ6 DACK7/ DRQ7 +5V , IRQ15 VSS 82 VSS 95 16 IRQ14 1 10 19 17 2 15 4 13 6 11 8 20 3 18 5 16 7 14 9
Cybernetic Micro Systems
Original
P-51 EISA/PC-104 74HCT244 HLMP-6600 1N4002 CS-5201-373 12MAY2000

IT8871

Abstract: 6J5P DACK1#/CSD2# DRQ1/IRQ14 IOCHRDY AEN/IRQ15/P80LA TC/CSD3# IOW# IOR# IRQ0 CSA0# SD7 SD6 SD5 , 82 81 VCC5 CKO0/BALE/GPB0 DACK1#/CSD2# DRQ1/IRQ14 IOCHRDY AEN/IRQ15/P80LA TC/CSD3# IOW , CKO0/BALE/GPB0 6 DACK1#/CSD2# 3,5,6 DRQ1/IRQ14 3,5,6 IOCHRDY 3,5,6 AEN/IRQ15/P80LA 3,5,6 TC/CSD3 , SA5 SA4 SA3 SA2 SA1 SA0 +5V 1 2 3 DACK1#/CSD2# 2,5,6 SD[0.7] 2,5,6 AEN/IRQ15/P80LA , [0.19] 2,3,6 AEN/IRQ15/P80LA 2,3,6 IOCHRDY 2,3,6 RSTDRV 2,3,6 IOW# 2,3,6 IOR# 2,3,6 TC/CSD3
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Original
IT8871 6J5P IT887 uai 92 GP 23 AE 12V JS B55 IT-887 IT-88 SA19/IRQ4/GPC4 SA18/CSB0 SA17/IRQ5/GPC2

OZ 9998 GN

Abstract: 12U7 equivalent to ISA IRQ15 if HEADER is " Not connected" or Logic High. However, this pin will go to TRI-STATE , #, CH1_CS3# CHO-INT CH1_INT 0 0 0 1 ENABLE HEADER IRQ14 1 1 O/TRI-STATE IRQ15 , CH0_INT is not masked by the bitO of register 43h. Otherwise, it is at TRI-STATE. IRQ14: Off IRQ15: same , TRI-STATE. IRQ15: TRI-STATE IRQ14: TRI-STATE IRQ15: TRI-STATE INTA#: Inversion of ORed value of CH0_INT and
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OCR Scan
OZ 9998 GN 12U7 494F IRQ14/15 272-9S59 SS-11 SS8-9998

CON AT62B

Abstract: computer schematics 80386 connected directly to the corresponding ISA Bus interrupt signals. The IRQ12 and IRQ15 Signals have a , 1Eh) Bit 7 (IRQ15 Is RI Out) is set, the IRQ15 Pin functions instead as a debounced -RI ring indicate , Out to IRQ15, the corresponding socket's Interrupt and General Register Control Register (Index 3h) Bit 7 (Ring Indicate Enable) must be set to `1'. In a '386SL-based system, IRQ15 can then be connected to the '360SL -RI input. In the PD6722, if either cards' -RI input is active, IRQ15 will go low
Intel
Original
CON AT62B computer schematics 80386 ISA bus controller for 80386 U1LM317T ISA bus controller for 80286 386sl PD6710/6722 SI9953DY CL-PD6710

80386SL

Abstract: signal and is passed through to the IRQ15(multi pin, set Mise Control 2 bit 7 to one is used as RI_OUT#). , lEh ) Bit D7 Function IRQ 15 is RI Out. This bit determines the function of the IRQ15. When configured for ring indicate, IRQ15 is used to resume the 386SL when a high to low change is detected on the STSCHG#. 0: Normal IRQ15 operation. 1: IRQ15 is connected to Ring Indicate on the processor. R/W. 0 , VIA Technologies, Inc. VT83C465 191 TO 12ma NOWS# PWGOOD IRQ14,11-9,7,5-3 IRQ15 IRQ12
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OCR Scan
80386SL 82365SL CL-PD6720 IOIS16 208-P

CL-PD6729

Abstract: IRQ10 -IRQ11 -IRQ12 -IRQ14 -IRQ15 PCI bus Pins programmed as INT#-type interrupts can be connected , Pins The CL-PD6729 has two dual-function interrupt pins: IRQ14/EXT_CLK and IRQ15/RI_OUT*. In their default modes, these pins indicate interrupt requests IRQ14and IRQ15. IRQ14/EXT_CLK can alternately be , drives the CL-PD6729 circuitry whenever the PCI bus is inactive. Similarly, IRQ15/RLOUT* can alternately , from a PCM CIA I/O card's -STSCHG pin1 are passed through to the IRQ15/RI_OUT* pin of the CL-PD6729. 1
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OCR Scan
82365SL-

intel 80386SL

Abstract: Jedia 4.0 signal and is passed through to the IRQ15(multi pin, set Misc Control 2 bit 7 to one is used as RI_OUT , enable Reserved IRQ14 enable IRQ15 enable Card Status Change Register ( Read Only ) Address , IRQ11 enable IRQ12 enable Reserved IRQ14 enable IRQ15 enable Card Status Change Interrupt on INTR , IRQ15 is RI Out. This bit determines the function of the IRQ15. When configured for ring indicate, IRQ15 is used to resume the 386SL when a high to low change is detected on the STSCHG#. 0: Normal
VIA Technologies
Original
intel 80386SL Jedia 4.0 BPd-15 16bit pcmcia 82365SL PCMCIA VIA Technologies 85TYP 60MAX

XC95144XL-TQ100

Abstract: sd3 32m DACK5X DRQ1 DRQ5 IRQ15 FLASHCSX[3.0] FLASHCSX[3.0] GPIO0 CLK8MHZ CLK14MHZ PRSTX , SMEMWX IOCHRDY BALE IRQ[3.5] IRQ[9.12] IRQ7 IOCHCHKX DACK1X DACK5X DRQ1 DRQ5 IRQ15 FLASHCSX , GND P05 ISA CONNS, FLASH, BOOTSTRAP GND P06 IRQ15 IDEAR0 IDEAR1 IDEAR2 IDECSR0X IDECSR1X IDEPDACKRX IDEPIOWRX IDEPIORRX IDEPIORDY IDEPDREQ IDERSTRX IRQ14 IDEDR[15.0] IRQ15 , RESETX GPCSX[3.0] GPIO[7.0] GPCSX[3.0] GPIO[7.0] IRQ15 IDEAR0 IDEAR1 IDEAR2 IDECSR0X
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XC95144XL-TQ100 sd3 32m SMD SOT23 A53 b60 c300 b30 c250 b30 c300 - 1 VCC12V VDD-12V MCS16X IOCS16X

4556 AD 8 PIN

Abstract: PCI0646 Disk Interrupt is an input to the PCI0646 used to generate the IRQ15 output when the secondary IDE , tri-stated when IDE port 0 is in Native Mode. Signal Pin Type IRQ15 83 T/O Function IRQ15 is used to request an interrupt for secondary IDE port in PCI IDE Legacy Mode. (PC-AT compatible.) IRQ15 is tri-stated when IDE port 1 is in Native Mode. Signal Pin Type PAR 96 B/T , ) or IRQ15 (secondary). When an IDE port is in PCI IDE Native Mode, the IDE task file registers may be
CMD Technology
Original
4556 AD 8 PIN cmd technology 4556 ad EMM386 MAN-000646-000
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