IRLI530N IRL530N - Datasheet Archive

 

PD -9.1350 IRLI530N HEXFET® Power MOSFET l l l l l l Logic-Level Gate Drive Advanced Process Technology Isolated Package High

 

PRELIMINARY PD -9.1350 IRLI530N IRLI530N HEXFET® Power MOSFET l l l l l l Logic-Level Gate Drive Advanced Process Technology Isolated Package High Voltage Isolation = 2.5KVRMS Sink to Lead Creepage Dist. = 4.8mm Fully Avalanche Rated D VDSS = 100V RDS(on) = 0.10 G ID = 11A S Description Fifth Generation HEXFETs from International Rectifier utilize advanced processing techniques to achieve the lowest possible on-resistance per silicon area. This benefit, combined with the fast switching speed and ruggedized device design that HEXFET Power MOSFETs are well known for, provides the designer with an extremely efficient device for use in a wide variety of applications. The TO-220 Fullpak eliminates the need for additional insulating hardware in commercial-industrial applications. The moulding compound used provides a high isolation capability and a low thermal resistance between the tab and external heatsink. This isolation is equivalent to using a 100 micron mica barrier with standard TO-220 product. The Fullpak is mounted to a heatsink using a single clip or by a single screw fixing. TO-220 FULLPAK Absolute Maximum Ratings Parameter ID @ TC = 25°C ID @ TC = 100°C IDM PD @TC = 25°C VGS EAS IAR EAR dv/dt TJ T STG Max. Continuous Drain Current, VGS @ 10V Continuous Drain Current, VGS @ 10V Pulsed Drain Current Power Dissipation Linear Derating Factor Gate-to-Source Voltage Single Pulse Avalanche Energy Avalanche Current Repetitive Avalanche Current Peak Diode Recovery dv/dt Operating Junction and Storage Temperature Range Soldering Temperature, for 10 seconds Mounting torque, 6-32 or M3 screw. 11 7.8 60 33 0.22 ±20 150 9.0 6.3 7.2 -55 to + 175 Units A W W/°C V mJ A mJ V/ns °C 300 (1.6mm from case) 10 lbf·in (1.1N·m) Thermal Resistance Parameter RJC RJA Junction-to-Case Junction-to-Ambient Min. Typ. Max. Units ­­­­ ­­­­ ­­­­ ­­­­ 4.5 65 °C/W IRLI530N IRLI530N Electrical Characteristics @ TJ = 25°C (unless otherwise specified) V(BR)DSS/TJ Parameter Drain-to-Source Breakdown Voltage Breakdown Voltage Temp. Coefficient Qg Qgs Qgd td(on) tr td(off) tf Gate-to-Source Forward Leakage Gate-to-Source Reverse Leakage Total Gate Charge Gate-to-Source Charge Gate-to-Drain ("Miller") Charge Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Min. 100 ­­­ ­­­ ­­­ ­­­ 1.0 7.7 ­­­ ­­­ ­­­ ­­­ ­­­ ­­­ ­­­ ­­­ ­­­ ­­­ ­­­ RDS(on) Static Drain-to-Source On-Resistance VGS(th) gfs Gate Threshold Voltage Forward Transconductance IDSS Drain-to-Source Leakage Current LD Internal Drain Inductance ­­­ LS Internal Source Inductance ­­­ Ciss Coss Crss C Input Capacitance Output Capacitance Reverse Transfer Capacitance Drain to Sink Capacitance ­­­ ­­­ ­­­ ­­­ V(BR)DSS IGSS Typ. ­­­ 0.122 ­­­ ­­­ ­­­ ­­­ ­­­ ­­­ ­­­ ­­­ ­­­ ­­­ ­­­ ­­­ 7.2 53 30 26 Max. Units Conditions ­­­ V VGS = 0V, ID = 250µA ­­­ V/°C Reference to 25°C, ID = 1mA 0.100 VGS = 10V, ID = 9.0A 0.120 VGS = 5.0V, ID = 9.0A 0.150 VGS = 4.0V, ID = 8.0A 2.0 V VDS = VGS, ID = 250µA ­­­ S VDS = 50V, ID = 9.0A 25 VDS = 100V, VGS = 0V µA 250 VDS = 80V, VGS = 0V, T J = 150°C 100 VGS = 20V nA -100 VGS = -20V 34 ID = 9.0A 4.8 nC VDS = 80V 20 VGS = 5.0V, See Fig. 6 and 13 ­­­ VDD = 50V ­­­ ID = 9.0A ns ­­­ RG = 6.0, VGS = 5.0V ­­­ RD = 5.5, See Fig. 10 Between lead, 4.5 ­­­ 6mm (0.25in.) nH from package 7.5 ­­­ and center of die contact 800 ­­­ VGS = 0V 160 ­­­ pF VDS = 25V 90 ­­­ = 1.0MHz, See Fig. 5 12 ­­­ = 1.0MHz D G S Source-Drain Ratings and Characteristics IS ISM VSD t rr Q rr Parameter Continuous Source Current (Body Diode) Pulsed Source Current (Body Diode) Diode Forward Voltage Reverse Recovery Time Reverse RecoveryCharge Min. Typ. Max. Units ­­­ ­­­ 11 A ­­­ ­­­ 60 ­­­ ­­­ ­­­ ­­­ 1.3 140 210 740 1100 V ns nC Conditions MOSFET symbol showing the integral reverse p-n junction diode. TJ = 25°C, IS = 6.6A, VGS = 0V TJ = 25°C, IF = 9.0A di/dt = 100A/µs Notes: Repetitive rating; pulse width limited by Pulse width 300µs; duty cycle 2%. max. junction temperature. ( See fig. 11 ) VDD = 25V, starting TJ = 25°C, L = 3.1mH t=60s, =60Hz RG = 25, IAS = 9.0A. (See Figure 12) ISD 9.0A, di/dt 540A/µs, VDD V(BR)DSS , TJ 175°C Uses IRL530N IRL530N data and test conditions D G S IRLI530N IRLI530N 100 100 VGS 15V 12V 10V 8.0V 6.0V 4.0V 3.0V BOTT OM 2.5V ID , D ra in -to -S o u rce C u rre n t (A ) ID , D ra in -to -S o u rce C u rre n t (A ) 10 1 2 .5V 20 µ s PU LSE W ID TH T J = 2 5°C 0.1 0.1 1 10 10 2 .5 V 1 0.1 100 3.0 R D S (o n ) , D ra in -to -S o u rc e O n R e si sta n ce (N o rm a li ze d ) I D , D r ain- to-S ourc e C urre nt (A ) T J = 2 5 °C T J = 17 5° C 10 1 V DS = 5 0 V 2 0µ s PU L SE W ID TH 4 5 6 7 8 9 10 A 100 Fig 2. Typical Output Characteristics, TJ = 175oC 100 3 1 V D S , Drain-to-Source V oltage (V ) Fig 1. Typical Output Characteristics, T J = 25oC 0.1 20 µ s PU LSE W ID TH T J = 1 75°C 0.1 A V D S , Drain-to-Source V oltage (V ) 2 VGS 15V 12V 10V 8.0V 6.0V 4.0V 3.0V BOTT OM 2.5V TOP TOP 10 V G S , G ate-to -S ource V olta ge (V ) Fig 3. Typical Transfer Characteristics A I D = 15 A 2.5 2.0 1.5 1.0 0.5 V G S = 10 V 0.0 -60 -40 -20 0 20 40 60 80 A 100 120 140 160 180 T J , Junction T emperature (°C) Fig 4. Normalized On-Resistance Vs. Temperature IRLI530N IRLI530N V GS C iss C rs s C os s C , C a p a c ita n c e (p F ) 1200 = = = = 15 0V , f = 1 MH z C gs + C gd , C ds SH O R TED C gd C ds + C gd V G S , G a te -to -S o u rce V o lta g e (V ) 1400 800 600 C os s 400 C rss 200 0 10 9 6 3 FO R TES T C IR CU IT SEE FIG U R E 13 0 A 1 V D S = 80 V V D S = 50 V V D S = 20 V 12 C is s 1000 I D = 9 .0 A 0 100 10 V D S , D rain-to-S ource Voltage (V ) 30 40 A 50 Q G , Total Gate Charge (nC ) Fig 5. Typical Capacitance Vs. Drain-to-Source Voltage Fig 6. Typical Gate Charge Vs. Gate-to-Source Voltage 100 1000 O PER ATIO N IN TH IS AR EA L IM ITED BY R DS (on) I D , D ra in C u rre n t (A ) I S D , R e v e rse D ra in C u rre n t (A ) 20 T J = 1 75°C 10 T J = 25 °C VG S = 0 V 1 0.4 0.6 0.8 1.0 1.2 V S D , S ource-to-Drain Voltage (V ) Fig 7. Typical Source-Drain Diode Forward Voltage A 1.4 100 10µ s 10 10 0µs 1m s T C = 25 °C T J = 17 5°C S ing le Pulse 1 1 1 0m s 10 100 A 1000 V D S , Drain-to-Source Voltage (V) Fig 8. Maximum Safe Operating Area IRLI530N IRLI530N RD VDS 12 VGS I D , D ra in C u rre n t (A m p s) D.U.T. RG 10 + -VDD 5.0V 8 Pulse Width 1 µs Duty Factor 0.1 % 6 Fig 10a. Switching Time Test Circuit 4 VDS 90% 2 A 0 25 50 75 100 125 150 175 10% VGS TC , Case Temperature (°C ) td(on) Fig 9. Maximum Drain Current Vs. Case Temperature tr t d(off) tf Fig 10b. Switching Time Waveforms Therm al R esp onse (Z thJC ) 10 D = 0.50 1 0 .2 0 0 .1 0 0 .0 5 PD M 0 .0 2 0.1 0 .0 1 t S ING LE P U LS E ( TH E R M A L R E S P O N S E ) t2 N o te s : 1 . D u ty fa c to r D = t 0.01 0.00001 1 1 / t 2 2. P e a k T J = P DM x Z t h J C + T C 0.0001 0.001 0.01 0.1 1 t 1 , Rectan gular Pulse Duration (sec) Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case A 10 IRLI530N IRLI530N L VDS D.U.T. RG + - VDD IAS 5.0 V tp 0.01 Fig 12a. Unclamped Inductive Test Circuit V(BR)DSS tp VDD E A S , S in g le P u ls e A va la n c h e E n e rg y (m J) 350 TO P 300 B OT TO M ID 3.7A 6.4 A 9.0 A 250 200 150 100 50 VD D = 2 5V 0 25 50 A 75 100 125 150 Starting T J , Junction Temperature (°C) VDS Fig 12c. Maximum Avalanche Energy Vs. Drain Current IAS Fig 12b. Unclamped Inductive Waveforms Current Regulator Same Type as D.U.T. 50K 12V .2µF QG .3µF 5.0 V QGS D.U.T. QGD + V - DS VGS VG 3mA IG Charge Fig 13a. Basic Gate Charge Waveform ID Current Sampling Resistors Fig 13b. Gate Charge Test Circuit 175 IRLI530N IRLI530N Peak Diode Recovery dv/dt Test Circuit + D.U.T Circuit Layout Considerations · Low Stray Inductance · Ground Plane · Low Leakage Inductance Current Transformer + - - + · · · · RG Driver Gate Drive P.W. + dv/dt controlled by RG Driver same type as D.U.T. ISD controlled by Duty Factor "D" D.U.T. - Device Under Test Period D= - VDD P.W. Period VGS=10V D.U.T. ISD Waveform Reverse Recovery Current Body Diode Forward Current di/dt D.U.T. VDS Waveform Diode Recovery dv/dt Re-Applied Voltage Body Diode VDD Forward Drop Inductor Curent Ripple 5% * VGS = 5V for Logic Level Devices Fig 14. For N-Channel HEXFETS ISD * IRLI530N IRLI530N Package Outline - TO-220 FullPak Dimensions are shown in millimeters (inches) 10.60 (.41 7) 10.40 (.40 9) ø 3.40 (.133 ) 3.10 (.123 ) 4.8 0 (.189) 4.6 0 (.181) -A 3.70 (.145) 3.20 (.126) 16 .0 0 (.630) 15 .8 0 (.622) 2 .80 (.110) 2 .60 (.102) LE AD A S SIGN M E N T S 1 - GA TE 2 - D R AIN 3 - SO U R C E 7 .10 (.280) 6 .70 (.263) 1.15 (.04 5) M IN . N O T ES : 1 D IM EN SION IN G & T O LER A N C IN G PE R AN S I Y14.5 M , 1982 1 2 3 2 C O N TR OLLIN G D IM EN S ION : IN C H . 3.30 (.130 ) 3.10 (.122 ) -B- 13 .7 0 (.540) 13 .5 0 (.530) C A 1.40 (.05 5) 3X 1.05 (.04 2) 0.9 0 (.035) 3X 0.7 0 (.028) 0.25 (.010 ) 3X M A M B 2 .54 (.100) 2X 0.48 (.019) 0.44 (.017) 2.85 (.112 ) 2.65 (.104 ) D B M IN IM U M C R E EP AG E D IST A NC E B ET W E EN A-B -C -D = 4.80 (.189 ) Part Marking E X A M P L E : T H IS IS A N I R F I8 4 0 G W ITH A S S E M B L Y LO T CO DE E4 01 A IN T E R N A TI O N A L R E C T IF IE R LOGO PA RT NU MB E R IR F I8 4 0 G E40 1 92 45 AS S EM BL Y LOT COD E DATE C ODE (Y Y W W ) YY = Y E AR W W = W EE K WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, Tel: (310) 322 3331 EUROPEAN HEADQUARTERS: Hurst Green, Oxted, Surrey RH8 9BB, UK Tel: + 44 1883 732020 IR CANADA: 7321 Victoria Park Ave., Suite 201, Markham, Ontario L3R 2Z8, Tel: (905) 475 1897 IR GERMANY: Saalburgstrasse 157, 61350 Bad Homburg Tel: + 49 6172 96590 IR ITALY: Via Liguria 49, 10071 Borgaro, Torino Tel: + 39 11 451 0111 IR FAR EAST: K&H Bldg., 2F, 3-30-4 Nishi-Ikeburo 3-Chome, Toshima-Ki, Tokyo Japan 171 Tel: 81 3 3983 0086 IR SOUTHEAST ASIA: 315 Outram Road, #10-02 Tan Boon Liat Building, Singapore 0316 Tel: 65 221 8371 http://www.irf.com/ Data and specifications subject to change without notice. 7/96