91348C IRL530N NIRF1010 EEK19 - Datasheet Archive

 

IRL530N l l l l l l Logic-Level Gate Drive Advanced Process Technology Dynamic dv/dt Rating 175°C Operating Temperature Fast

 

PD - 91348C 91348C IRL530N IRL530N l l l l l l Logic-Level Gate Drive Advanced Process Technology Dynamic dv/dt Rating 175°C Operating Temperature Fast Switching Fully Avalanche Rated HEXFET® Power MOSFET D VDSS = 100V RDS(on) = 0.10 G ID = 17A S Description Fifth Generation HEXFETs from International Rectifier utilize advanced processing techniques to achieve extremely low on-resistance per silicon area. This benefit, combined with the fast switching speed and ruggedized device design that HEXFET Power MOSFETs are well known for, provides the designer with an extremely efficient and reliable device for use in a wide variety of applications. The TO-220 package is universally preferred for all commercial-industrial applications at power dissipation levels to approximately 50 watts. The low thermal resistance and low package cost of the TO-220 contribute to its wide acceptance throughout the industry. TO-220AB Absolute Maximum Ratings Parameter ID @ TC = 25°C ID @ TC = 100°C IDM PD @T C = 25°C VGS EAS IAR EAR dv/dt TJ TSTG Max. Continuous Drain Current, VGS @ 10V Continuous Drain Current, VGS @ 10V Pulsed Drain Current Power Dissipation Linear Derating Factor Gate-to-Source Voltage Single Pulse Avalanche Energy Avalanche Current Repetitive Avalanche Energy Peak Diode Recovery dv/dt Operating Junction and Storage Temperature Range Soldering Temperature, for 10 seconds Mounting torque, 6-32 or M3 srew 17 12 60 79 0.53 ± 16 150 9.0 7.9 5.0 -55 to + 175 Units A W W/°C V mJ A mJ V/ns °C 300 (1.6mm from case ) 10 lbf·in (1.1N·m) Thermal Resistance Parameter RJC RCS RJA Junction-to-Case Case-to-Sink, Flat, Greased Surface Junction-to-Ambient Typ. Max. Units ­­­ 0.50 ­­­ 1.9 ­­­ 62 °C/W 1/09/04 IRL530N IRL530N Electrical Characteristics @ TJ = 25°C (unless otherwise specified) V(BR)DSS/TJ Parameter Drain-to-Source Breakdown Voltage Breakdown Voltage Temp. Coefficient RDS(on) Static Drain-to-Source On-Resistance VGS(th) gfs Gate Threshold Voltage Forward Transconductance IDSS Drain-to-Source Leakage Current V(BR)DSS Qg Qgs Qgd td(on) tr td(off) tf Gate-to-Source Forward Leakage Gate-to-Source Reverse Leakage Total Gate Charge Gate-to-Source Charge Gate-to-Drain ("Miller") Charge Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time LD Internal Drain Inductance LS Internal Source Inductance Ciss Coss Crss Input Capacitance Output Capacitance Reverse Transfer Capacitance IGSS Min. 100 ­­­ ­­­ ­­­ ­­­ 1.0 7.7 ­­­ ­­­ ­­­ ­­­ ­­­ ­­­ ­­­ ­­­ ­­­ ­­­ ­­­ Typ. Max. Units Conditions ­­­ ­­­ V V GS = 0V, ID = 250µA 0.122 ­­­ V/°C Reference to 25°C, ID = 1mA ­­­ 0.100 VGS = 10V, ID = 9.0A ­­­ 0.120 VGS = 5.0V, ID = 9.0A ­­­ 0.150 VGS = 4.0V, ID = 8.0A ­­­ 2.0 V VDS = VGS, ID = 250µA ­­­ ­­­ S V DS = 25V, ID = 9.0A ­­­ 25 VDS = 100V, VGS = 0V µA ­­­ 250 VDS = 80V, VGS = 0V, TJ = 150°C ­­­ 100 VGS = 16V nA ­­­ -100 VGS = -16V ­­­ 34 ID = 9.0A ­­­ 4.8 nC VDS = 80V ­­­ 20 VGS = 5.0V, See Fig. 6 and 13 7.2 ­­­ VDD = 50V 53 ­­­ ID = 9.0A ns 30 ­­­ RG = 6.0, VGS = 5.0V 26 ­­­ RD = 5.5, See Fig. 10 Between lead, ­­­ 4.5 ­­­ nH 6mm (0.25in.) G from package ­­­ 7.5 ­­­ and center of die contact ­­­ 800 ­­­ VGS = 0V ­­­ 160 ­­­ pF VDS = 25V ­­­ 90 ­­­ = 1.0MHz, See Fig. 5 Source-Drain Ratings and Characteristics IS ISM VSD trr Qrr ton Parameter Continuous Source Current (Body Diode) Pulsed Source Current (Body Diode) Diode Forward Voltage Reverse Recovery Time Reverse RecoveryCharge Forward Turn-On Time Min. Typ. Max. Units Conditions D MOSFET symbol 17 ­­­ ­­­ showing the A G integral reverse ­­­ ­­­ 60 p-n junction diode. S ­­­ ­­­ 1.3 V TJ = 25°C, IS = 9.0A, VGS = 0V ­­­ 140 210 ns TJ = 25°C, I F = 9.0A ­­­ 740 1100 nC di/dt = 100A/µs Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD) Notes: Repetitive rating; pulse width limited by max. junction temperature. ( See fig. 11 ) Starting TJ = 25°C, L = 3.7mH RG = 25, IAS = 9.0A. (See Figure 12) . ISD 9.0A, di/dt 540A/µs, VDD V(BR)DSS, TJ 175°C Pulse width 300µs; duty cycle 2% D S IRL530N IRL530N 100 100 VGS 15V 12V 10V 8.0V 6.0V 4.0V 3.0V BOTTOM 2.5V 10 1 2 .5V 2 0µ s P U LS E W ID TH T J = 2 5°C 0.1 0.1 VGS 15V 12V 10V 8.0V 6.0V 4.0V 3.0V BOTTOM 2.5V TOP ID , Drain-to-Source Current (A ) ID , Drain-to-Source Current (A ) TOP 1 10 10 2.5 V 1 2 0µ s P U LS E W ID TH T J = 1 75 °C 0.1 A 100 0.1 V D S , D rain-to-S ource V oltage (V ) 3.0 R D S (on) , D ra in-to -S o urc e O n R e s is ta nc e (N o rm alize d) I D , D ra in -to-S ourc e C urrent (A) T J = 2 5 °C T J = 1 7 5°C 10 1 V DS = 5 0V 2 0µ s P U L S E W ID TH 3 4 5 6 7 8 9 V G S , G ate-to -So urce Voltag e (V) Fig 3. Typical Transfer Characteristics A 100 Fig 2. Typical Output Characteristics 100 2 10 V D S , D rain-to-S ource V oltage (V ) Fig 1. Typical Output Characteristics 0.1 1 10 A I D = 15 A 2.5 2.0 1.5 1.0 0.5 V G S = 1 0V 0.0 -60 -40 -20 0 20 40 60 80 A 100 120 140 160 180 T J , J unc tion T em perature (°C ) Fig 4. Normalized On-Resistance Vs. Temperature IRL530N IRL530N V GS C iss C rs s C o ss C , Capacitance (pF) 1200 = = = = 15 0V , f = 1MHz C g s + C g d , C d s S H O R TE D C gd C ds + C g d V G S , G ate-to-S ource V oltage (V ) 1400 800 600 C oss 400 C rss 200 0 10 9 6 3 FO R TE S T C IR C U IT S E E FIG U R E 1 3 0 A 1 V D S = 8 0V V D S = 5 0V V D S = 2 0V 12 C iss 1000 I D = 9.0 A 100 0 V D S , D rain-to-S ourc e V oltage (V ) 20 30 40 A 50 Q G , T otal G ate C harge (nC ) Fig 5. Typical Capacitance Vs. Drain-to-Source Voltage Fig 6. Typical Gate Charge Vs. Gate-to-Source Voltage 1000 100 O P E R A TIO N IN TH IS A R E A LIM ITE D B Y R D S (o n ) I D , Drain C urrent (A ) I S D , R everse Drain C urrent (A ) 10 T J = 17 5°C 10 T J = 2 5°C V G S = 0V 1 0.4 0.6 0.8 1.0 1.2 V S D , S ourc e-to-D rain V oltage (V ) Fig 7. Typical Source-Drain Diode Forward Voltage A 1.4 100 10µ s 10 10 0µs 1m s T C = 25 °C T J = 17 5°C S ing le P u lse 1 1 10m s 10 100 V D S , D rain-to-S ource V oltage (V ) Fig 8. Maximum Safe Operating Area A 1000 IRL530N IRL530N 20 RD VDS VGS I D , Drain Current (A) 15 D.U.T. RG + -VDD 5.0V 10 Pulse Width 1 µs Duty Factor 0.1 % Fig 10a. Switching Time Test Circuit 5 VDS 90% 0 25 50 75 100 125 150 175 TC , Case Temperature ( ° C) Fig 9. Maximum Drain Current Vs. Case Temperature 10% VGS td(on) tr t d(off) tf Fig 10b. Switching Time Waveforms Thermal Response (Z thJC ) 10 1 D = 0.50 0.20 0.10 P DM 0.05 0.1 0.01 0.00001 0.02 0.01 SINGLE PULSE (THERMAL RESPONSE) t1 t2 Notes: 1. Duty factor D = t 1 / t 2 2. Peak T J = P DM x Z thJC + TC 0.0001 0.001 0.01 0.1 t1 , Rectangular Pulse Duration (sec) Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case 1 IRL530N IRL530N D.U.T. RG + V - DD IAS 5.0 V tp 0.01 Fig 12a. Unclamped Inductive Test Circuit V(BR)DSS E A S , S ingle P ulse A valanche E nergy (m J) 350 L VDS TO P 300 B O TTO M 250 200 150 100 50 V D D = 25 V 0 25 50 A 75 100 125 150 S tarting T J , J unc tion T em perature (°C ) tp VDD Fig 12c. Maximum Avalanche Energy Vs. Drain Current VDS IAS Fig 12b. Unclamped Inductive Waveforms Current Regulator Same Type as D.U.T. 50K QG 12V .2µF .3µF 5.0 V QGS ID 3 .7A 6 .4A 9.0 A D.U.T. QGD + V - DS VGS VG 3mA Charge Fig 13a. Basic Gate Charge Waveform IG ID Current Sampling Resistors Fig 13b. Gate Charge Test Circuit 175 IRL530N IRL530N Peak Diode Recovery dv/dt Test Circuit + D.U.T Circuit Layout Considerations · Low Stray Inductance · Ground Plane · Low Leakage Inductance Current Transformer + - - + · · · · RG Driver Gate Drive P.W. + dv/dt controlled by RG Driver same type as D.U.T. ISD controlled by Duty Factor "D" D.U.T. - Device Under Test D= Period - VDD P.W. Period VGS=10V D.U.T. ISD Waveform Reverse Recovery Current Body Diode Forward Current di/dt D.U.T. VDS Waveform Diode Recovery dv/dt Re-Applied Voltage Body Diode VDD Forward Drop Inductor Curent Ripple 5% ISD * VGS = 5V for Logic Level Devices Fig 14. For N-Channel HEXFETS * IRL530N IRL530N TO-220AB Package Outline Dimensions are shown in millimeters (inches) 2.87 (.113) 2.62 (.103) 10.54 (.415) 10.29 (.405) -B- 3.78 (.149) 3.54 (.139) 4.69 (.185) 4.20 (.165) -A- 1.32 (.052) 1.22 (.048) 6.47 (.255) 6.10 (.240) 4 15.24 (.600) 14.84 (.584) LEAD ASSIGNMENTS 1.15 (.045) MIN 1 2 LEAD ASSIGNMENTS HEXFET GATE 1- 14.09 (.555) 13.47 (.530) IGBTs, CoPACK 2 1- GATE- DRAIN 32- DRAINSOURCE 3- SOURCE 4 - DRAIN 4- DRAIN 3 1- GATE 2- COLLECTOR 3- EMITTER 4- COLLECTOR 4.06 (.160) 3.55 (.140) 3X 1.40 (.055) 3X 1.15 (.045) 0.93 (.037) 0.69 (.027) 0.36 (.014) 3X M B A M 2.92 (.115) 2.64 (.104) 2.54 (.100) 2X NOTES: 1 DIMENSIONING & TOLERANCING PER ANSI Y14.5M, 1982. 2 CONTROLLING DIMENSION : INCH 0.55 (.022) 0.46 (.018) 3 OUTLINE CONFORMS TO JEDEC OUTLINE TO-220AB. 4 HEATSINK & LEAD MEASUREMENTS DO NOT INCLUDE BURRS. TO-220AB Part Marking Information @Y6HQG@) UCDTÃDTÃ6IÃDSA Ã GPUÃ8P9@Ã &'( 6TT@H7G@9ÃPIÃXXÃ (Ã (& DIÃUC@Ã6TT@H7G`ÃGDI@ÃÅ8Å Note: "P" in assembly line position indicates "Lead-Free" DIU@SI6UDPI6G S@8UDAD@S GPBP 6TT@H7G` GPUÃ8P9@ Q6SUÃIVH7@S 96U@Ã8P9@ `@6SÃ&Ã2Ã (& X@@FÃ ( GDI@Ã8 For GB Production EX M A PLE: THIS IS A NIRF1010 NIRF1010 LOT C DE 1789 O A SSEM BLEDO W19, 1997 NW INTHE A SSEM BLYLINE "C " INTERNA TIONA L REC TIFIER LO O G A SSEM BLY LO C DE T O PA NUM RT BER DA C DE TE O Y R 7 = 1997 EA W EEK19 EEK19 LINE C TO-220AB package is not recommended for Surface Mount Application. Data and specifications subject to change without notice. IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 Visit us at www.irf.com for sales contact information. 01/04