1338D IRL3103S IRL3103 AN-994 IRF530S - Datasheet Archive

 

IRL3103S PRELIMINARY HEXFET® Power MOSFET l l l l l l Logic-Level Gate Drive Advanced Process Technology Dynamic dv/dt Rating

 

PD -9.1338D 1338D IRL3103S IRL3103S PRELIMINARY HEXFET® Power MOSFET l l l l l l Logic-Level Gate Drive Advanced Process Technology Dynamic dv/dt Rating 175°C Operating Temperature Fast Switching Fully Avalanche Rated D VDSS = 30V RDS(on) = 0.014 G ID = 56A S Description Fifth Generation HEXFETs from International Rectifier utilize advanced processing techniques to achieve the lowest possible on-resistance per silicon area. This benefit, combined with the fast switching speed and ruggedized device design that HEXFET Power MOSFETs are well known for, provides the designer with an extremely efficient device for use in a wide variety of applications. The D2PAK is a surface mount power package capable of accommodating die sizes up to HEX-4. It provides the highest power capability and the lowest possible onresistance in any existing surface mount package. The D2PAK is suitable for high current applications because of its low internal connection resistance and can dissipate up to 2.0W in a typical surface mount application. D 2 Pak Absolute Maximum Ratings Parameter ID @ TC = 25°C ID @ TC = 100°C IDM PD @TC = 25°C VGS EAS IAR EAR dv/dt TJ T STG Max. Continuous Drain Current, VGS @ 10V Continuous Drain Current, VGS @ 10V Pulsed Drain Current Power Dissipation Linear Derating Factor Gate-to-Source Voltage Single Pulse Avalanche Energy Avalanche Current Repetitive Avalanche Energy Peak Diode Recovery dv/dt Operating Junction and Storage Temperature Range Soldering Temperature, for 10 seconds 56 40 220 83 0.56 ±16 240 34 8.3 2.0 -55 to + 175 Units A W W/°C V mJ A mJ V/ns °C 300 (1.6mm from case) Thermal Resistance Parameter RJC RJA Junction-to-Case Junction-to-Ambient (PCB Mount,steady-state)* Min. Typ. Max. Units ­­­­ ­­­­ ­­­­ ­­­­ 1.8 40 °C/W 11/1/96 IRL3103S IRL3103S Electrical Characteristics @ TJ = 25°C (unless otherwise specified) V(BR)DSS/TJ Parameter Drain-to-Source Breakdown Voltage Breakdown Voltage Temp. Coefficient RDS(on) Static Drain-to-Source On-Resistance VGS(th) gfs Gate Threshold Voltage Forward Transconductance IDSS Drain-to-Source Leakage Current V(BR)DSS Qg Qgs Qgd td(on) tr td(off) tf Gate-to-Source Forward Leakage Gate-to-Source Reverse Leakage Total Gate Charge Gate-to-Source Charge Gate-to-Drain ("Miller") Charge Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time LS Internal Source Inductance Ciss Coss Crss Input Capacitance Output Capacitance Reverse Transfer Capacitance I GSS Min. 30 ­­­ ­­­ ­­­ 1.0 23 ­­­ ­­­ ­­­ ­­­ ­­­ ­­­ ­­­ ­­­ ­­­ ­­­ ­­­ Typ. ­­­ 0.037 ­­­ ­­­ ­­­ ­­­ ­­­ ­­­ ­­­ ­­­ ­­­ ­­­ ­­­ 9.0 210 20 54 Max. Units Conditions ­­­ V VGS = 0V, I D = 250µA ­­­ V/°C Reference to 25°C, I D = 1mA 0.014 VGS = 10V, ID = 34A 0.019 VGS = 4.5V, I D = 28A ­­­ V VDS = VGS , ID = 250µA ­­­ S VDS = 25V, I D = 34A 25 VDS = 30V, VGS = 0V µA 250 VDS = 24V, VGS = 0V, TJ = 150°C 100 V GS = 16V nA -100 VGS = -16V 50 ID = 34A 14 nC VDS = 24V 28 V GS = 4.5V, See Fig. 6 and 13 ­­­ VDD = 15V ­­­ I D = 34A ns ­­­ RG = 3.4, VGS = 4.5V ­­­ RD = 0.43, See Fig. 10 Between lead, nH ­­­ 7.5 ­­­ and center of die contact ­­­ 1600 ­­­ VGS = 0V ­­­ 640 ­­­ pF VDS = 25V ­­­ 320 ­­­ = 1.0MHz, See Fig. 5 Source-Drain Ratings and Characteristics Parameter Continuous Source Current (Body Diode) Pulsed Source Current (Body Diode) Diode Forward Voltage Reverse Recovery Time Reverse RecoveryCharge Forward Turn-On Time IS ISM VSD t rr Q rr t on Min. Typ. Max. Units Conditions MOSFET symbol ­­­ ­­­ 56 showing the A G integral reverse ­­­ ­­­ 220 p-n junction diode. ­­­ ­­­ 1.3 V TJ = 25°C, IS = 34A, VGS = 0V ­­­ 81 120 ns TJ = 25°C, IF = 34A ­­­ 210 310 nC di/dt = 100A/µs Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD) D S Specification changes Rev. # 1 1 Parameters Old spec. VGS(th) (Max.) VGS (Max.) New spec. 2.0V ±20 No spec. ±16 Comments Removed V GS(th) Max. Specification Decrease VGS Max. Specification Notes: Repetitive rating; pulse width limited by max. junction temperature. ( See fig. 11 ) VDD = 15V, starting TJ = 25°C, L = 300µH RG = 25, IAS = 34A. (See Figure 12) I SD 34A, di/dt 140A/µs, VDD V(BR)DSS , TJ 175°C Pulse width 300µs; duty cycle 2%. Uses IRL3103 IRL3103 data and test conditions. * When mounted on 1" square PCB ( FR-4 or G-10 Material ). For recommended footprint and soldering techniques refer to application note #AN-994 AN-994. Revision Date 5/2/96 5/2/96 IRL3103S IRL3103S 1000 1000 VGS 15V 12V 10V 8.0V 6.0V 4.0V 3.0V BOTTOM 2.5V VGS 15V 12V 10V 8.0V 6.0V 4.0V 3.0V BOTT OM 2.5V TOP ID , D ra in -to -S o u rc e C u rre n t (A ) ID , D ra in -to -S o u rce C u rre n t (A ) TOP 100 10 100 10 2.5 V 2 .5V 2 0µ s PU L SE W ID TH T J = 2 5°C 1 0.1 1 10 20 µ s PU LSE W ID TH T J = 1 75°C 1 A 0.1 100 2.0 R D S (o n ) , D ra in -to -S o u rc e O n R e si sta n ce (N o rm a li ze d ) I D , D r ain- to-S ourc e C urre nt (A ) 1000 T J = 2 5 °C 100 TJ = 1 7 5 ° C 10 V DS = 1 5 V 2 0 µ s P U L S E W ID T H 3.0 4.0 5.0 6.0 7.0 8.0 A 100 Fig 2. Typical Output Characteristics Fig 1. Typical Output Characteristics 2.0 10 V D S , Drain-to-Source V oltage (V ) V D S , Drain-to-S ource Voltage (V ) 1 1 9.0 V G S , Ga te-to-S o urce V oltage (V ) Fig 3. Typical Transfer Characteristics A I D = 56 A 1.5 1.0 0.5 V G S = 10 V 0.0 -60 -40 -20 0 20 40 60 80 A 100 120 140 160 180 T J , Junction T emperature (°C) Fig 4. Normalized On-Resistance Vs. Temperature IRL3103S IRL3103S 15 C , C a p a c ita n c e (p F ) 2800 C iss 2400 V GS C is s C rs s C os s = = = = 0V , f = 1MH z C gs + C g d , Cds SH OR TED Cgd C ds + C gd V G S , G a te -to -S o u rce V o lta g e (V ) 3200 C os s 2000 1600 1200 C rs s 800 I D = 34A V DS = 2 4V V DS = 1 5V 12 9 6 3 400 0 0 A 1 10 FO R TEST CIR CU IT SEE FIG UR E 13 0 100 20 30 40 50 60 A 70 Q G , T otal Gate C harge (nC ) V D S , Drain-to-Source V oltage (V) Fig 6. Typical Gate Charge Vs. Gate-to-Source Voltage Fig 5. Typical Capacitance Vs. Drain-to-Source Voltage 1000 1000 OPE R ATIO N IN TH IS A RE A LIMITE D BY R D S(o n) I D , D ra in C u rre n t (A ) I S D , R e v e rse D ra in C u rre n t (A ) 10 100 T J = 17 5°C T J = 2 5°C VG S = 0 V 0.8 1.2 1.6 1 00µs 1 ms 10 1 0m s 10 0.4 10 µs 100 2.0 2.4 V S D , S ource-to-Drain Voltage (V ) Fig 7. Typical Source-Drain Diode Forward Voltage A 2.8 T C = 25 °C T J = 17 5°C S ing le Pulse 1 1 A 10 V D S , Drain-to-Source Voltage (V) Fig 8. Maximum Safe Operating Area 100 IRL3103S IRL3103S 60 RD VDS VGS ID , D ra in C u rre n t (A m p s ) 50 D.U.T. RG + -VDD 40 4.5V 30 Pulse Width 1 µs Duty Factor 0.1 % 20 Fig 10a. Switching Time Test Circuit VDS 10 90% A 0 25 50 75 100 125 150 175 TC , Case Temperature (°C ) 10% VGS Fig 9. Maximum Drain Current Vs. Case Temperature td(on) tr t d(off) tf Fig 10b. Switching Time Waveforms Th erm al R esp on se (Z th JC ) 10 1 D = 0.5 0 0.20 0.10 0.1 PD M 0 .0 5 t 0.02 0.01 S IN G LE P U L S E (T HE RM A L RE S P O N S E ) 0.01 0.00001 N o te s : 1 . D u ty fa c to r D = t 1 / t 1 t2 2 2 . P e a k TJ = P D M x Z th J C + T C 0.0001 0.001 0.01 0.1 t 1 , Rectan gular Pulse Duration (sec) Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case A 1 IRL3103S IRL3103S D.U.T. RG + V - DD IAS 4.5 V tp 0.01 Fig 12a. Unclamped Inductive Test Circuit V(BR)DSS E A S , S in g le P u ls e A va la n c h e E n e rg y (m J) 600 L VDS TO P 500 BO TTO M 400 300 200 100 VD D = 1 5V 0 25 A 50 75 100 125 150 Starting T J , Junction Temperature (°C) tp VDD Fig 12c. Maximum Avalanche Energy Vs. Drain Current VDS IAS Fig 12b. Unclamped Inductive Waveforms Current Regulator Same Type as D.U.T. 50K QG 12V .2µF .3µF 4.5 V QGS ID 1 4A 24 A 34 A D.U.T. QGD + V - DS VGS VG 3mA Charge Fig 13a. Basic Gate Charge Waveform IG ID Current Sampling Resistors Fig 13b. Gate Charge Test Circuit 175 IRL3103S IRL3103S Peak Diode Recovery dv/dt Test Circuit + D.U.T Circuit Layout Considerations · Low Stray Inductance · Ground Plane · Low Leakage Inductance Current Transformer + - - + · · · · RG Driver Gate Drive Period P.W. + dv/dt controlled by RG Driver same type as D.U.T. ISD controlled by Duty Factor "D" D.U.T. - Device Under Test D= - VDD P.W. Period VGS=10V D.U.T. ISD Waveform Reverse Recovery Current Body Diode Forward Current di/dt D.U.T. VDS Waveform Diode Recovery dv/dt Re-Applied Voltage Body Diode VDD Forward Drop Inductor Curent Ripple 5% * VGS = 5V for Logic Level Devices Fig 14. For N-Channel HEXFETS ISD * IRL3103S IRL3103S D2Pak Package Details 10.54 (.415) 10.29 (.405) 1.40 (.055) MA X. -B - 4.69 (.185) 4.20 (.165) -A- 1.32 (.052) 1.22 (.048) 2 1.78 (.070) 1.27 (.050) 1 10.16 (.400) R EF . 6.47 (.255) 6.18 (.243) 3 15.49 (.610) 14.73 (.580) 2.79 (.110) 2.29 (.090) 2.61 (.103) 2.32 (.091) 5.28 (.208) 4.78 (.188) 3X 1.40 (.055) 1.14 (.045) 0.55 (.022) 0.46 (.018) 0.93 (.037) 3X 0.69 (.027) 5.08 (.200) 0.25 (.010) M 8.89 (.350) R EF . 1.39 (.055) 1.14 (.045) M IN IM U M R EC OM M EN D ED F OOT PR IN T B A M 11.43 (.450) LE AD ASSIGN M EN T S 1 - GAT E 2 - D RA IN 3 - SOU R C E N OT ES: 1 D IME NS IO N S AF TE R SO LD ER D IP. 2 D IME NS IO N IN G & T OLER AN C IN G PER AN SI Y14.5M, 1982. 3 C ON T RO LLIN G D IM ENS IO N : IN CH . 4 H EA TSIN K & LEA D D IM E N SIO NS DO NO T INC LU D E BU R R S. 8.89 (.350) 17.78 (.700) 3.81 (.150) TRR 2.08 (.082) 2X 1 .6 0 (. 0 6 3 ) 1 .5 0 (. 0 5 9 ) 4. 1 0 (.1 6 1 ) 3. 9 0 (.1 5 3 ) F E ED D IR E C T IO N 1. 6 0 (. 0 63 ) 1. 5 0 (. 0 59 ) 0 .3 6 8 (.0 1 4 5) 0 .3 4 2 (.0 1 3 5) 1 1. 60 (. 45 7 ) 1 1. 40 (. 44 9 ) 1 .8 5 (. 0 73 ) 1 .6 5 (. 0 65 ) 1 5. 42 (. 60 9 ) 1 5. 22 (. 60 1 ) 24 .3 0 (.9 5 7 ) 23 .9 0 (.9 4 1 ) TRL 1. 7 5 (. 0 69 ) 1. 2 5 (. 0 49 ) 1 0 .9 0 (.4 2 9 ) 1 0 .7 0 (.4 2 1 ) 2 7. 40 (1 .07 9 ) 2 3. 90 (.9 41 ) A S S E M B LY LO T C O D E 4 3 3 0. 00 (1 4. 1 73 ) M A X. N O TES : 1 . C OM FO R M S TO EIA -41 8 . 2 . C ON T R OL LI N G D I M EN S ION : M IL LIM E TER . 3 . D IM EN S IO N M EA SU R E D @ H U B . 4 . IN C L U D ES FL AN G E D IST OR TIO N @ O U TER ED G E. (This is an IRF530S IRF530S with assembly lot code 9B1M ) IN TE R NA TIO NA L R E C TIFIE R LO G O Tape & Reel 1 3 .5 0 (. 53 2 ) 1 2 .8 0 (. 50 4 ) Part Marking 4 .7 2 (.1 3 6 ) 4 .5 2 (.1 7 8 ) 1 6. 10 (. 63 4 ) 1 5. 90 (. 62 6 ) F EE D D IR EC T IO N 2.54 (.100) 2X A P A RT N U M B E R F5 3 0S 9 2 46 9B 1M D A TE C O D E (Y Y W W ) Y Y = YE A R W W = W EEK 6 0. 00 (2 .3 62 ) M IN . 2 6 .4 0 (1. 03 9 ) 2 4 .4 0 (.9 61 ) 30 .4 0 (1 .1 9 7) M A X. 4 3 WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, Tel: (310) 322 3331 EUROPEAN HEADQUARTERS: Hurst Green, Oxted, Surrey RH8 9BB, UK Tel: + 44 1883 732020 IR CANADA: 7321 Victoria Park Ave., Suite 201, Markham, Ontario L3R 2Z8, Tel: (905) 475 1897 IR GERMANY: Saalburgstrasse 157, 61350 Bad Homburg Tel: + 49 6172 96590 IR ITALY: Via Liguria 49, 10071 Borgaro, Torino Tel: + 39 11 451 0111 IR FAR EAST: K&H Bldg., 2F, 3-30-4 Nishi-Ikeburo 3-Chome, Toshima-Ki, Tokyo Japan 171 Tel: 81 3 3983 0086 IR SOUTHEAST ASIA: 315 Outram Road, #10-02 Tan Boon Liat Building, Singapore 0316 Tel: 65 221 8371 http://www.irf.com/ Data and specifications subject to change without notice. 11/96