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IPD09N03LB PG-TO252-3-11 Q67042-S4264 09N03LB J-STD20 JESD22 P-TO252-3-11 - Datasheet Archive
OptiMOS®2 Power-Transistor Product Summary Features V DS 1) · Qualified according to JEDEC for target applications V R
IPD09N03LB IPD09N03LB G OptiMOS®2 Power-Transistor Product Summary Features V DS 1) · Qualified according to JEDEC for target applications V R DS(on),max · Ideal for high-frequency dc/dc converters 30 9.1 m ID 50 A · N-channel, logic level · Excellent gate charge x R DS(on) product (FOM) · Superior thermal resistance PG-TO252-3-11 PG-TO252-3-11 · 175 °C operating temperature · Pb-free lead plating; RoHS compliant Type Package Ordering Code Marking IPD09N03LB IPD09N03LB G PG-TO252-3-11 PG-TO252-3-11 Q67042-S4264 Q67042-S4264 09N03LB 09N03LB Maximum ratings, at T j=25 °C, unless otherwise specified Parameter Symbol Conditions Continuous drain current ID Value T C=25 °C2) 50 T C=100 °C Unit 42 A Pulsed drain current I D,pulse T C=25 °C3) 200 Avalanche energy, single pulse E AS I D=50 A, R GS=25 57 mJ Reverse diode dv /dt dv /dt I D=50 A, V DS=20 V, di /dt =200 A/µs, T j,max=175 °C 6 kV/µs Gate source voltage4) V GS Power dissipation P tot Operating and storage temperature T j, T stg ±20 IEC climatic category; DIN IEC 68-1 Rev. 1.21 58 W -55 . 175 T C=25 °C V °C 55/175/56 page 1 2004-12-16 IPD09N03LB IPD09N03LB G Parameter Values Symbol Conditions Unit min. typ. max. - - 2.6 minimal footprint - - 75 6 cm2 cooling area5) - - 50 Thermal characteristics Thermal resistance, junction - case R thJC SMD version, device on PCB R thJA K/W Electrical characteristics, at T j=25 °C, unless otherwise specified Static characteristics Drain-source breakdown voltage V (BR)DSS V GS=0 V, I D=1 mA 30 - - Gate threshold voltage V GS(th) V DS=V GS, I D=20 µA 1.2 1.6 2 Zero gate voltage drain current I DSS V DS=30 V, V GS=0 V, T j=25 °C - 0.1 1 V DS=30 V, V GS=0 V, T j=125 °C - 10 100 V µA Gate-source leakage current I GSS V GS=20 V, V DS=0 V - 10 100 nA Drain-source on-state resistance R DS(on) V GS=4.5 V, I D=25 A - 11.4 14.2 m V GS=10 V, I D=50 A - 7.4 9.1 - 1 - 30.5 61 - S Gate resistance RG Transconductance g fs |V DS|>2|I D|R DS(on)max, I D=50 A 1) J-STD20 J-STD20 and JESD22 JESD22 1) Current is limited by bondwire; with an R thJC=2.6 K/W the chip is able to carry 59 A. 3) See figure 3 4) T j,max=150 °C and duty cycle D