IPD06N03LA IPS06N03LA IPF06N03LA IPU06N03LA P-TO252-3-11 P-TO252-3-23

IPS06N03LA OptiMOS®2 Power-Transistor IPF06N03LA IPU06N03LA Product Summary Features V DS · Ideal for high-frequency

IPD06N03LA IPD06N03LA IPS06N03LA IPS06N03LA OptiMOS®2 Power-Transistor IPF06N03LA IPF06N03LA IPU06N03LA IPU06N03LA Product Summary Features V DS · Ideal for high-frequency dc/dc converters · Qualified according to JEDEC1) for target application 25 V R DS(on),max (SMD version) 5.7 m ID 50 A · N-channel, logic level · Excellent gate charge x R DS(on) product (FOM) · Superior thermal resistance · 175 °C operating temperature Type IPD06N03LA IPD06N03LA IPF06N03LA IPF06N03LA IPS06N03LA IPS06N03LA IPU06N03LA IPU06N03LA Package P-TO252-3-11 P-TO252-3-11 P-TO252-3-23 P-TO252-3-23 P-TO251-3-11 P-TO251-3-11 P-TO251-3-21 P-TO251-3-21 Ordering Code Q67042-S4149 Q67042-S4149 Q67042-S4236 Q67042-S4236 Q67042-S4245 Q67042-S4245 Q67042-S4145 Q67042-S4145 Marking 06N03LA 06N03LA 06N03LA 06N03LA 06N03LA 06N03LA 06N03LA 06N03LA Maximum ratings, at T j=25 °C, unless otherwise specified Parameter Symbol Conditions Continuous drain current ID Value T C=25 °C2) 50 T C=100 °C Unit 50 Pulsed drain current I D,pulse T C=25 °C3) 350 Avalanche energy, single pulse E AS I D=45 A, R GS=25 225 Reverse diode dv /dt dv /dt I D=50 A, V DS=20 V, di /dt =200 A/µs, T j,max=175 °C 6 Gate source voltage4) V GS Power dissipation P tot Operating and storage temperature T j, T stg A kV/µs ±20 V 83 W -55 . 175 T C=25 °C IEC climatic category; DIN IEC 68-1 Rev. 1.7 mJ °C 55/175/56 page 1 2004-05-19 IPD06N03LA IPD06N03LA IPS06N03LA IPS06N03LA Parameter IPF06N03LA IPF06N03LA IPU06N03LA IPU06N03LA Values Symbol Conditions Unit min. typ. max. - - 1.8 minimal footprint - - 75 6 cm2 cooling area5) - - 50 25 - - Thermal characteristics Thermal resistance, junction - case R thJC SMD version, device on PCB R thJA K/W Electrical characteristics, at T j=25 °C, unless otherwise specified Static characteristics Drain-source breakdown voltage V (BR)DSS V GS=0 V, I D=1 mA Gate threshold voltage V GS(th) V DS=V GS, I D=40 µA 1.2 1.6 2 Zero gate voltage drain current I DSS V DS=25 V, V GS=0 V, T j=25 °C - 0.1 1 V DS=25 V, V GS=0 V, T j=125 °C - 10 100 V µA Gate-source leakage current I GSS V GS=20 V, V DS=0 V - 10 100 nA Drain-source on-state resistance R DS(on) V GS=4.5 V, I D=30 A - 7.7 9.6 m V GS=4.5 V, I D=30 A, SMD version - 7.5 9.4 V GS=10 V, I D=30 A - 5.0 5.9 V GS=10 V, I D=30 A, SMD version - 4.8 5.7 - 1 - 29 59 - S Gate resistance RG Transconductance g fs |V DS|>2|I D|R DS(on)max, I D=30 A 1) J-STD20 J-STD20 and JESD22 JESD22 2) Current is limited by bondwire; with an R thJC=1.8 K/W the chip is able to carry 94 A. 3) See figure 3 4) T j,max=150 °C and duty cycle D