IP113M 10/100BASE-TX/ 100BASE-FX 10/100BASE-TX 10M/100M TS-1000 IEEE802 - Datasheet Archive

 

Preliminary Data Sheet Managed 10/100Base-TX / FX Media Converter Features General Description A 10/100BASE-TX/ 100BASE-FX

 

IP113M IP113M LF Preliminary Data Sheet Managed 10/100Base-TX / FX Media Converter Features General Description A 10/100BASE-TX/ 10/100BASE-TX/ 100BASE-FX 100BASE-FX converter with a SMI port for management Built in a 10/100BASE-TX 10/100BASE-TX transceiver Built in a PHY for 100BASE-FX 100BASE-FX Built in a 2-port switch ­ Pass all packets without address and CRC check (optional) ­ Supports modified cut-through frame forwarding for low latency ­ Supports pure converter mode data forwarding for extreme low latency ­ Supports flow control for full and half duplex operation ­ Bandwidth control ­ Max packet length 1600 bytes ­ Optional forward fragments Built in 128Kb RAM for data buffer Supports 3.3v I/O tolerance SMI (MDC, MDIO) and MII registers for management ­ Configure local and remote IP113M IP113M LF through local SMI ­ Monitor local and remote IP113M IP113M LF through local SMI ­ Configure/ monitor TP port support (auto-negotiation or force 10M/100M 10M/100M, full/half) ­ Configure/ monitor flow control, bandwidth ­ Supports loop back test (In-band or out-band, auto or program) ­ The maintenance frame is compliant to TS-1000 TS-1000 standard (the Telecommunication Technology Committee, TTC) Supports Statistic Counters Supports auto MDI-MDIX function Supports link fault pass through function Supports far end fault function LED display for link/activity, full/half, 10/100 Built in a watchdog timer to monitor internal switch error Supports EEPROM Configuration 0.25u CMOS technology Single 2.5V power supply 48-pin LQFP package Support Lead Free package (Please refer to the Order Information) IP113M IP113M LF can be a 10/100BASE-TX 10/100BASE-TX to 100BASE-FX 100BASE-FX converter with an SMI port for management. It consists of a 2-port switch controller, a fast Ethernet transceiver and a PHY for 100BASE-FX 100BASE-FX. The transceivers in IP113M IP113M LF are designed in DSP approach with advance 0.25um technology; this results in high noise immunity and robust performance. IP113M IP113M LF not only supports store and forward mode, it also supports modified cut through mode and pure converter mode for low latency data forwarding. IP113M IP113M LF can transmit packet(s) up to 1600 bytes to meet requirement of extra long packets. IP113M IP113M LF supports remote management function. IP113M IP113M LF supports remote access functions and it also supports remote monitor and loop back test function defined in TS-1000 TS-1000 spec (*). Local IP113M IP113M LF can access the MII registers of remote IP113M IP113M LF by programming local IP113M IP113M LF's MII registers via SMI connection. IP113M IP113M LF implements the management function using the maintenance frame defined in TS-1000 TS-1000 spec. IP113M IP113M LF supports IEEE802 IEEE802.3x, collision base backpressure, and various LED functions, etc. These functions can be configured to fit the different requirements by feeding operation parameters via EEPROM interface or pull up/down resistors on specified pins. * The Telecommunication Technology Committee owns the copyright of TS-1000 TS-1000. 1/58 Copyright © 2004, IC Plus Corp. April 9, 2007 IP113M IP113M LF-DS-R11 LF-DS-R11 IP113M IP113M LF Preliminary Data Sheet Contents Features. 1 General Description. 1 Contents . 2 Revision History. 4 Block Diagram . 5 Application Diagram . 5 Applications . 6 Managed converter (up to 31 pieces of IP113M IP113M LF in a chassis) . 6 Un-managed converter. 6 PIN Diagram . 7 1. PIN Description . 8 PIN Description (continued). 9 PIN Description (continued). 10 PIN Description (continued).11 PIN Description (continued). 12 PIN Description (continued). 13 2. Functional Description . 14 2.1 Data forwarding . 14 2.1.1 Modified cut-through mode. 14 2.1.2 Pure converter mode . 14 2.1.3 Fragment forwarding . 14 2.2 TP port force mode . 15 2.3 Remote management . 16 2.3.1 Maintenance frame format at MII . 16 2.3.2 Bit definition of maintenance frame . 16 2.3.3 Bit definition of maintenance frame (continued). 17 2.3.4 Remote monitor . 18 2.3.5 Remote control read . 18 2.3.6 Remote control write. 18 2.4 Loop back test . 19 2.4.1 Out-band loop back test . 19 2.4.2 In-band loop back test . 21 2.4.3 Programming procedure for In-band loop back test. 22 2.4.4 Auto in-band loop back test. 22 2.5 Remote monitor without SMI programming. 23 2.5.1 Auto sends (Status change notice). 23 2.6 Link fault pass through . 24 2.6.1 Normal case . 24 2.6.2 Remote TP port disconnected . 24 2.6.3 FX port disconnected . 25 2.6.4 LED diagnostic functions for fault indication . 25 2.7 EEPROM ­ store the initial value . 26 2.8 Auto MDI_MDIX. 27 2.9 Serial management interface. 28 3. MII registers . 29 3.1 The basic MII registers . 30 The basic MII registers 0 . 30 The basic MII registers 1 . 32 The basic MII registers 1(continued). 33 The basic MII registers 2 , 3 . 34 The basic MII registers 4 . 35 The basic MII registers 5 . 36 2/58 Copyright © 2004, IC Plus Corp. April 9, 2007 IP113M IP113M LF-DS-R11 LF-DS-R11 IP113M IP113M LF Preliminary Data Sheet 4. 5. 6. The basic MII registers 6 . 37 3.2 Extended MII registers and EEPROM registers . 38 Extended MII registers and EEPROM registers 16. 39 Extended MII registers and EEPROM registers 17. 40 Extended MII registers and EEPROM registers 17(continued). 41 Extended MII registers and EEPROM registers 18. 42 Extended MII registers and EEPROM registers 19. 43 Extended MII registers and EEPROM registers 20. 44 Extended MII registers and EEPROM registers 20(continued). 45 Extended MII registers and EEPROM registers 21. 46 Extended MII registers and EEPROM registers 22. 47 Extended MII registers and EEPROM registers 22(continued). 48 Extended MII registers and EEPROM registers 23. 49 Extended MII registers and EEPROM registers 23(continued). 50 Extended MII registers and EEPROM registers 24. 51 Extended MII registers and EEPROM registers 25. 52 Extended MII registers and EEPROM registers 26. 53 Extended MII registers and EEPROM registers 27,28,29,30. 54 Extended MII registers and EEPROM registers 31. 55 Electrical Characteristics . 57 4.1 Absolute Maximum Rating. 57 4.2. DC Characteristic . 57 Order Information. 57 Package Detail. 58 3/58 Copyright © 2004, IC Plus Corp. April 9, 2007 IP113M IP113M LF-DS-R11 LF-DS-R11 IP113M IP113M LF Preliminary Data Sheet Revision History Revision # Change Description IP113M IP113M LF-DS-R01 LF-DS-R01 Initial release. IP113M IP113M LF-DS-R02 LF-DS-R02 IP113M IP113M LF-DS-R03 LF-DS-R03 IP113M IP113M LF-DS-R04 LF-DS-R04 Remove Operation Junction Temperature. IP113M IP113M LF-DS-R05 LF-DS-R05 TP port should be linked at 100M full duplex when working at this mode. IP113M IP113M LF-DS-R06 LF-DS-R06 Update page 42,1 IP113M IP113M LF-DS-R07 LF-DS-R07 Add the order information for lead free package. Update page 50 (Item:31.2 & 31.3) IP113M IP113M LF-DS-R08 LF-DS-R08 Update page 27 Update the default value of following resisters MII reg3.[5:4], reg4.10, reg6.2, reg16.6, reg18.3, reg18.13, reg22.4, reg22.6, reg23.13 and Description of reg26.0 Add explanation to MII reg31.[5:4], reg31.3, reg31.2 IP113M IP113M LF-DS-R09 LF-DS-R09 Revise the diagram. IP113M IP113M LF-DS-R10 LF-DS-R10 Modify the IPL : pull-low and IPH : pull-high on page 8. IP113M IP113M LF-DS-R11 LF-DS-R11 Add Power Pin description on Page13 4/58 Copyright © 2004, IC Plus Corp. April 9, 2007 IP113M IP113M LF-DS-R11 LF-DS-R11 IP113M IP113M LF Preliminary Data Sheet Block Diagram MDC MDIO RXIP RXIM TXOP TXOM SCL SDA SSRAM MII registers 10/100M 10/100M TX PHY EEPROM I/F MII Two port switch Forward Mode Control PLL/ Clock Generator MII 100M FX LED I/F FXSD FXRDP FXRDM FXTDP FXTDM LED Remote Control Application Diagram FX Fiber Module IP113M IP113M LF TX 5/58 Copyright © 2004, IC Plus Corp. April 9, 2007 IP113M IP113M LF-DS-R11 LF-DS-R11 IP113M IP113M LF Preliminary Data Sheet Applications Managed converter (up to 31 pieces of IP113M IP113M LF in a chassis) VCC FAST_FWD MDC, MDIO uC IP113M IP113M LF (for management) X1 X 31 Un-managed converter 10BASE 10BASE_T/1 00BASE-TX 00BASE-TX PHY1 100BASE-FX 100BASE-FX PHY2 SWITCH RAM IP113M IP113M LF 6/58 Copyright © 2004, IC Plus Corp. April 9, 2007 IP113M IP113M LF-DS-R11 LF-DS-R11 IP113M IP113M LF Preliminary Data Sheet MDIO AVCC MDC SCL / ADDR0 SDA VCC GND GND OSCI X2 VCC LED_FX_SD/ SPEED_MODE LED_FX_FDX/ ADDR2 48 47 46 45 44 43 42 41 40 39 38 37 PIN Diagram 1 36 LED_FX_LINK/ FX_FULL GND_IO BGRES 2 35 AUTO_TEST 3 34 VCC_IO GND 4 33 LED_TP_SPD RXIP 5 32 LED_TP_FDX/ ADDR3 RXIM 6 31 LED_TP_LINK/ ADDR4 30 LED_FX_FEF_DET/ DUPLEX_MODE AVCC 7 TXOP IP113M IP113M LF 8 20 21 22 23 24 LFP DIRECT_WIRE FAST_FWD LED_RMT_TP_FDX/ TP_FORCE FXTDM FXTDP FXRDP GND LED_RMT_TP_SPD/ AUTO_SEND 19 12 VCC ADDR1 18 TSM 25 FXSD AVCC 26 17 TSE 11 16 27 15 10 INTB GND TXOM 14 9 RESETB FXRDM LED_RMT_TP_LINK/ X_EN 28 13 29 7/58 Copyright © 2004, IC Plus Corp. April 9, 2007 IP113M IP113M LF-DS-R11 LF-DS-R11 IP113M IP113M LF Preliminary Data Sheet 1. PIN Description Type I Description Input pin O Output pin IPH Input pin with internal pull-high resistor IPL Input pin with internal pull-low resistor Pin no. Label Type Description Transceiver 5, 6 RXIP, RXIM I TP receive 8, 9 TXOP, TXOM O TP transmit 2 BGRES O Band gap resistor It is connected to GND through a 6.19k (1%) resistor in application circuit. 18 FXSD I 100Base-FX signal detect Fiber signal detect. It is an input signal from fiber MAU. Fiber signal detect is active if the voltage on FXSD is higher than the threshold voltage, which is 1.35v ±5% when VCC is equal to 2.5v. 13, 14 FXRDP, FXRDM I Fiber receiver data pair Common-mode voltage of FXRDP and FXRDM are suggested to near 0.5x AVCC. When voltage peak-to-peak>0.1V,FXRX could be workable. 16, 17 FXTDP, FXTDM O Fiber transmitter data pair FXTX with the external 100 resistor. Common-mode voltage of FXTDP and FXTDM are suggested to near 0.5x AVCC. Swing of Voltage 0.8V. 8/58 Copyright © 2004, IC Plus Corp. April 9, 2007 IP113M IP113M LF-DS-R11 LF-DS-R11 IP113M IP113M LF Preliminary Data Sheet PIN Description (continued) Pin no. Label Type Description LED pins 31 LED_TP_LINK O TP port link LED On: link ok, Off: link fail, Flash: link ok & activity (Flash: on for 20ms and off for 80ms) 33 LED_TP_SPD O TP port speed LED On: 100M, Off: 10M 32 LED_TP_FDX O TP port full duplex LED On: full, Off: half, Flash: half & collision happens (Flash: on for 20ms and off for 80ms) 36 LED_FX_LINK O Fiber port link LED On: link ok, Off: link fail, Flash: link ok & activity (Flash: on for 20ms and off for 80ms) 37 LED_FX_FDX O Fiber port full duplex LED On: full, Off: half, Flash: half & collision happens (Flash: on for 20ms and off for 80ms) 38 LED_FX_SD O Fiber port signal detect On: FXSD is active, Off: FXSD is inactive 30 LED_FX_FEF_DET O Far end fault pattern received Far End Fault Pattern received: LED On: 80ms, LED Off: 20ms Far End Fault Pattern not Receive: LED is always off 29 LED_RMT_TP_LINK O LED for link status of TP port of remote IP113M IP113M LF Pin 3 AUTO_TEST = 0 25 LED_RMP_TP_SPD O On: link ok, Flash Off: link fail (On: 80ms, Off: 20ms) LED for speed of TP port of remote IP113M IP113M LF Pin 3 AUTO_TEST = 0 24 LED_RMT_TP_FDX O Pin 3 AUTO_TEST = 1 On: 100M, On: loop back test complete, Off: 10M Off: under loop back test LED for full duplex of TP port of remote IP113M IP113M LF Pin 3 AUTO_TEST = 0 On: full duplex, Off: half duplex Note: The output of LED pin is logic low when the LED is on. 9/58 Copyright © 2004, IC Plus Corp. Pin 3 AUTO_TEST = 1 Pin 3 AUTO_TEST = 1 On: loop back test result is ok, Off: loop back test result fails April 9, 2007 IP113M IP113M LF-DS-R11 LF-DS-R11 IP113M IP113M LF Preliminary Data Sheet PIN Description (continued) Pin no. Label Type Description LED pins used as initial setting mode during reset 29 X_EN IPH Flow control enable on TP port and fiber port 1: enable (default), 0: disable 24 TP_FORCE IPL Local TP port auto negotiation enable 1: TP port supports auto-negotiation with limited capability defined by pin 38 SPEED_MODE and pin 30 DUPLEX_MODE. 0: TP port supports auto-negotiation with 10M/100M 10M/100M, full/ half capability (default) The setting may be updated by programming EEPROM register 3.5 or MII register 20.13. 38 SPEED_MODE IPH Local TP port speed selection 1: TP port has the 100Mb speed ability 0: TP port has the 10Mb speed ability only It is valid only if pin 24 TP_FORCE is enabled. 30 DUPLEX_MODE IPH Local TP port duplex selection 1: TP port has the full duplex ability 0: TP port has the half duplex ability only 25 AUTO_SEND IPL Auto send the status to the remote IP113M IP113M LF 1: enable 0: disable (default) 36 FX_FULL IPH Set the duplex of fiber port 1: full duplex (default) 0: half duplex 3 AUTO_TEST IPL Auto loop back test 1: enable When IP113M IP113M LF detects a low-to-high transition on this pin, it will perform loop back test for once. It supports an easy way to instruct IP113M IP113M LF performing fiber loop back test without programming MII registers. 0: disable (default) It is valid only if pin 24 TP_FORCE is enabled. 10/58 Copyright © 2004, IC Plus Corp. April 9, 2007 IP113M IP113M LF-DS-R11 LF-DS-R11 IP113M IP113M LF Preliminary Data Sheet PIN Description (continued) Pin no. Label Type Description LED pins used as initial setting mode during reset 11/58 Copyright © 2004, IC Plus Corp. April 9, 2007 IP113M IP113M LF-DS-R11 LF-DS-R11 IP113M IP113M LF Preliminary Data Sheet PIN Description (continued) Pin no. Label MC operation mode 21 LFP 22 23 DIRECT_WIRE FAST_FWD Type IPL IPL Description Link fault pass through (LFP) 1: enable Link status of one port is forwarded to the other port. 0: disable (default) DIRECT_ FAST_F Function WIRE WD 0 0 Store and forward switch mode (default) 0 1 Modified cut-through switch mode 1 1 0 1 Converter mode Converter mode with auto-change-forward function Store and forward switch mode: IP113M IP113M LF begins to forward a frame at the end of receiving a frame completely. Modified cut-through switch mode: IP113M IP113M LF begins to forward a frame after the first 64 bytes data received. TP port should be forced at 100M at this mode. Converter mode: Incoming frames are not buffered in IP113M IP113M LF to achieve the min latency. Both TP port and fiber port of IP113M IP113M LF should work at 100M full duplex in this mode. If TP port is linked at half duplex, the total length of UTP cable and fiber should be less than 60 meters to meet the requirement of CSMACD in IEEE802 IEEE802.3. Converter mode with auto-change-forward function: IP113M IP113M LF will change forward mode itself if it detects the speed is different in TP port and FX port. In converter mode, IP113M IP113M LF forwards IEEE802 IEEE802.3x pause frame directly. In the other modes, IP113M IP113M LF doesn't forward IEEE802 IEEE802.3x pause frame directly, it sends out pause frame when its internal buffer is full. 12/58 Copyright © 2004, IC Plus Corp. April 9, 2007 IP113M IP113M LF-DS-R11 LF-DS-R11 IP113M IP113M LF Preliminary Data Sheet PIN Description (continued) Pin no. Label Type SMI interface 47, 48 MDC, MDIO I, IO SMI interface The external MAC device uses the interface to program IP113M IP113M LF. MDIO is an open drain. IPL PHY address The external MAC device uses the address to identify each IP113M IP113M LF in a chassis. IP113M IP113M LF also uses ADDR[2:0] as EEPROM address A[2:0] to read EEPROM. Type Description 31, 32, 37, 12, 46 ADDR[4:0] Pin no. Label Description EEPROM interface 45, 46 SDA, SCL Pin no. Label IPH, O EEPROM interface Type Misc. 28 RESETB I 41, 40 OSCI, X2 I, O Description Reset It is low active. Crystal pins OSCI and X2 are connected to a 25Mhz crystal. If a 25MHz oscillator is used, OSCI is connected to the oscillator's output and X2 should be left open. 26, 27 TSM, TSE 15 INTB Pin no. IPL O Label Scan pins These two pins should be left open or connected to ground for normal operation. Interrupt 0: an interrupt happens. Its output is low. 1: no interrupt. Its output is high impedance and it needs an external pull up resistor. Type Description Power 1,7,11 AVCC 2.5V Analog Power 19,39,44 34 VCC VCC_IO 2.5V Digital Power 3.3V or 2.5V Digital Power 35 GND_IO I/O Ground 4,10,20, 42,43 GND Ground 13/58 Copyright © 2004, IC Plus Corp. April 9, 2007 IP113M IP113M LF-DS-R11 LF-DS-R11 IP113M IP113M LF Preliminary Data Sheet 2. Functional Description 2.1 Data forwarding IP113M IP113M LF supports three types of data forwarding mode, store & forward mode, modified cut-through mode and pure converter mode. It can forward a frame despite of its address and CRC error. IP113M IP113M LF begins to forward the received data when it receives the frame completely. The latency depends on the packet length. 2.1.1 Modified cut-through mode IP113M IP113M LF begins to forward the received data when it receives the first 64 bytes of the frame. The latency is about 512 bits time width. The maximum packet length is up to1600 bytes in this mode. Please refer to pin description of FAST_FWD for configuration information. 2.1.2 Pure converter mode IP113M IP113M LF operates with the minimum latency in this mode. The transmission flow does not wait until entire frame is ready, but instead it forwards the received data immediately after the data being received. Both transceivers are interconnected via internal MIIs and the internal switch engine and data buffer are not used. Both TP port and fiber port of IP113M IP113M LF should work at 100M full duplex in this mode. If TP port is linked at half duplex, the total length of UTP cable and fiber should be less than 60 meters to meet the requirement of CSMACD in IEEE802 IEEE802.3. The packet length is not limited at this mode. Please refer to pin description of DIRECT_WIRE for configuration information. In converter mode, it is strongly recommended that both TP port and fiber port of IP113M IP113M LF should work at 100M full duplex. If TP port is linked at half duplex, the UTP cable length should be less than 30 meters to meet the requirement of CSMACD in IEEE802 IEEE802.3. 2.1.3 Fragment forwarding IP113M IP113M LF forwards CRC error packets but it will filter fragments when it works in modified cut-through mode. IP113M IP113M LF forwards fragments if user turns on bit 3 of MII register 20. 14/58 Copyright © 2004, IC Plus Corp. April 9, 2007 IP113M IP113M LF-DS-R11 LF-DS-R11 IP113M IP113M LF Preliminary Data Sheet 2.2 TP port force mode The TP port of IP113M IP113M LF can work at auto mode or force mode. The following table shows all of the combination of its TP port. Link partner's capability AN on {TP_FORCE, SPEED_MODE, DUPLEX_MODE} IP113M IP113M LF's link result AN off 100F 100H 10F 10H 100F 100H 10F 10H 100F 100H 10F 10H 100H 100H 10H 10H IP113M IP113M LF's capability 011 100/10M 100/10M, Full/Half, AN on 010 100/10M 100/10M, Half, AN on X 100H X 10H 100H 100H 10H 10H 001 000 10M, Full/Half, AN on 10M, Half, AN on X X X X 10F X 10H 100H 100H 10H 10H 100H 100H 10H 10H 10H 111 100M, Full, AN on 100F X X X 100F 100F X X 110 100M, Half, AN on X 100H X X 100H 100H X X 101 10M, Full, AN on X X 10F X X X 10F 10F 100 10M, Half, AN on X X X 10H X X 10H 10H Note: AN on: with auto-negotiation capability AN off: without auto-negotiation capability 100F: 100M full duplex 100H: 100M half duplex 10F: 10M full duplex 10H: 10M half duplex 15/58 Copyright © 2004, IC Plus Corp. April 9, 2007 IP113M IP113M LF-DS-R11 LF-DS-R11 IP113M IP113M LF Preliminary Data Sheet 2.3 Remote management IP113M IP113M LF supports remote monitor and configuration function. IP113M IP113M LF implement the function by exchanging maintenance frames on fiber ports between two IP113M IP113M LF's. The maintenance frames are not forwarded to TP ports. The frame format follows the TS-1000 TS-1000 standard. 2.3.1 Maintenance frame format at MII TXD0 F0 F4 C0 C4 C8 C12 S0 S4 S8 S12 M0 M4 M8 M12 M16 M20 M24 M28 M32 M36 M40 M44 E0 E4 TXD1 F1 F5 C1 C5 C9 C13 S1 S5 S9 S13 M1 M5 M9 M13 M17 M21 M25 M29 M33 M37 M41 M45 E1 E5 TXD2 F2 F6 C2 C6 C10 C14 S2 S6 S10 S14 M2 M6 M10 M14 M18 M22 M26 M30 M34 M38 M42 M46 E2 E6 TXD3 F3 F7 C3 C7 C11 C15 S3 S7 S11 S15 M3 M7 M11 M15 M19 M23 M27 M31 M35 M39 M43 M47 E3 E7 TXEN 2.3.2 Bit definition of maintenance frame Bit Item Description F7 ­ F0 C0 Preamble Discriminator for the maintenance signal C1 Direction 0: terminal MC central MC 1: central MC terminal MC (MC: media converter) C3 ­ C2 Command 00: Reserved 10: Indication 01: Request 11: Acknowledge C7 ­ C4 Version 0000 C15 ­ C8 Control signal C15 Note 01010101 0 Fixed Fixed Fixed C8 0 0 0 0 0 0 01 Function Loop test start 0 0 0 0 0 0 00 Loop test finished 0 0 0 0 0 0 10 Status indication R/W 11 R/W link partner's registers Address [4:0] S0 Condition of power 0: normal, 1: power off S1 Situation of receiving optical power 0: normal, 1: abnormal S2 Terminal/ network side link 0: link up, 1: link down If S11="1", S2="X" S3 MC (media converter) fails 0: normal, 1: abnormal S4 Informing way for optical 0: maintenance frame receiving power off 1: Far end fault indication Status indication for loop test 0: normal mode, 1: under loop test S5 16/58 Copyright © 2004, IC Plus Corp. April 9, 2007 IP113M IP113M LF-DS-R11 LF-DS-R11 IP113M IP113M LF Preliminary Data Sheet 2.3.3 Bit definition of maintenance frame (continued) Bit Item Description Note S6 Information for notice of terminal link status (Available for option B or not) 0: terminal IP113M IP113M LF does not support option B. 1: terminal IP113M IP113M LF supports option B, which can inform speed, duplex, and auto-negotiation in terminal IP113M IP113M LF. If S11 = "1", S6="X' S8 ­ S7 Terminal link speed 00: 10 Mbps 01: 100 Mbps 10: 1000 Mbps 11: others It is valid, if S6 = "1". If S2 or S11 = "1", S7, S8 = {X, X} S9 Duplex for the terminal side 1: full duplex, 0: half duplex It is valid, if S6 = "1". If S6 ="0", S9="0". If {S7, S8} = {1,1}, S9="X" If S2 or S11 = "1", S9="X" S10 Auto-negotiation capability for the terminal side 1: available, 0: un-available It is valid, if S6 = "1". If S6 ="0", S10="0". If {S7, S8} = {1,1}, S10="X" If S11 = "1", S10="X" S11 Number of interface in Terminal/ network side 0: one UTP 1: more than one UTP S15 ­ S12 Reserved M23 ­ M0 Vender code M47 ­ M24 Model number E7 ­ E0 FCS Vender code for TTC standard It is C30900h. Specified by vender It is 000000h. CRC ­ 8 FCS calculation area: C0 - M47 17/58 Copyright © 2004, IC Plus Corp. April 9, 2007 IP113M IP113M LF-DS-R11 LF-DS-R11 IP113M IP113M LF Preliminary Data Sheet 2.3.4 Remote monitor Refer to the diagram below, users can instruct central IP113M IP113M LF, on the right, to issue a status request frame to get status defined in TS-1000 TS-1000 by programming MII register 24. The terminal IP113M IP113M LF, on the left, receives the status request frame and sends out its current status as a response frame onto the fiber port when it is available. The central IP113M IP113M LF receives the status frame and stores the status of terminal IP113M IP113M LF to its MII register 23. An acknowledge maintenance frame is store to MII register 26~30. The status of terminal IP113M IP113M LF is shown on the LEDs of central IP113M IP113M LF. (1) TP IP113M IP113M LF (terminal) Maintenance frame (C1=1, C2-3=10, C8-15 C8-15=01000000) FX IP113M IP113M LF (central) (MII reg 24, 23) Maintenance frame (C1=0, C2-3=11, C8-15 C8-15=01000000) TP (2) MDC, MDIO 2.3.5 Remote control read Users can instruct central IP113M IP113M LF to issue a remote control read frame to read the MII register of terminal IP113M IP113M LF by programming MII register 24. The bits [11:7] of the register 24 are filled with the address of register and bits [6:4] of the register 24 are filled with "011". The terminal IP113M IP113M LF receives the frame and sends out the content of the MII register to central IP113M IP113M LF when it is available. The central IP113M IP113M LF receives the frame and stores the data to MII register 27. An acknowledge maintenance frame is stored to MII register 26~30. The status of terminal IP113M IP113M LF is shown on LED of central IP113M IP113M LF. TP Maintenance frame (C1=1, C2-3=10, C8-15 C8-15=110xxxxx) IP113M IP113M LF (terminal) FX IP113M IP113M LF (central) (MII reg 24,27) Maintenance frame (C1=0, C2-3=11, C8-15 C8-15=01000000) TP MDC, MDIO 2.3.6 Remote control write Users can instruct central IP113M IP113M LF to issue a configure frame to write the MII register of terminal IP113M IP113M LF by programming MII register 24 and 25. The bits [11:7] of the register 24 are filled with the address of register and bits [6:4] of the register 24 are filled with "111". MII register 25 defines the data. The terminal IP113M IP113M LF receives the configure frame, configures itself according to the content of the frame and sends out its current status as a response frame onto the fiber port when it is available. The status of terminal IP113M IP113M LF is shown on LED of central IP113M IP113M LF. TP IP113M IP113M LF (terminal) Maintenance frame (C1=1, C2-3=10, C8-15 C8-15=111xxxxx) FX (MII reg 24,25) Maintenance frame (C1=0, C2-3=11, C8-15 C8-15=01000000) 18/58 Copyright © 2004, IC Plus Corp. IP113M IP113M LF (central) TP MDC, MDIO April 9, 2007 IP113M IP113M LF-DS-R11 LF-DS-R11 IP113M IP113M LF Preliminary Data Sheet 2.4 Loop back test IP113M IP113M LF supports two kind of loop back test function, in-band loop back test and out-band loop back test. 2.4.1 Out-band loop back test Users can instruct central IP113M IP113M LF to issue a maintenance frame onto the fiber port by programming MII register 24 to request a loop back test. Central IP113M IP113M LF does not generate test frames and users need an external packet source from PC. 1. Disconnect switch port and instruct the terminal IP113M IP113M LF to perform loop back and disable terminal T2 timer by programming central IP113M IP113M LF through SMI (1) IP113M IP113M LF (terminal) TP Maintenance frame (C1=1, C2-3=10, C8-15 C8-15=10000000) FX IP113M IP113M LF (central) TP Switch (MII reg 24) (2) Maintenance frame (C1=0, C2-3=11, C8-15 C8-15=10000000) MDC, MDIO 2 . T e r m in a l IP 1 1 3 M L F r u n s a t lo o p b a c k m o d e IP 1 1 3 M L F ( te r m in a l) TP IP 1 1 3 M L F ( c e n tr a l) FX TP S w itc h ( M II r e g 0 .1 4 = 1 ) 3. PC forces test frames to central IP113M IP113M LF and terminal IP113M IP113M LF loops back the frames. IP113M IP113M LF (terminal) TP test frame IP113M IP113M LF (central) FX TP (MII reg 0.14=1) PC test frame 4. PC reports the loop back test result after sending all test frames . IP113M IP113M LF (terminal) TP (MII reg 0.14=1) IP113M IP113M LF (central) FX PC 19/58 Copyright © 2004, IC Plus Corp. TP April 9, 2007 IP113M IP113M LF-DS-R11 LF-DS-R11 IP113M IP113M LF Preliminary Data Sheet 5. Reconnect switch and instruct the central IP113M IP113M LF to end loop back test and enable T2 timer. (1) IP113M IP113M LF (terminal) TP Maintenance frame (C1=1, C2-3=10, C8-15 C8-15=00000000) FX IP113M IP113M LF (central) TP Switch (MII reg 24) (2) Maintenance frame (C1=0, C2-3=11, C8-15 C8-15=00000000) MDC, MDIO 20/58 Copyright © 2004, IC Plus Corp. April 9, 2007 IP113M IP113M LF-DS-R11 LF-DS-R11 IP113M IP113M LF Preliminary Data Sheet Loop back test (continued) 2.4.2 In-band loop back test Besides performing the loop back test with an external packet source, IP113M IP113M LF supports an easy alternative. IP113M IP113M LF sends out private maintenance frame to do loop back test. All users have to do is to program MII registers through SMI. 1. Disabe receive function of central TP port and instruct the terminal IP113M IP113M LF to perform loop back and disable T2 timer by programming central IP113M IP113M LF through SMI Maintenance frame (C1=1, C2-3=10, C8-15 C8-15=10000000) IP113M IP113M LF (terminal) FX TP IP113M IP113M LF (central) TP Switch (MII reg 24) MDC, MDIO 2. Terminal IP113M IP113M LF runs at loop back mode and acknowledges with maintenance frame IP113M IP113M LF (terminal) TP IP113M IP113M LF (central) FX TP Switch (MII reg 0.14=1) Maintenance frame (C1=0, C2-3=11, C8-15 C8-15=10000000) 3. Central IP113M IP113M LF forces test frames to terminal IP113M IP113M LF and terminal IP113M IP113M LF loops back the test frames. Central IP113M IP113M LF checks the received test frame. test frame IP113M IP113M LF (terminal) TP IP113M IP113M LF (central) FX TP Switch (MII reg 24,25) (MII reg 0.14=1) test frame MDC, MDIO 4. Central IP113M IP113M LF ends loop back test enables receive function of TP port and enable LP T 2 timer (1) IP113M IP113M LF (terminal) TP Maintenance frame (C1=1, C2-3=10, C8-15 C8-15=00000000) FX IP113M IP113M LF (central) TP Switch (MII reg 24) (2) Maintenance frame (C1=0, C2-3=11, C8-15 C8-15=00000000) 21/58 Copyright © 2004, IC Plus Corp. MDC, MDIO April 9, 2007 IP113M IP113M LF-DS-R11 LF-DS-R11 IP113M IP113M LF Preliminary Data Sheet Loop back test (continued) 2.4.3 Programming procedure for In-band loop back test Step Description C1 C3~C2 1 Set local IP113M IP113M LF TP receive disabled C15~C8 Note Set Reg. 20.14 off 2a Set remote T2 timer disabled by maintenance frame 1 01 11 11 11 11 Reg24 and Reg 25 2 Set remote IP113M IP113M LF to be loop back mode enabled by maintenance frame 1 01 00 00 00 01 TS-1000 TS-1000: loop back set 3 Remote IP113M IP113M LF sends back loop back acknowledge 4 Send loop back test maintenance frame 5 Remote IP113M IP113M LF send back acknowledge 6 Local IP113M IP113M LF stores the loop back maintenance to Reg. 26~30 and checks CRC bit is in Reg. 26.12 - 7 Repeat step 4~6 continuously - 8 Set remote IP113M IP113M LF to be loop back mode disable by maintenance frame 9 Remote IP113M IP113M LF sends back loop back acknowledge 10 Set local IP113M IP113M LF TP receive enable -1 -01 - 1 11 01 10 11 - 01 - - Reg24 and Reg 25 - 00 00 00 00 - - - TC-1000 TC-1000: loop back end - -Set Reg. 20.14 on 2.4.4 Auto in-band loop back test Step Description 1 Set pin AUTO_TEST to "1" (The following step is executed automatically by IP113M IP113M LF) 1.1 Central IP113M IP113M LF sends loop back start request to remote IP113M IP113M LF and goes to CST2 state. 1.2 Remote IP113M IP113M LF sends loop back start acknowledge to Central IP113M IP113M LF and enters loop back test mode. 1.3 Central IP113M IP113M LF goes to CST1 state and begins sending 15 frames in 64 bytes. 1.4 Remote IP113M IP113M LF loops back the received frames at the TP port's PMD sub-layer. 1.5 Central IP113M IP113M LF checks the loop back frames and reports the result. 2 The LED pin LED_RMT_TP_LINK is Flash (on 80ms / off 20ms) during the auto loop back test period (AUTO_TEST is "1"). 3 The LED pin LED_RMT_TP_SPD indicates the loop back test complete (on) (when AUTO_TEST is "1"). The LED pin LED_RMT_TP_FDX indicates the loop back test ok (on) (when AUTO_TEST is "1") 4 If another auto loop back test is needed, set AUTO_TEST to "0" and then "1". That is, AUTO_TEST is triggered whenever there is a low-to-high transition on this pin. 22/58 Copyright © 2004, IC Plus Corp. April 9, 2007 IP113M IP113M LF-DS-R11 LF-DS-R11 IP113M IP113M LF Preliminary Data Sheet 2.5 Remote monitor without SMI programming 2.5.1 Auto sends (Status change notice) IP113M IP113M LF sends out status frame without receiving status request frame if pin AUTO_SEND is pulled high. It sends out the first status frame onto the fiber port when the link status of fiber port has established. It sends out status frames when the status on TP port has changed. IP113M IP113M LF supports two types of frame. For a TS-1000 TS-1000 maintenance frame, C[9:8] is 2'b10 and S[15:0] is defined as that in TS-1000 TS-1000 standard. For an ICplus maintenance frame, C[9:8] is 2'b11 and S[15:0] is the content of MII register 22. It carries ICplus private defined information. User can select the frame type by programming MII register 20.10. Central IP113M IP113M LF uses the mechanism to get the status of the remote IP113M IP113M LF even if there is no SMI programming. Option A Central IP113M IP113M LF sends indication frames to terminal IP113M IP113M LF if its status is changed. Maintenance frame (C1=1, C2-3=01, C8-9= 01) IP113M IP113M LF (terminal) TP IP113M IP113M LF (central) TP FX status changed !! Option B Terminal IP113M IP113M LF sends indication frames to central IP113M IP113M LF if its status is changed. Maintenance frame (C1=0, C2-3=01, C8-9= 01) IP113M IP113M LF (terminal) TP IP113M IP113M LF (central) TP FX status changed !! CRC polynomial for maintenance frame: X8 + X2 + X + 1 data in CRC + data X0 X1 X2 X3 X4 X5 X6 X7 CRC calculation 23/58 Copyright © 2004, IC Plus Corp. April 9, 2007 IP113M IP113M LF-DS-R11 LF-DS-R11 IP113M IP113M LF Preliminary Data Sheet 2.6 Link fault pass through When link fault pass through function is enabled, link status on TX port will inform the FX port of the same device and vice versa. From the link fault pass through procedure illustrates in the figure below, if link fail happens on IP113M IP113M LF's TX port (1), the local FX port sends non-idle pattern to notice the remote FX port (2). The remote FX port then forces its TX port to link failed after receiving the non-idle pattern (4). In other words, this mechanism will alert the link fault status of local TX port to the remote converter's TX port, and the link status of the remote TX port will become off. Link status LED will also be off for both IP113M IP113M LF and its link partner. Switch1 or NIC 1 local IP113M IP113M LF UTP (5) remote TP link is off (3) fiber port gets remote link fault information (1) TP port link failed remote IP113M IP113M LF Fiber UTP Switch2 or NIC 2 link off (2) fiber port sends non-idle pattern (4) TP link fail The procedure of link fault pass through 2.6.1 Normal case remote local UTP Switch1 LED SW1 Fiber IP113M IP113M LF LED_TP_LINK1 LED_FX_LINK1 IP113M IP113M LF UTP LED_FX_LINK2 LED_TP_LINK2 Switch2 LED SW2 Link LED on SW1 LED_TP_LINK1 LED_FX_LINK1 LED_FX_LINK2 LED_TP_LINK2 Link LED on SW2 ON ON ON ON ON ON 2.6.2 Remote TP port disconnected UTP disconnected remote Switch1 LED SW1 IP113M IP113M LF Fiber LED_TP_LINK1 LED_FX_LINK1 IP113M IP113M LF local UTP Switch2 LED_FX_LINK2 LED_TP_LINK2 LED SW2 Link LED on SW1 LED_TP_LINK1 LED_FX_LINK1 LED_FX_LINK2 LED_TP_LINK2 Link LED on SW2 Off Off Off Off 24/58 Copyright © 2004, IC Plus Corp. Off Off April 9, 2007 IP113M IP113M LF-DS-R11 LF-DS-R11 IP113M IP113M LF Preliminary Data Sheet 2.6.3 FX port disconnected remote Switch1 LED SW1 local UTP Fiber IP113M IP113M LED_TP_LINK1 LED_FX_LINK1 IP113M IP113M UTP LED_FX_LINK2 LED_TP_LINK2 Switch2 LED SW2 Link LED on SW1 LED_TP_LINK1 LED_FX_LINK1 LED_FX_LINK2 LED_TP_LINK2 Link LED on SW2 Off Off Off Off 2.6.4 LED diagnostic functions for fault indication LED_TP_LINK LED_FX_LINK LED_FX_SD LED_FX_FEF_DET On Flash Off Off Off On Flash Off Off Off On On On Off On Off Off Off Off Flash Off Off Status Link ok Link ok & activity Remote TP link off Fiber RX off, Fiber TX/ RX off Fiber TX off Note Flash: flash, period 100 ms Link fault pass through is enabled. 25/58 Copyright © 2004, IC Plus Corp. April 9, 2007 IP113M IP113M LF-DS-R11 LF-DS-R11 IP113M IP113M LF Preliminary Data Sheet 2.7 EEPROM ­ store the initial value IP113M IP113M LF supports two ways to load initial value of MII registers. The procedure is illustrated as below. 1. IP113M IP113M LF reads the default setting of MII register from pins IP113M IP113M LF pins 2. IP113M IP113M LF updates the default setting of MII by reading EEPROM. If there exists an EEPROM. EEPROM IP113M IP113M LF 3. After reading EEPROM, IP113M IP113M LF is virtually isolated from the EEPROM. Micro-controller can program both MII register and EEPROM. EEPROM IP113M IP113M LF SCL, SDA MDC, MDIO uC 4. IP113M IP113M LF reloads the content of EEPROM to recover the value in MII registers programmed by Micro-controller after power on reset. EEPROM IP113M IP113M LF 26/58 Copyright © 2004, IC Plus Corp. April 9, 2007 IP113M IP113M LF-DS-R11 LF-DS-R11 IP113M IP113M LF Preliminary Data Sheet 2.8 Auto MDI_MDIX IP113M IP113M LF supports auto MDI-MDIX. It is always enabled. The following is its application circuit for auto MDI-MDIX. RXIP RD + TXOP TD + RXIM RD - TXOM TD - IP113M IP113M LF IP113M IP113M LF AVCC 50 50 CT AVCC 50 50 MDI-MDIX 0.1u CT MDI-MDIX transformer 0.1u GND transformer GND IP113M IP113M LF's application circuit (auto MDI-MDIX on) 27/58 Copyright © 2004, IC Plus Corp. April 9, 2007 IP113M IP113M LF-DS-R11 LF-DS-R11 IP113M IP113M LF Preliminary Data Sheet 2.9 Serial management interface User can access IP113M IP113M LF's MII registers through serial management interface MDC and MDIO. A specific pattern on MDIO is used to access a MII register. Its format is shown in the following table. When the SMI is idle, MDIO is in high impedance. To initialize the MDIO interface, the management entity sends a sequence of 32 contiguous "1" and "start" on MDIO. Syatem diagram 113M LF MDC MDIO 113M LF MDC 113M LF MDIO MDC MDIO management entity Frame format