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IOR 421

Catalog Datasheet MFG & Type PDF Document Tags

ssi 73M2550

Abstract: 73M1550 Handheld Terminal Personal Digital Assistants Cellular Phones DataPort Datasheet Version 4.2.1 August , REV. 4.2.1 GENERAL DESCRIPTION The ST16C1450 is a universal asynchronous receiver and transmitter , 48-TQFP PACKAGE DSR# VCC N.C. N.C. N.C. CD# N.C. N.C. D3 D2 D1 D0 xr REV. 4.2.1 48 47 , # XTAL1 XTAL2 GND N.C. N.C. N.C. N.C. RST INT IOW# IOR# RI# 28 VCC D3 D2 D1 D0 D4 D5 , to +85°C -40°C to +85°C DEVICE STATUS Active Active Active Active 2 IOW# IOR# xr REV
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ssi 73M2550 73M1550 73M1550/2550/S INS8250 NS16450 16C450 PLCC-28 TQFP-48

ST16C1450

Abstract: 16C1450 ST16C1450 xr 2.97V TO 5.5V UART AUGUST 2005 REV. 4.2.1 GENERAL DESCRIPTION , 2.97V TO 5.5V UART REV. 4.2.1 FIGURE 2. ST16C1450 PINOUTS N.C. D3 D2 D1 N.C. D0 , . D2 23 INT 3 22 RST D3 21 RI# 4 20 IOR# 17 IOW# 19 16 XTAL2 18 , 10 20 A1 CS# 11 19 A2 15 16 17 18 GND IOR# RI# INT 14 13 , 5.5V UART REV. 4.2.1 PIN DESCRIPTIONS NAME 28-PIN PLCC 48-PIN TQFP TYPE
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ST16C450 16C1450 NCD223 ST16C1450CJ28 ST16C1450CQ48 ST16C1450IJ28 73M2550 73M1550/ ST16C1450/51

ssi 73M2550

Abstract: FIFO18 Assistants Cellular Phones DataPort Datasheet Version 4.2.1 August 2005 741.38 KB Application Notes DAN , -BYTE FIFO REV. 4.2.1 GENERAL DESCRIPTION The ST16C1550 and ST16C1551 UARTs (here on denoted as the , Cellular Phones DataPort 16 Byte TX FIFO A2:A0 D7:D0 IOR# IOW # CS# Data Bus Interface UART , . N.C. N.C. CD# N.C. N.C. D3 D2 D1 D0 xr REV. 4.2.1 NOTE: PINOUTS NOT TO SCALE. ACTUAL SIZE OF , . ST16C1550CQ48 31 30 29 28 27 26 25 XTAL1 XTAL2 GND N.C. N.C. N.C. IOW# IOR# 28
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FIFO18 ST16C1550CJ28-F 73M1550/2550 NS16C550 16C550

DSA00210750

Abstract: áç APRIL 2004 ST16C2550 2.97V TO 5.5V DUART WITH 16-BYTE FIFO REV. 4.2.1 GENERAL , input · 48-TQFP and 44-PLCC packages A2:A0 D7:D0 IOR# IOW# CSA# CSB# INTA INTB TXRDYA# TXRDYB# RXRDYA , TXRDYA# áç REV. 4.2.1 DSRA# VCC RIA# CTSA# 38 CDA# 48 45 43 42 41 40 , A0 A1 A2 CTSB# RTSB# RIB# DSRB# IOR# CSA# 10 CSB# 11 NC 12 15 13 18 19 20 22 16 14 17 21 23 CTSB# 24 NC RXRDYB# DSRB# RTSB# XTAL2 CDB# XTAL1 IOW# IOR# RIB# GND 9 10
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DSA00210750 PC16550 ST16C2450 XR16L2750 TL16C752B 48TQFP XR16C2850

ssi 73M2550

Abstract: 12 13 14 15 16 17 RI# 18 INT XTAL1 XTAL2 GND IOW# IOR# 2 xr REV. 4.2.1 , xr AUGUST 2005 ST16C1550/51 2.97V TO 5.5V UART WITH 16-BYTE FIFO REV. 4.2.1 GENERAL , TX FIFO A2:A0 D7:D0 IOR# IOW # CS# Data Bus Interface UART Configuration Regs DTR#, RTS# M odem , xr REV. 4.2.1 NOTE: PINOUTS NOT TO SCALE. ACTUAL SIZE OF TQFP PACKAGE IS SMALLER THAN PLCC , 25 XTAL1 XTAL2 GND N.C. N.C. N.C. IOW# IOR# 28-PLCC PACKAGES 26 DSR# VCC
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ST16C155X ST16C550 AN-1450/AN-1550 ST16C1551CJ28-F PLCC28 ST16C1551CQ48-F

ST16C1550

Abstract: 16C1550 ST16C1550/51 xr 2.97V TO 5.5V UART WITH 16-BYTE FIFO AUGUST 2005 REV. 4.2.1 GENERAL , DIAGRAM 16 Byte TX FIFO A2:A0 Transm itter D7:D0 TX IOR# IOW # CS# INT Data Bus , www.exar.com xr ST16C1550/51 2.97V TO 5.5V UART WITH 16-BYTE FIFO REV. 4.2.1 FIGURE 2. ST16C1550 , . 21 RI# 19 GND 20 18 N.C. IOR# 17 IOW# 16 15 XTAL2 14 N.C. XTAL1 , 13 14 15 16 17 18 XTAL1 XTAL2 IOW# GND IOR# RI# INT
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16C1550

PC16552

Abstract: ST16C2552CJ44-F Sup V Pkgs Documents Datasheets Datasheet Version 4.2.1 October 2006 671.70 KB Application Notes 16/16 , 2006 REV. 4.2.1 GENERAL DESCRIPTION The ST16C2552 (2552) is a dual universal asynchronous receiver , external clock input A2:A0 D7:D0 IOR# IOW# CS# CHSEL INTA INTB TXRDYA# TXRDYB# MFA# (OP2A#, BAUDOUTA , 2.97V TO 5.5V DUAL UART WITH 16-BYTE FIFO FIGURE 2. PIN OUT ASSIGNMENT REV. 4.2.1 TXRDYA# DSRA , 16 INTB 17 18 MFB# 19 IOW# 20 RESET 21 GND 22 RTSB# 23 IOR# 24 RXB 25 TXB 26 DTRB# 27 CTSB# 28 30
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PC16552 ST16C2552CJ44-F marking AFR XR16L2752 XR16C2852

ST16C2552

Abstract: 16-BYTE ST16C2552 2.97V TO 5.5V DUAL UART WITH 16-BYTE FIFO OCTOBER 2006 REV. 4.2.1 GENERAL , IOR# IOW# CS# CHSEL INTA INTB TXRDYA# TXRDYB# MFA# (OP2A#, BAUDOUTA#, or RXRDYA#) MFB , 5.5V DUAL UART WITH 16-BYTE FIFO REV. 4.2.1 D4 D3 D2 D1 D0 TXRDYA# VCC RIA , # CTSB# 28 DTRB# 27 TXB 26 RXB 25 IOR# 24 RTSB# 23 GND 22 RESET 21 CS# IOW# 20 , -BYTE FIFO REV. 4.2.1 PIN DESCRIPTIONS Pin Description NAME 44-PLCC PIN # TYPE DESCRIPTION
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ST16C2552CJ44 ST16C2552IJ44

STK 411 230 E

Abstract: A5005 PM+ . 31 4.2.1 . 31 4.2.2 [V850] . 32 4.3 PM+ SM+ . 33 4.3.1 . 33 4.4 . 34 , . 59 5.8.1 . 60 5.8.2 IOR/SFR . 61 5.8.3 I/O . 61 5.9 . 62 5.9.1 . 63 5.9.2 , . 207 . 208 . 209 DMM . 210 . 212 . 215 IOR/SFR . 216 IOR/SFR . 220 I/O , C . 417 D . 420 D.1 . 420 D.2 . 421 D.3 . 422 E . 446 U17662JJ1V0UM 13 , . 57 DMM 58 . 58 . . 60 IOR/SFR . 61 I/O . 61 63 . . 65 . 70
NEC
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CC78K0 STK 411 230 E A5005 e10501 CC78K0S RA78K0 78K0S U17662JJ1V0UM001 M8E02 V85078K078K0S U17201J

v8507

Abstract: e10501 PM+ . 32 4.2.1 . 32 4.2.2 [V850] . 33 4.3 PM+ SM+ . 34 4.3.1 . 34 4.4 . 35 , . 56 5.8.2 IOR/SFR . 57 5.8.3 I/O . 57 5.9 . 58 5.9.1 . 58 5.9.2 Run-Break . 58 , 205 . 207 DMM . 208 . 210 . 213 IOR/SFR . 215 IOR/SFR . 219 I/O . 222 , . 416 register . 417 reset . 418 run . 419 step . 420 stop . 421 upload . 422 , 50 . . 51 . 52 . 52 . 53 . 54 DMM 55 . . 56 IOR/SFR . 57 I/O
NEC
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RA78K0S v8507 tip f0401 F101B e10704 SFR 252 diode V85078K0 U17246JJ2V0UM002 U17246JJ2V0UM U17200J U17200E U17199J U17199E
Abstract: 4855452 OOS^SIO S34 International IOR Rectifier IRF2807S/L Electrical Characteristics @ Tj = , 5 4 5 2 0G 2R511 470 International IOR Rectifier IRF2807S/L VDS, Drain-to-Source Voltage , 002^513 243 â  1000 International IOR Rectifier * â D in Current (A) D ra IRF2807S/L , , Junction-to-Case 4 0 5 5 4 5 2 GG2cl S m 1ÛT International IOR Rectifier IRF2807S/L D R IV E R ,   MflSSMSa GGSTSI S Fig 13b. Gate Charge Test Circuit 01b â  International IOR Rectifier -
OCR Scan
IRF2807S IRF2807L EIA-418
Abstract: °C/W 9/22/97 4055455 â¡â¡2C 1S40 271 IRLZ24NS/L International IOR Rectifier , ) International IOR Rectifier VDS , Drain-to-Source Voltage (V) Fig 2. Typical Output Characteristics , . Temperature IRLZ24NS/L C, Capacitance (pF) International IOR Rectifier 0 4 V DS , , Junction-to-Case 4Ã" 554 52 002^544 ^17 IRLZ24NS/L International IOR Rectifier L Fig 12a , IRLZ24NS/L International IOR Rectifier D2Pak Package Outline 10.54 (.415) 10.29 (.405) 4.69 -
OCR Scan
1358D IRLZ24NS IRLZ24NL

N82593SX

Abstract: i386SL DRQ5930 * !DRQ2 + DRQ5930 * DRQ6 * !(DRQ2 * (!IOR + !iSW) 4.2.1 82593 I/O READ ACCESS Figure 4 shows , verview .1-359 4.2 ISA Bus In terface. 1-360 4.2.1 82593 I/O Read , 7 for low PCB space and additional power saving. This is discussed in detail in Section 4.2.1. The , additional delay when the P L D resumes from standby mode.) M inimum delay from SA bus valid to IOR is M inimum delay from IOR to R D 593 is Once the 82593 is configured, the application can as semble the
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N82593SX i386SL Aromat relay Intel 82593 N82593 Intel 82593 1991 1N4001 MMAD1107 AQV251A 74FCT245 82S123 N85C224
Abstract: ) 9 .3 8 (.3 6 9 ) ! 1 0.69 ( .421) 1 0 .3 9 ( 409) 1 6.0 2 (.631) IS .7 3 (.619) U , -1 Dimensions in millimeters and (inches) 8/29/97 4Ã"S5452 GGSHSbS TT*? International IOR Rectifier , Fig. 5 International IOR Rectifier 15CLQ100 - 0.0001 0 20 40 60 , ) Fig.5 - Max. Thermal Impedance ZlhJC characteristics (Per Leg) International IOR Rectifier WORLD -
OCR Scan
MIL-PRF-19500 55M52 15CLQ10
Abstract: 10.69 (-421) 10.39 (.409) I EE! I 0 .7 6 (.0 30 ) MIN. r 0 .5 0 (.020) 0 .2 6 (.0 1 , millimeters and (inches) 9/22/97 4 S 5 S 4 5 2 DD2T273 T7S International IOR Rectifier 60LQ045 , together 4Ã"554S2 0G2TS74 TGI See Fig. 4 International IOR Rectifier 60LQ045 Reverse , DQ2C 1275 64Ã International 60LQ045 IOR Rectifier 300 D = 0.08 D = 0.17 D = 0.25 D = -
OCR Scan

HC4066

Abstract: MSM5210 D14 SIOCK D15 ADSD WR RD CH D/C IOW IOR MID FUL EMP RESET BUSY CS No.NCNone Conect 6/10 6 , D14 SIOCK D15 ADSD OWR ORD CH ODC IOW IOR MID FUL EMP RESET BUSY CS DREQL DACKL 2 31 3 28 4 25 23 26 , MIDMC FULLMC WE OE IWR IRD IDC EMP MID FUL OWR ORD ODC 9 8 100k 10 IOW IOR MIN 52 51 38 39 41 42 35 36 37 51 44 43 40 34 50 45 IOW IOR WR RD D/C BUSY EMP MID FUL DREQL DASD SIOCK CS CH DACKL ADSD , 2017001 0762 222600 9200981 1 5 2 0 5410042 421 06 2261325 7300013 1 5 1
OKI Electric Industry
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C1157 HC4066 MSM5210 IOR 421 mic 342 27C4000 J2D010218Z5 MSM9841 MSM9841FPGA HC244 56PIN

stk 413 430 ic

Abstract: e10501 7.102 8.380 A.421 B.429 C.434 D.437 E.473 U16906JJ1V0UM 3 , . 25 4 PM plus . 26 4.1 . 27 4.2 PM plus . 27 4.2.1 . 27 4.2.2 . 28 4.3 PM , wish . 416 xcoverage . 417 xtime . 418 xtrace . 419 8.12 420 . A . 421 A.1 . 421 A.2 . 421 A.3 . 421 A.4 . 421 List . 422 Grep . 423 RRM . 424 Hook . , -1 B-2 B-3 B-4 B-5 B-6 C-1 D-1 18 Tcl . 382 ID . 384 . 421 . 429 . 429
NEC
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stk 413 430 ic IC stk 412 - 410 ic stk 442 130 tektronix 213 dmm ic stk 412 -420 IC stk 412 410 U16906JJ1V0UM001 U11595J U11595E U14487J U14487E IE-703003-MC-EM1V853

765 fdc

Abstract: nec 765 fdc -bit storage cell via the internal bus. It gets the IOR and IOW signals from the WD76C10, and with the , 30 wd 15 dirc 17 ided7 43 ra8 56 we 14 dma 8 idx 33 ra9 55 wp 31 dph 52 ior 48 ra10 54 dpl 53 , fclk2 27 m03 48 ior 69 rtcirq 7 rdd 28 hdl 49 iow 70 tc 8 dma 29 rwc 50 csen 71 prdy 9 firq 30 pwrdn , . IDED7 is an input, passing data from the IDE drive to DB7 of the Host data bus whenever an IOR of the IDE drive interface is detected, except when reading from address 3F7H. During an IOR of 3F7H, the
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OCR Scan
WD76C20 765 fdc nec 765 fdc NEC 765A diagram baling machine FLOPPY STEPPER MOTOR WD7600 8042CS

diode SFR-136

Abstract: SFR 136 PM+ . 31 4.2.1 . 31 4.2.2 [V850] . 32 4.3 PM+ SM+ . 33 4.3.1 . 33 4.4 . 34 , . 59 5.8.1 . 60 5.8.2 IOR/SFR . 61 5.8.3 I/O . 61 5.9 . 62 5.9.1 . 63 5.9.2 , . 211 . 212 . 213 DMM . 214 . 217 . 220 IOR/SFR . 221 IOR/SFR . 225 I/O , . 58 . . 60 IOR/SFR . 61 I/O . 61 63 . . 65 . 70 . 71 . 74 , DMM IOR/SFR 214 . . 217 . 220 IOR [V850] . 221 SFR [78K] . 222 IOR/SFR . 225
NEC
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CC78K0R diode SFR-136 SFR 136 213-DMM STK 415 90 7 segment E10501 led 7 segment 5161 78K0R U18010JJ2V0UM002 U18010JJ2V0UM V85078K0R78K078K0S U17838J

NEC 765A

Abstract: circuit diagram laptop motherboard -bit storage cell via the internal bus. It gets the IOR and IOW signals from 765A Core - The core of the , NAME PIN DS2 DS3 EMS FIRQ FCLK1/FX1 FCLK2 FX1 FX1/FCLK1 HDL HS IDEDENH IDEDENL IDED7 IDX IOR IOW , VSS DACK IOR IOW CSEN DACKEN DPH DPL RA10 RA9 RA8 RESET RCLR BALE RTCX RTCX VBAT MX14 PIN 64 65 66 67 , , passing data from the IDE drive to DB7 of the Host data bus when ever an IOR of the IDE drive interface is detected, except when reading from address 3F7H. During an IOR of 3F7H, the floppy DCHG status is output on
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OCR Scan
circuit diagram laptop motherboard plcc ide controller MC146818A D76C20 D76C2
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