NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
| Catalog Datasheet Results | Type | Document Tags |
| Abstract: L303A 5 4 3 2 1 Power & Config D FPGA_CFG D FPGA_CFG CONFIG[9.0] CONFIG[9.0] EXT_RESET# EXT_RESET# RESET#[1.0] Reference ID: 100 RESET#[1.0] RESET#1 #2 Lime Evaluation Board Revision: PA8 EXT_RESET# RESET#1 C RESET#[1.0] FPGA_CFG CONFIG[9.0] RESET#1 Video Input VO0_SYNC[4.0] VI_656_CLK VI_656_D[7.0] I2C[1.0] I2C[1.0] VI_656_CLK #3 A +-#1 Lime Eval Top ¦ +-#2 Power +-#3 Video Inpu ... | Original |
11 pages, |
XCF02 DD30 ev C703 C729 C734 FUJITSU L101 u12 c515 RN612 RN607 FTSH-108-01-L sil 164 transistor C730 PanelLink Transmitter sil164 sil-164 transistor C734 datasheet abstract |
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| Abstract: ATF280F ATF280F Features · SRAM based FPGA designed for Space use · · · · · · · · · · · · · · ·  280K equivalent ASIC gates  14 400 Cells ( two 3-input LUT or one 4-input LUT, one DFF)  Unlimited reprogrammability  SEE hardened (Configuration RAM, FreeRAMTM, DFF, JTAG, I/O buffers)  RHBD no need for mitigation technics during design FreeRAMTM:  115200 Bits of Distributed RAM  32x4 RAM blocks organization  Independent of Logic Cells  Single/Dual Port c ... | Original |
56 pages, |
U1 V1 and W1 is delta connections 32X4 ATF280F ATF280F abstract |
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| Abstract: ATF280FFeatures · SRAM based FPGA designed for Space use · · · · · · · · · · · · · · ·  280K equivalent ASIC gates  14 400 Cells ( two 3-input LUT or one 4-input LUT, one DFF)  Unlimited reprogrammability  SEE hardened (Configuration RAM, FreeRAMTM, DFF, JTAG, I/O buffers)  RHBD no need for mitigation technics during design FreeRAMTM:  115200 Bits of Distributed RAM  32x4 RAM blocks organization  Independent of Logic Cells  Single/Dual Port ca ... | Original |
57 pages, |
atmel 2816 memory 32X4 ATF280F ATF280 datasheet abstract |
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| Abstract: Lime CREMSON-STARTERKITLIME Rev. 1.03 Feb 2007 1.03 Lime Evaluation Board Revision 1.03 © 2007 Fujitsu Microelectronics Europe Page 1 MB86276 MB86276 Evaluation Board Manual Warranty and Disclaimer To the maximum extent permitted by applicable law, Fujitsu Microelectronics Europe GmbH restricts its warranties and its liability for Lime Evaluation Board and all its deliverables (e.g. software include or header files, application examples, target boards, evaluation boards, engin ... | Original |
29 pages, |
a20 c739 s m r707 u c756 transistor C618 X602 SiI164CT64 sg series MB86276 r707 FUJITSU L101 VC2 220r RN-400 SAA7113 Application notes SAA7113 datasheet abstract |
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| Abstract: ATF280F ATF280F Rad-Hard Reprogrammable FPGA DATASHEET Features · SRAM-based FPGA designed for Space use · · · · · 280K equivalent ASIC gates 14,400 cells ( two 3-input LUT or one 4-input LUT, one DFF) Unlimited reprogrammability SEE-hardened (Configuration RAM, FreeRAMTM, DFF, JTAG, I/O buffers) RHBD need for mitigation techniques during design 115,200 bits of distributed RAM Organized in 32x4 blocks of RAM Independent of Logic Cells Single/Dual port capability · FreeRAMTM · · · · ... | Original |
107 pages, |
LGA rework ATF280 MQFP-256 ATF280F ATF280F abstract |
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| Abstract: PM5382 PM5382 Â S/UNI 16X155 16X155 PRELIMINARY REFERENCE DESIGN PMC-2000506 PMC-2000506 ISSUE 1 S/UNI-16X155 S/UNI-16X155 REFERENCE DESIGN PM5382 PM5382 S/UNI-16X155 S/UNI-16X155 SATURN USER NETWORK INTERFACE (16X155 16X155) REFERENCE DESIGN PRELIMINARY PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE PM5382 PM5382 Â S/UNI 16X155 16X155 PRELIMINARY REFERENCE DESIGN PMC-2000506 PMC-2000506 ISSUE 1 S/UNI-16X155 S/UNI-16X155 REFERENCE DESIGN PUBLIC REVISION HISTORY Issue No. Issue Date Details of Change 1 ... | Original |
107 pages, |
lt1117-adj PM5382 powerblock dd SMD CAPACITOR L27 PLX PCI9054 603-82 f XC1702L sb6 sot23 plx 9054 15D10 stpa smd datasheet smd transistor 9f8 sot223 transistor p38 PMC-2000506 PMC-2000506 PM5382 PMC-2000506 abstract |
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| Abstract: ATF697FF ATF697FF Rad- hard 32 bit SPARC V8 Reconfigurable Processor DATASHEET Features · SPARC V8 High Performance Low-power 32-bit processor core · AT697F AT697F Sparc v8 processor · LEON2-FT 1.0.9.16.1 compliant · 8 Register Windows · Advanced Architecture 5 Stage Pipeline 32 kbyte 4-way associative instruction cache 16 kbyte 2-way associative data cache · · Integrated 32/64-bit IEEE 754 Floating-point Unit Reconfigurable Unit · · · · · · · ATF280F ATF280F SRAM FPGA 280K equivalent ASIC gates 1 ... | Original |
198 pages, |
AT697F PCI tag 87 ATF697FF ATF697FF abstract |
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| Abstract: (external clock j- SET D6(MSD) D5 D4 DS DZ DI(LSD) D T^l X ^ io5110- n^T^T^T HDC ... | OCR Scan |
14 pages, |
TC5072P 6-digit counter 6-digit counter dip TC4050BP TC5070 TC5071P 1S1588 TC5070P comprator 6-Digit BCD Counter segment TC5070P/TC5071P/TC5072P TC5072P abstract |
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| Abstract: PCA9556 PCA9556 Philips Configuration System Management ICs Octal SMBus Registered Interface Part Type Description The PCA9556 PCA9556 is an octal SMBus registered interface for parallel I/O expansion or collection through I2C or SMBus. The PCA9556 PCA9556 has four SMBus registers to facilitate its BIOS implementation. The PCA9556 PCA9556 has its own reset pin so that its I/O can be reset independently of an I/O controller's general purpose I/O (GPIO). This is useful for applications in which only a subset of th ... | Original |
2 pages, |
smbus PCA9556 motherboard diagnostic card laptop bios 8 pin laptop power motherboard ic laptop motherboard PCA9556 abstract |
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| Abstract: 5 4 3 2 D C A THIS DRAWING IS UNPUBLISHED. RELEASED FOR PUBLICATION COPYRIGHT - BY PLCO ELECTRONICS CORPORATION. ALL INTERNATIONAL RIGHTS RESERVED. GP 00 REVISIONS LTR DESCRIPTION REVISED PER ECO- -004952 DATE 9JUN2008 9JUN2008 DWN APVD Z M R S LB 2.54 [. 1 OO] 0.74 [.029] - REF - REF 2.54 [. 1 OO] TYP 2.69 [. 1 O 6] DIA 2 PLC fo| 00.08 [.003 1 7.65 [.695] 2 PLC 4. 4 5.84 [.230] 2 PLC 0.89 ±0.08 [.Q55+.QQ5] DIA TYP â- fol 00.08 r.003" EJECTION LATCHES OMITTED IN THIS VIEW EOR CLARITY 5\PC RECOMMENDED BO ... | OCR Scan |
1 pages, |
datasheet abstract |
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| Abstract: W1MA MKS 4 Capacitors for stringent requirements with assessed quality Metallized polyester capacitors â- CECC approval Certificate No. 30401-030 â- in accordance with DIN 44122 â- In plastic cases with good humidity protection â- Available taped and reeled (up to and including case size 15 X 26 X 31.5/PCM 27.5 mm) Technical Data Dielectric: Polyethylene terephthalate film. Capacitor electrodes: Vacuum deposited aluminium. Encapsulation: Flame-retardent plastic case, UL 94 V-O, with epox ... | OCR Scan |
2 pages, |
wima 0.01 MF 63 V CAPACITOR 10X10 W1MA datasheet abstract |
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| Abstract: TC55V4000ST-70 TC55V4000ST-70,-85 TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS 524,288-WORD 288-WORD BY 8-BIT STATIC RAM DESCRIPTION The TC55V4000ST TC55V4000ST is a 4,194,304-bit static random access memory (SRAM) organized as 524,288 words by 8 bits. Fabricated using Toshiba's CMOS Silicon gate process technology, this device operates from a single 2.3 to 3.6 V power supply. Advanced circuit technology provides both high speed and low power at an operating current of 3 mA/MHz and a minimum cycle time of 70 ns. I ... | Original |
10 pages, |
TC55V4000ST-70 288-WORD TC55V4000ST TC55V4000ST-70 abstract |
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| Abstract: AT&T MELEC (I C) 2SE D â- 005002b 0002tafl 3 â- SPEECH NETWORK IC_LB1071AC LB1071AC PRELIMINARY Description T-7S-Q7-/5 The LB1071AC LB1071AC Speech Network Integrated Circuit provides the 2- to 4-wire interface between a telephone loop and a telephone handset. The integrated circuit furnishes ac and dc loop termination for the off-hook state and transmits/ receives voice signals to or from the central office. The LB1071AC LB1071AC device is available in a 16-pin plastic DIP. Features â- Capable of speech transmission ... | OCR Scan |
16 pages, |
SPEECH NETWORK WITH DIALER INTERFACE MK5373N LB1071AC LB1068AW lb1068 2N2907A plastic 2N2907A Mostek tone LB1071AC abstract |
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| Abstract: H EE GEN FR ALO CAT28LV65 CAT28LV65 64K-Bit CMOS PARALLEL EEPROM LE A D F R E ETM FEATURES s 3.0V to 3.6V supply s CMOS and TTL compatible I/O s Read access times: s Automatic page write operation:  1 to 32 bytes in 5ms  Page load timer  150/200/250ns s Low power CMOS dissipation: s End of write detection:  Active: 8 mA max.  Standby: 100 uA max.  Toggle bit  DATA polling  RDY/BUSY BUSY s Simple write operation:  On-chip address and data la ... | Original |
12 pages, |
CAT28LV65 d 1555 CAT28LV65 abstract |
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| Abstract: Crosspoint Switch Implementation Using the ispLSI ® 1032 This application note describes a crosspoint switch that will allow any of four input busses to be connected to any or all of the four output busses. The input and output busses are eight bits wide. Wider busses can be accommodated by paralleling multiple ispLSI 1032 devices. By pairing the input and output busses, the design can be changed to a two-by-two-by-sixteen crosspoint switch. The actual implementation of the switch con ... | Original |
8 pages, |
datasheet abstract |
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| Abstract: CY7C128A CY7C128A 2K x 8 Static RAM Features Functional Description D The CY7C128A CY7C128A is a highperformance CMOS static RAM organized as 2048 words by 8 bits. Easy memory expansion is provided by an active LOW chip enable (CE), and active LOW output enable (OE) and threestate drivers. The CY7C128A CY7C128A has an automatic powerdown feature, re ducing the power consumption by 83% when deselected. Writing to the device is accomplished when the chip enable (CE) and write enable (WE) inputs are ... | Original |
9 pages, |
CY7C128A datasheet abstract |
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| Abstract: Crosspoint Switch Implementation Using the ispLSI ® 1032E 1032E This application note describes a crosspoint switch that will allow any of four input busses to be connected to any or all of the four output busses. The input and output busses are eight bits wide. Wider busses can be accommodated by paralleling multiple ispLSI 1032E 1032E devices. By pairing the input and output busses, the design can be changed to a two-by-two-by-sixteen crosspoint switch. The actual implementation of the switch c ... | Original |
8 pages, |
1032E 1032E abstract |
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| ; IO506 IO506 IO506 IO506: inout bit; IO507 IO507 IO507 IO507: inout bit; IO508 IO508 IO508 IO508: inout bit; IO510 IO510 IO510 IO510: inout bit; IO511: inout bit; IO512 IO512 IO512 IO512 ," & "IO510 IO510 IO510 IO510:B4," & "IO511:D7," & "IO512 IO512 IO512 IO512:C6," & "IO513 IO513 IO513 IO513:E8," & "IO514 IO514 IO514 IO514:B5," & "IO515 IO515 IO515 IO515:A5," & "IO518 IO518 IO518 IO518:D8 , 1, PULL1)," & " 22 (BC_1, IO510 IO510 IO510 IO510, input, X)," & " 23 (BC_1, *, controlr, 1)," & " 24 (BC_1, IO511, output3, X, 23, 1, PULL1)," & " 25 (BC_1, IO511, input, X)," & " 26 (BC_1, *, controlr, 1 www.datasheetarchive.com/download/68606710-987023ZC/wcd02dff.z |
Xilinx | 13/07/1998 | 34.3 Kb | Z | wcd02dff.z |
| ; IO506 IO506 IO506 IO506: inout bit; IO507 IO507 IO507 IO507: inout bit; IO508 IO508 IO508 IO508: inout bit; IO510 IO510 IO510 IO510: inout bit; IO511: inout bit; IO512 IO512 IO512 IO512 :BB2," & "IO506 IO506 IO506 IO506:AY4," & "IO507 IO507 IO507 IO507:AR7," & "IO508 IO508 IO508 IO508:AP8," & "IO510 IO510 IO510 IO510:AT6," & "IO511:AY2," & "IO512 IO512 IO512 IO512:AU5 , input, X)," & " 23 (BC_1, *, controlr, 1)," & " 24 (BC_1, IO511, output3, X, 23, 1, PULL1)," & " 25 (BC_1, IO511, input, X)," & " 26 (BC_1, *, controlr, 1)," & " 27 (BC_1, IO512 IO512 IO512 IO512, output3, X, 26 www.datasheetarchive.com/download/68606710-987023ZC/wcd02dff.z |
Xilinx | 13/07/1998 | 34.3 Kb | Z | wcd02dff.z |
| ; IO506 IO506 IO506 IO506: inout bit; IO507 IO507 IO507 IO507: inout bit; IO508 IO508 IO508 IO508: inout bit; IO510 IO510 IO510 IO510: inout bit; IO511: inout bit; IO512 IO512 IO512 IO512 :BB2," & "IO506 IO506 IO506 IO506:AY4," & "IO507 IO507 IO507 IO507:AR7," & "IO508 IO508 IO508 IO508:AP8," & "IO510 IO510 IO510 IO510:AT6," & "IO511:AY2," & "IO512 IO512 IO512 IO512:AU5 , input, X)," & " 23 (BC_1, *, controlr, 1)," & " 24 (BC_1, IO511, output3, X, 23, 1, PULL1)," & " 25 (BC_1, IO511, input, X)," & " 26 (BC_1, *, controlr, 1)," & " 27 (BC_1, IO512 IO512 IO512 IO512, output3, X, 26 www.datasheetarchive.com/download/48084229-987024ZC/wcd02e00.zip (xc4085xl_pg559.bsd) |
Xilinx | 13/07/1998 | 29.13 Kb | ZIP | wcd02e00.zip |
| ; IO506 IO506 IO506 IO506: inout bit; IO507 IO507 IO507 IO507: inout bit; IO508 IO508 IO508 IO508: inout bit; IO510 IO510 IO510 IO510: inout bit; IO511: inout bit; IO512 IO512 IO512 IO512 ," & "IO510 IO510 IO510 IO510:B4," & "IO511:D7," & "IO512 IO512 IO512 IO512:C6," & "IO513 IO513 IO513 IO513:E8," & "IO514 IO514 IO514 IO514:B5," & "IO515 IO515 IO515 IO515:A5," & "IO518 IO518 IO518 IO518:D8 , 1, PULL1)," & " 22 (BC_1, IO510 IO510 IO510 IO510, input, X)," & " 23 (BC_1, *, controlr, 1)," & " 24 (BC_1, IO511, output3, X, 23, 1, PULL1)," & " 25 (BC_1, IO511, input, X)," & " 26 (BC_1, *, controlr, 1 www.datasheetarchive.com/download/48084229-987024ZC/wcd02e00.zip (xc4085xl_bg560.bsd) |
Xilinx | 13/07/1998 | 29.13 Kb | ZIP | wcd02e00.zip |
| ; IO506 IO506 IO506 IO506: inout bit; IO507 IO507 IO507 IO507: inout bit; IO508 IO508 IO508 IO508: inout bit; IO510 IO510 IO510 IO510: inout bit; IO511: inout bit; IO512 IO512 IO512 IO512 ," & "IO510 IO510 IO510 IO510:B4," & "IO511:D7," & "IO512 IO512 IO512 IO512:C6," & "IO513 IO513 IO513 IO513:E8," & "IO514 IO514 IO514 IO514:B5," & "IO515 IO515 IO515 IO515:A5," & "IO518 IO518 IO518 IO518:D8 , 1, PULL1)," & " 22 (BC_1, IO510 IO510 IO510 IO510, input, X)," & " 23 (BC_1, *, controlr, 1)," & " 24 (BC_1, IO511, output3, X, 23, 1, PULL1)," & " 25 (BC_1, IO511, input, X)," & " 26 (BC_1, *, controlr, 1 www.datasheetarchive.com/download/80319827-987372ZC/wcd03012.zip (xc4085xl_bg560.bsd) |
Xilinx | 12/02/1999 | 42.05 Kb | ZIP | wcd03012.zip |
| ; IO505 IO505 IO505 IO505: inout bit; IO506 IO506 IO506 IO506: inout bit; IO507 IO507 IO507 IO507: inout bit; IO508 IO508 IO508 IO508: inout bit; IO510 IO510 IO510 IO510: inout bit; IO511 ," & "IO505 IO505 IO505 IO505:B4," & "IO506 IO506 IO506 IO506:C5," & "IO507 IO507 IO507 IO507:A4," & "IO508 IO508 IO508 IO508:D6," & "IO510 IO510 IO510 IO510:B5," & "IO511:C6," & "IO512 IO512 IO512 IO512:A5 , 1, PULL1)," & " 22 (BC_1, IO510 IO510 IO510 IO510, input, X)," & " 23 (BC_1, *, controlr, 1)," & " 24 (BC_1, IO511, output3, X, 23, 1, PULL1)," & " 25 (BC_1, IO511, input, X)," & " 26 (BC_1, *, controlr, 1 www.datasheetarchive.com/download/80319827-987372ZC/wcd03012.zip (xc4085xl_bg432.bsd) |
Xilinx | 12/02/1999 | 42.05 Kb | ZIP | wcd03012.zip |
| ; IO506 IO506 IO506 IO506: inout bit; IO507 IO507 IO507 IO507: inout bit; IO508 IO508 IO508 IO508: inout bit; IO510 IO510 IO510 IO510: inout bit; IO511: inout bit; IO512 IO512 IO512 IO512 :BB2," & "IO506 IO506 IO506 IO506:AY4," & "IO507 IO507 IO507 IO507:AR7," & "IO508 IO508 IO508 IO508:AP8," & "IO510 IO510 IO510 IO510:AT6," & "IO511:AY2," & "IO512 IO512 IO512 IO512:AU5 , input, X)," & " 23 (BC_1, *, controlr, 1)," & " 24 (BC_1, IO511, output3, X, 23, 1, PULL1)," & " 25 (BC_1, IO511, input, X)," & " 26 (BC_1, *, controlr, 1)," & " 27 (BC_1, IO512 IO512 IO512 IO512, output3, X, 26 www.datasheetarchive.com/download/80319827-987372ZC/wcd03012.zip (xc4085xl_pg559.bsd) |
Xilinx | 12/02/1999 | 42.05 Kb | ZIP | wcd03012.zip |
| ; IO507 IO507 IO507 IO507: inout bit; IO508 IO508 IO508 IO508: inout bit; IO509 IO509 IO509 IO509: inout bit; IO510 IO510 IO510 IO510: inout bit; IO511: inout bit; IO516 IO516 IO516 IO516 505:AV36," & "IO506 IO506 IO506 IO506:BB36," & "IO507 IO507 IO507 IO507:AY36," & "IO508 IO508 IO508 IO508:BC35," & "IO509 IO509 IO509 IO509:AW35," & "IO510 IO510 IO510 IO510:AU33," & "IO511:AT30," & "IO516 IO516 IO516 IO516:AV32," & "IO517 IO517 IO517 IO517:AU31," & "IO518 IO518 IO518 IO518:AW33," & "IO519 IO519 IO519 IO519:BB34," & "IO520 IO520 IO520 IO520:AY34," & "IO www.datasheetarchive.com/download/20918364-986996ZC/wcd02de4.zip (xc40150xv_pg559.bsd) |
Xilinx | 13/07/1998 | 49.29 Kb | ZIP | wcd02de4.zip |
| ; IO506 IO506 IO506 IO506: inout bit; IO507 IO507 IO507 IO507: inout bit; IO508 IO508 IO508 IO508: inout bit; IO509 IO509 IO509 IO509: inout bit; IO510 IO510 IO510 IO510: inout bit; IO511 :AF4," & "IO506 IO506 IO506 IO506:AG3," & "IO507 IO507 IO507 IO507:AE5," & "IO508 IO508 IO508 IO508:AH1," & "IO509 IO509 IO509 IO509:AF3," & "IO510 IO510 IO510 IO510:AE4," & "IO511:AG2 www.datasheetarchive.com/download/20918364-986996ZC/wcd02de4.zip (xc40150xv_bg560.bsd) |
Xilinx | 13/07/1998 | 49.29 Kb | ZIP | wcd02de4.zip |
| ; IO502 IO502 IO502 IO502: inout bit; IO507 IO507 IO507 IO507: inout bit; IO508 IO508 IO508 IO508: inout bit; IO511: inout bit; IO512 IO512 IO512 IO512: inout bit; IO513 IO513 IO513 IO513 :Y2," & "IO511:Y4," & "IO512 IO512 IO512 IO512:Y3," & "IO513 IO513 IO513 IO513:Y1," & "IO514 IO514 IO514 IO514:W1," & "IO520 IO520 IO520 IO520:W4," & "IO521 IO521 IO521 IO521:W3 www.datasheetarchive.com/download/13915944-986987ZC/wcd02ddb.z |
Xilinx | 13/07/1998 | 52.16 Kb | Z | wcd02ddb.z |