MAX17030/MAX17036 MAX8791 MAX17036 MAX17030GTL MAX17036GTL MAX17030 - Datasheet Archive

 

KIT ATION EVALU BLE AVAILA 1/2/3-Phase Quick-PWM IMVP-6.5 VID Controllers High-Current Voltage-Positioned Step-Down Converters

 

19-4577; Rev 1; 8/09 KIT ATION EVALU BLE AVAILA 1/2/3-Phase Quick-PWM IMVP-6.5 VID Controllers High-Current Voltage-Positioned Step-Down Converters BST2 LX2 DH2 DL1 DH1 LX1 TOP VIEW BST1 3 to 4 Li+ Cells Battery to CPU Core Supply Converters Pin Configuration DL2 IMVP-6.5 SV and XE Core Power Supplies VRHOT Applications VDD The MAX17030/MAX17036 MAX17030/MAX17036 are 3/2-phase interleaved Quick-PWMTM step-down VID power-supply controllers for IMVP-6.5 notebook CPUs. Two integrated drivers and the option to drive a third phase using an external driver such as the MAX8791 MAX8791 allow for a flexible 3/2-phase configuration depending on the CPU being supported. True out-of-phase operation reduces input ripple-current requirements and output-voltage ripple while easing component selection and layout difficulties. The QuickPWM control provides instantaneous response to fast load-current steps. Active voltage positioning reduces power dissipation and bulk output capacitance requirements and allows ideal positioning compensation for tantalum, polymer, or ceramic bulk output capacitors. The MAX17030/MAX17036 MAX17030/MAX17036 are intended for bucking down the battery directly to create the core voltage. The single-stage conversion method allows this device to directly step down high-voltage batteries for the highest possible efficiency. A slew-rate controller allows controlled transitions between VID codes. A thermistor-based temperature sensor provides programmable thermal protection. An output current monitor provides an analog current output proportional to the sum of the inductor currents, which in steady state is the same as the current consumed by the CPU. Features o Triple/Dual-Phase Quick-PWM Controllers o 2 Internal Drivers + 1 External Driver o ±0.5% VOUT Accuracy Over Line, Load, and Temperature o 7-Bit IMVP-6.5 DAC o Dynamic Phase Selection Optimizes Active/Sleep Efficiency o Transient Phase Overlap Reduces Output Capacitance o Transient Suppression Feature (MAX17036 MAX17036 Only) o Integrated Boost Switches o Active Voltage Positioning with Adjustable Gain o Accurate Lossless Current Balance and Current Limit o Remote Output and Ground Sense o Adjustable Output Slew-Rate Control o Power-Good (IMVPOK), Clock Enable (CLKEN), and Thermal-Fault (VRHOT) Outputs o IMVP-6.5 Power Sequencing and Timing Compliant o Output Current Monitor (IMON) o Drives Large Synchronous Rectifier FETs o 7V to 26V Battery Input Range o Adjustable Switching Frequency (600kHz max) o Undervoltage, Overvoltage, and Thermal-Fault Protection 30 29 28 27 26 25 24 23 22 21 Notebooks/Desktops/Servers PGD_IN 31 Ordering Information PART MAX17030GTL MAX17030GTL+ MAX17036GTL MAX17036GTL+ 20 PWM3 D0 32 19 DRSKP D1 33 18 PWRGD TEMP RANGE PIN-PACKAGE D2 34 17 CLKEN 40 TQFN-EP* D3 35 40 TQFN-EP* D4 36 -40°C to +105°C -40°C to +105°C 16 TON MAX17030 MAX17030 MAX17036 MAX17036 15 PSI D5 37 D6 38 13 SHDN CSP1 39 +Denotes a lead-free(Pb)/RoHS-compliant package. *EP = Exposed pad. 14 DPRSLPVR 12 CSP2 11 CSN2 Quick-PWM is a trademark of Maxim Integrated Products, Inc. 5 6 7 8 9 10 VCC FB FBAC GNDS THRM 4 TIME 3 ILIM 2 IMON 1 CSN3 + CSP3 CSN1 40 THIN QFN 5mm x 5mm _ Maxim Integrated Products 1 For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com. MAX17030/MAX17036 MAX17030/MAX17036 General Description MAX17030/MAX17036 MAX17030/MAX17036 1/2/3-Phase Quick-PWM IMVP-6.5 VID Controllers ABSOLUTE MAXIMUM RATINGS (Note 1) VCC, VDD to GND .-0.3V to +6V D0­D6, PGD_IN, PSI, DPRSLPVR to GND .-0.3V to +6V CSP_, CSN_, THRM, ILIM to GND.-0.3V to +6V PWRGD, CLKEN, VR_HOT to GND.-0.3V to +6V FB, FBAC, IMON, TIME to GND .-0.3V to (VCC + 0.3V) SHDN to GND (Note 2).-0.3V to +30V TON to GND .-0.3V to +30V GNDS to GND .-0.3V to +0.3V DL1, DL2, PWM3, DRSKP to GND .-0.3V to (VDD + 0.3V) BST1, BST2 to GND .-0.3V to +36V BST1, BST2 to VDD .-0.3V to +30V LX1 to BST1.-6V to +0.3V LX2 to BST2.-6V to +0.3V DH1 to LX1 .-0.3V to (VBST1 + 0.3V) DH2 to LX2 .-0.3V to (VBST2 + 0.3V) Continuous Power Dissipation (40-pin, 5mm x 5mm TQFN) Up to +70°C .1778mW Derating above +70°C .22.2mW/°C Operating Temperature Range .-40°C to +105°C Junction Temperature .+150°C Storage Temperature Range .-65°C to +165°C Lead Temperature (soldering, 10s) .+300°C Note 1: Absolute Maximum Ratings valid using 20MHz bandwidth limit. Note 2: SHDN might be forced to 12V for the purpose of debugging prototype breadboards using the no-fault test mode. Internal BST switches are disabled as well. Use external BST diodes when SHDN is forced to 12V. Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (Circuit of Figure 1, VIN = 10V, VCC = VDD = V SHDN = VPGD_IN = V PSI = VILIM = 5V, VDPRSLPVR = VGNDS = 0, VCSP_ = VCSN_ = 1.0000V, FB = FBAC, RFBAC = 3.57k from FBAC to CSN_, [D6­D0] = [0101000]; TA = 0°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS PWM CONTROLLER VCC, VDD Input Voltage Range FB Output Voltage Accuracy Boot Voltage 4.5 5.5 7 26 DAC codes from 0.8125V to 1.5000V -0.5 +0.5 DAC codes from 0.3750V to 0.8000V -7 +7 DAC codes from 0 to 0.3625V -20 +20 VIN VFB Measured at FB with respect to GNDS; includes loadregulation error (Note 3) VBOOT 1.094 V -0.1 +0.1 A -200 TA = +25°C 1.106 +200 mV VCC = 4.5V to 5.5V, VIN = 4.5V to 26V FB Input Bias Current GNDS Input Range GNDS Gain A GNDS GNDS Input Bias Current IGNDS TIME Regulation Voltage VTIME VOUT/ VGNDS 1.100 0.1 0.97 TA = +25°C 1.00 1.985 (6.08mV/s nominal) % 2.000 1.03 V/V +0.5 -0.5 RTIME = 147k RTIME = 147k A 2.015 V -10 +10 RTIME = 35.7k (25mV/s nominal) to 178k (5mV/s nominal) -15 +15 Soft-start and soft-shutdown: RTIME = 35.7k (6.25mV/s nominal) to 178k (1.25mV/s nominal) 2 % mV Line Regulation Error TIME Slew-Rate Accuracy V -20 % _ +20 1/2/3-Phase Quick-PWM IMVP-6.5 VID Controllers (Circuit of Figure 1, VIN = 10V, VCC = VDD = V SHDN = VPGD_IN = V PSI = VILIM = 5V, VDPRSLPVR = VGNDS = 0, VCSP_ = VCSN_ = 1.0000V, FB = FBAC, RFBAC = 3.57k from FBAC to CSN_, [D6­D0] = [0101000]; TA = 0°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER On-Time Accuracy SYMBOL t ON CONDITIONS VIN = 10V, VFB = 1.0V, measured at DH1, DH2, and PWM3 (Note 4) MIN TYP MAX RTON = 96.75k (600kHz per phase), 167ns nominal -15 +15 RTON = 200k (300kHz per phase), 333ns nominal -10 +10 RTON = 303.25k (200kHz per phase), 500ns nominal -15 UNITS +15 % Minimum Off-Time t OFF(MIN) Measured at DH1, DH2, and PWM3 (Note 4) 300 375 ns TON Shutdown Input Current ITON,SDN SHDN = GND, VIN = 26V, VCC = VDD = 0 or 5V, TA = +25°C 0.01 0.1 A BIAS CURRENTS Quiescent Supply Current (VCC) ICC Measured at VCC, VDPRSLPVR = 5V, FB forced above the regulation point 3.5 7 mA Quiescent Supply Current (VDD) IDD Measured at VDD, VDPRSLPVR = 0, FB forced above the regulation point, TA = +25°C 0.02 1 A Shutdown Supply Current (VCC) ICC,SDN Measured at VCC, SHDN = GND, TA = +25°C 0.01 1 A Shutdown Supply Current (VDD) IDD,SDN Measured at VDD, SHDN = GND, TA = +25°C 0.01 1 A mV FAULT PROTECTION Output Overvoltage-Protection Threshold VOVP Skip mode after output reaches the regulation voltage or PWM mode; measured at FB with respect to the voltage target set by the VID code (see Table 4) 250 300 350 Soft-start, soft-shutdown, skip mode, and output have not reached the regulation voltage; measured at FB 1.45 1.50 1.55 Minimum OVP threshold; measured at FB 0.8 10 Output OvervoltagePropagation Delay t OVP FB forced 25mV above trip threshold Output UndervoltageProtection Threshold VUVP Measured at FB with respect to the voltage target set by the VID code (see Table 4) Output UndervoltagePropagation Delay tUVP FB forced 25mV below trip threshold CLKEN Startup Delay and Boot Time Period tBOOT V Measured from the time when FB reaches the boot target voltage (Note 3) -450 -400 s -350 10 20 60 mV s 100 s _ 3 MAX17030/MAX17036 MAX17030/MAX17036 ELECTRICAL CHARACTERISTICS (continued) MAX17030/MAX17036 MAX17030/MAX17036 1/2/3-Phase Quick-PWM IMVP-6.5 VID Controllers ELECTRICAL CHARACTERISTICS (continued) (Circuit of Figure 1, VIN = 10V, VCC = VDD = V SHDN = VPGD_IN = V PSI = VILIM = 5V, VDPRSLPVR = VGNDS = 0, VCSP_ = VCSN_ = 1.0000V, FB = FBAC, RFBAC = 3.57k from FBAC to CSN_, [D6­D0] = [0101000]; TA = 0°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 3 6.5 10 ms Lower threshold, falling edge (undervoltage) -350 -300 -250 Upper threshold, rising edge (overvoltage) +150 PWRGD Startup Delay Measured at startup from the time when CLKEN goes low CLKEN and PWRGD Threshold Measured at FB with respect to the voltage target set by the VID code (see Table 4), 20mV hysteresis (typ) +200 tBLANK 10 s Measured from the time when FB reaches the target voltage (Note 3) 20 s CLKEN, PWRGD Output Low Voltage Low state, I SINK = 3mA CLKEN, PWRGD Leakage Current High-Z state, pin forced to 5V, TA = +25°C CSN1 Pulldown Resistance in UVLO and Shutdown SHDN = GND, measured after softshutdown completed (DL = low) VCC Undervoltage-Lockout Threshold +250 FB forced 25mV outside the PWRGD trip thresholds CLKEN and PWRGD Delay CLKEN and PWRGD Transition Blanking Time (VID Transitions) mV VUVLO(VCC) Rising edge, 65mV typical hysteresis, controller disabled below this level 0.4 V 1 A 8 4.05 4.27 4.48 V 29 30 31 % THERMAL PROTECTION Measured at THRM with respect to VCC; falling edge, typical hysteresis = 75mV VRHOT Trip Threshold VRHOT Delay VRHOT Output On-Resistance t VRHOT THRM forced 25mV below the VRHOT trip threshold, falling edge 10 RON(VRHOT) Low state VRHOT Leakage Current 2 High-Z state, VRHOT forced to 5V, TA = +25°C THRM Input Leakage ITHRM VTHRM = 0 to 5V, TA = +25°C Thermal-Shutdown Threshold T SHDN s 8 1 Typical hysteresis = 15°C +0.1 -0.1 A A °C +160 VALLEY CURRENT LIMIT, DROOP, CURRENT BALANCE, AND CURRENT MONITOR Current-Limit Threshold Voltage (Negative) Accuracy Current-Limit Threshold Voltage (Zero Crossing) CSP_, CSN_ Common-Mode Input Range 4 VTIME - VILIM = 100mV VLIMIT VCSP_ - VCSN_ 7 10 13 VTIME - VILIM = 500mV 45 50 55 ILIM = VCC Current-Limit Threshold Voltage (Positive) 20 22.5 25 VLIMIT(NEG) VCSP_ - VCSN_, nominally -125% of VLIMIT VZX -4 VGND - VLX_, VDPRSLPVR = 5V +4 0 0 _ mV mV mV 2 V 1/2/3-Phase Quick-PWM IMVP-6.5 VID Controllers (Circuit of Figure 1, VIN = 10V, VCC = VDD = V SHDN = VPGD_IN = V PSI = VILIM = 5V, VDPRSLPVR = VGNDS = 0, VCSP_ = VCSN_ = 1.0000V, FB = FBAC, RFBAC = 3.57k from FBAC to CSN_, [D6­D0] = [0101000]; TA = 0°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER SYMBOL Phases 2, 3 Disable Threshold CSP_, CSN_ Input Current CONDITIONS Measured at CSP2, CSP3 MIN TYP MAX UNITS 3 VCC 1 VCC 0.4 V TA = +25°C -0.2 +0.2 A I ILIM ILIM Input Current ICSP, ICSN TA = +25°C -0.1 +0.1 A -0.5 +0.5 (1/N) x (VCSP_ VCSN_) at IFBAC = 0; TA = +25°C indicates summation over all power-up enabled phases from 1 to N, TA = 0°C to +85°C N=3 Droop Amplifier Offset mV/ phase -0.75 IFBAC/ [ (VCSP_ - VCSN_)]; indicates summation over all power-up enabled phases from 1 to N, N = 3, VFBAC = VCSN_ = 0.45V to 1.5V 393 Current-Monitor Offset (1/N) x (VCSP_ - VCSN_) at I IMON = 0, indicates summation over all power-up enabled phases from 1 to N, N = 3 -1.1 Current-Monitor Transconductance Gm(IMON) I IMON/ [ (VCSP_ - VCSN_)]; indicates summation over all power-up enabled phases from 1 to N, N = 3, VCSN_ = 0.45V to 1.5V 1.552 R ON(DH) BST_ - LX_ forced to 5V +0.75 Droop Amplifier Transconductance Gm(FBAC) 400 406 S +1 mV/ phase 1.6 1.648 mS High state (pullup) 0.9 2.5 Low state (pulldown) 0.7 2 High state (pullup) 0.7 2 Low state (pulldown) 0.25 0.7 GATE DRIVERS DH_ Gate-Driver On-Resistance DL_ Gate-Driver On-Resistance DH_ Gate-Driver Source Current DH_ Gate-Driver Sink Current DL_ Gate-Driver Source Current DL_ Gate-Driver Sink Current R ON(DL) DH_ forced to 2.5V, IDH(SOURCE) BST_ - LX_ forced to 5V 2.2 A DH_ forced to 2.5V, BST_ - LX_ forced to 5V 2.7 A IDH(SINK) IDL(SOURCE) DL_ forced to 2.5V Internal BST_ Switch On-Resistance 20 20 DH_ rising, CDH_ = 3nF R ON(BST) A 20 DH_ falling, CDH_ = 3nF DH_ Transition Time A 8 DL rising, CDL_ = 3nF DL_ Transition Time 2.7 DL_ forced to 2.5V DL_ falling, CDL_ = 3nF IDL(SINK) 20 IBST_ = 10mA 10 ns ns 20 _ 5 MAX17030/MAX17036 MAX17030/MAX17036 ELECTRICAL CHARACTERISTICS (continued) MAX17030/MAX17036 MAX17030/MAX17036 1/2/3-Phase Quick-PWM IMVP-6.5 VID Controllers ELECTRICAL CHARACTERISTICS (continued) (Circuit of Figure 1, VIN = 10V, VCC = VDD = V SHDN = VPGD_IN = V PSI = VILIM = 5V, VDPRSLPVR = VGNDS = 0, VCSP_ = VCSN_ = 1.0000V, FB = FBAC, RFBAC = 3.57k from FBAC to CSN_, [D6­D0] = [0101000]; TA = 0°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS PWM3, DRSKP OUTPUTS PWM3, DRSKP Output High Voltages I SOURCE = 3mA PWM3, DRSKP Output Low Voltages I SINK = 3mA VDD 0.4V V 0.4 V LOGIC AND I/O Logic-Input High Voltage VIH SHDN, PGD_IN Logic-Input Low Voltage VIL SHDN, PGD_IN Low-Voltage Logic-Input High Voltage VIHLV PSI, D0­D6, DPRSLPVR Low-Voltage Logic-Input Low Voltage VILLV PSI, D0­D6, DPRSLPVR 2.3 TA = +25°C; SHDN, DPRSLPVR, PGD_IN, PSI, D0­D6 = 0 or 5V Logic Input Current V 1.0 0.67 V V 0.33 +1 -1 V A ELECTRICAL CHARACTERISTICS (Circuit of Figure 1, VIN = 10V, VCC = VDD = V SHDN = VPGD_IN = V PSI = VILIM = 5V, VDPRSLPVR = VGNDS = 0, VCSP_ = VCSN_ = 1.0000V, FB = FBAC, RFBAC = 3.57k from FBAC to CSN_, [D6­D0] = [0101000]; TA = -40oC to +105°C, unless otherwise noted.) (Note 5) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS PWM CONTROLLER VCC, VDD Boot Voltage 5.5 7 26 DAC codes from 0.8125V to 1.5000V -0.75 +0.75 DAC codes from 0.3750V to 0.8000V -10 +10 DAC codes from 0 to 0.3625V -25 +25 1.085 1.115 V +200 mV 0.95 1.05 V/V 1.985 2.015 V -10 +10 RTIME = 35.7k (25mV/s nominal) to 178k (5mV/s nominal) -15 +15 Soft-start and soft-shutdown: RTIME = 35.7k (6.25mV/s nominal) to 178k (1.25mV/s nominal) FB Output-Voltage Accuracy 4.5 -200 Input Voltage Range -20 VIN VFB Measured at FB with respect to GNDS, includes loadregulation error (Note 3) VBOOT GNDS Input Range GNDS Gain A GNDS TIME Regulation Voltage VTIME VOUT/ VGNDS RTIME = 147k RTIME = 147k TIME Slew-Rate Accuracy 6 (6.08mV/s nominal) V % mV % _ +20 1/2/3-Phase Quick-PWM IMVP-6.5 VID Controllers (Circuit of Figure 1, VIN = 10V, VCC = VDD = V SHDN = VPGD_IN = V PSI = VILIM = 5V, VDPRSLPVR = VGNDS = 0, VCSP_ = VCSN_ = 1.0000V, FB = FBAC, RFBAC = 3.57k from FBAC to CSN_, [D6­D0] = [0101000]; TA = -40oC to +105°C, unless otherwise noted.) (Note 5) PARAMETER On-Time Accuracy SYMBOL t ON Minimum Off-Time t OFF(MIN) CONDITIONS VIN = 10V, VFB = 1.0V, measured at DH1, DH2, and PWM3 (Note 4) MIN TYP MAX RTON = 96.75k (600kHz per phase), 167ns nominal -15 +15 RTON = 200k (300kHz per phase), 333ns nominal -10 +10 RTON = 303.25k (200kHz per phase), 500ns nominal -15 UNITS +15 Measured at DH1, DH2, and PWM3 (Note 4) % 400 ns 7 mA BIAS CURRENTS Quiescent Supply Current (VCC) ICC Measured at VCC, DPRSLPVR = 5V, FB forced above the regulation point FAULT PROTECTION VOVP 250 350 mV Soft-start, soft-shutdown, skip mode, and output have not reached the regulation voltage; measured at FB Output Overvoltage-Protection Threshold Skip mode after output reaches the regulation voltage or PWM mode; measured at FB with respect to the voltage target set by the VID code (see Table 4) 1.45 1.55 V -450 -350 mV Output Undervoltage-Protection Threshold VUVP Measured at FB with respect to the voltage target set by the VID code (see Table 4) CLKEN Startup Delay and Boot Time Period tBOOT Measured from the time when FB reaches the boot target voltage (Note 3) 20 100 s PWRGD Startup Delay Measured at startup from the time when CLKEN goes low 3 10 ms -350 -250 CLKEN and PWRGD Threshold Measured at FB with respect to the voltage target set by the VID code (see Table 4), 20mV hysteresis (typ) CLKEN, PWRGD Output Low Voltage VCC Undervoltage-Lockout Threshold Lower threshold, falling edge (undervoltage) mV Upper threshold, rising edge (overvoltage) +150 Low state, I SINK = 3mA VUVLO(VCC) Rising edge, 65mV typical hysteresis, controller disabled below this level +250 0.4 V 4.05 4.5 V 29 31 % THERMAL PROTECTION VRHOT Trip Threshold VRHOT Output On-Resistance Measured at THRM with respect to VCC, falling edge, typical hysteresis = 75mV RON(VRHOT) Low state 8 _ 7 MAX17030/MAX17036 MAX17030/MAX17036 ELECTRICAL CHARACTERISTICS (continued) MAX17030/MAX17036 MAX17030/MAX17036 1/2/3-Phase Quick-PWM IMVP-6.5 VID Controllers ELECTRICAL CHARACTERISTICS (continued) (Circuit of Figure 1, VIN = 10V, VCC = VDD = V SHDN = VPGD_IN = V PSI = VILIM = 5V, VDPRSLPVR = VGNDS = 0, VCSP_ = VCSN_ = 1.0000V, FB = FBAC, RFBAC = 3.57k from FBAC to CSN_, [D6­D0] = [0101000]; TA = -40oC to +105°C, unless otherwise noted.) (Note 5) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS VALLEY CURRENT LIMIT, DROOP, CURRENT BALANCE, AND CURRENT MONITOR Current-Limit Threshold Voltage (Negative) Accuracy VTIME - VILIM = 100mV VCSP_ - VCSN_ 7 13 45 55 20 25 -4 +4 mV 0 VLIMIT VTIME - VILIM = 500mV ILIM = VCC Current-Limit Threshold Voltage (Positive) 2 V VLIMIT(NEG) VCSP_ - VCSN_, nominally -125% of VLIMIT CSP_, CSN_ Common-Mode Input Range mV Phases 2, 3 Disable Threshold Measured at CSP2, CSP3 3 VCC 0.4 V Droop Amplifier Offset (1/N) x (VCSP_ - VCSN_) at IFBAC = 0; indicates summation over all power-up enabled phases from 1 to N, N = 3 -1 +1 mV/ phase Droop Amplifier Transconductance IFBAC/ [ (VCSP_ - VCSN_)]; indicates summation over all power-up enabled phases from 1 to N, N = 3, VFBAC = VCSN_ = 0.45V to 1.5V 390 407 S (1/N) x (VCSP_ - VCSN_) at IFBAC = 0; indicates summation over all power-up enabled phases from 1 to N, N = 3 -1.5 +1.5 mV/ phase 1.536 1.664 mS Gm(FBAC) Current-Monitor Offset Current-Monitor Transconductance Gm(IMON) IIMON/ [ (VCSP_ - VCSN_)]; indicates summation over all power-up enabled phases from 1 to N, N = 3, VCSN_ = 0.45V to 1.5V R ON(DH) BST_ ­ LX_ forced to 5V GATE DRIVERS DH_ Gate-Driver On-Resistance DL_ Gate-Driver On-Resistance R ON(DL) Internal BST_ Switch On-Resistance R ON(BST) High state (pullup) 2.5 Low state (pulldown) 2 High state (pullup) 2 Low state (pulldown) 0.7 IBST- = 10mA 20 PWM3, DRSKP OUTPUTS PWM3, DRSKP Output High Voltages I SOURCE = 3mA PWM3, DRSKP Output Low Voltages I SINK = 3mA VDD 0.4V V 0.4 V 1.0 V LOGIC AND I/O Logic-Input High Voltage VIH SHDN, PGD_IN Logic-Input Low Voltage VIL SHDN, PGD_IN Low-Voltage Logic-Input High Voltage Low-Voltage Logic-Input Low Voltage 8 VIHLV PSI, D0­D6, DPRSLPVR VILLV 2.3 PSI, D0­D6, DPRSLPVR V 0.67 _ V 0.33 V 1/2/3-Phase Quick-PWM IMVP-6.5 VID Controllers Note 3: The equation for the target voltage VTARGET is: VTARGET = The slew-rate-controlled version of VDAC, where VDAC = 0 for shutdown VDAC = VBOOT during IMVP-6.5 startup VDAC = VVID otherwise (the VVID voltages for all possible VID codes are given in Table 4). In pulse-skipping mode, the output rises by approximately 1.5% when transitioning from continuous conduction to no load. Note 4: On-time and minimum off-time specifications are measured from 50% to 50% at the DH_ pin, with LX_ forced to 0V, BST_ forced to 5V, and a 500pF capacitor from DH_ to LX_ to simulate external MOSFET gate capacitance. Actual in-circuit times might be different due to MOSFET switching speeds. Note 5: Specifications to -40°C and +105°C are guaranteed by design, not production tested. Typical Operating Characteristics (Circuit of Figure 1. VIN = 12V, VCC = VDD = 5V, SHDN = VCC, D0­D6 set for 0.95V, TA = +25°C, unless otherwise specified.) 12V 60 20V 50 40 7V 80 0.95 EFFICIENCY (%) OUTPUT VOLTAGE (V) 70 90 MAX17030 MAX17030 toc02 7V 80 0.90 12V 70 20V 60 0.85 SKIP MODE PWM MODE 30 20 50 0.80 0.1 1 10 100 0 10 20 30 40 50 60 0.1 70 1 10 100 LOAD CURRENT (A) LOAD CURRENT (A) LOAD CURRENT (A) OUTPUT VOLTAGE vs. LOAD CURRENT (VOUT(LFM) = 0.875V) SWITCHING FREQUENCY vs. LOAD CURRENT VOUT(HFM) = 0.95V NO-LOAD SUPPLY CURRENT vs. INPUT VOLTAGE 0.88 1-PHASE SKIP MODE 0.87 0.86 0.85 2-PHASE PWM MODE 0.84 350 VOUT(HFM) = 0.95V 300 250 200 150 100 5 10 LOAD CURRENT (A) 15 20 IIN 100 ICC + IDD 10 ICC + IDD 1 IIN 0.1 0.01 0 0 DPRSLPVR = VCC DPRSLPVR = GND DPRSLPVR = VCC DPRSLPVR = GND 50 0.83 1000 MAX17030 MAX17030 toc05 VOUT(LFM) = 0.875V SUPPLY CURRENT (mA) OUTPUT VOLTAGE (V) 0.89 400 SWITCHING FREQUENCY (kHz) MAX17030 MAX17030 toc04 0.90 MAX17030 MAX17030 toc06 EFFICIENCY (%) 1.00 MAX17030 MAX17030 toc01 100 90 EFFICIENCY vs. LOAD CURRENT (VOUT(LFM) = 0.875V) OUTPUT VOLTAGE vs. LOAD CURRENT (VOUT(HFM) = 0.95V) MAX17030 MAX17030 toc03 EFFICIENCY vs. LOAD CURRENT (VOUT(HFM) = 0.95V) 0 10 20 30 LOAD CURRENT (A) 40 50 6 9 12 15 18 21 INPUT VOLTAGE (V) _ 9 MAX17030/MAX17036 MAX17030/MAX17036 ELECTRICAL CHARACTERISTICS (continued) Typical Operating Characteristics (continued) (Circuit of Figure 1. VIN = 12V, VCC = VDD = 5V, SHDN = VCC, D0­D6 set for 0.95V, TA = +25°C, unless otherwise specified.) IIMON vs. LOAD CURRENT CURRENT BALANCE vs. LOAD CURRENT 100 0.2 VOUT = 0.95V VOUT = 0.95V 0.1 VCSP3 VCSN3 VCS2 - VCS1 0 VCSP2 - VCSN2 5 -0.1 VCS3 - VCS1 0 10 20 30 40 60 DPRSLPVR = GND 40 20 0 -0.2 50 60 0 70 10 20 40 30 50 LOAD CURRENT (A) 0.8125V OUTPUT VOLTAGE DISTRIBUTION Gm(FB) TRANSCONDUCTANCE DISTRIBUTION SAMPLE SIZE = 100 70 +85°C +25°C 60 SAMPLE PERCENTAGE (%) +85°C +25°C MAX17030 MAX17030 toc09 70 60 60 VCSP - CSN (mV) 50 40 30 20 SAMPLE SIZE = 100 50 40 30 20 410 408 406 404 402 400 398 396 394 392 390 0.8175 0.8165 0.8155 0.8145 0.8135 0.8125 0.8115 0.8105 0 0.8095 0 0.8085 10 0.8075 10 TRANCONDUCTANCE (s) OUTPUT VOLTAGE (V) 40 SAMPLE SIZE = 100 30 25 20 15 10 1650 1640 1610 1600 1590 1580 1570 1560 1550 0 1630 +85°C +25°C 5 1620 SAMPLE PERCENTAGE (%) 35 MAX17030 MAX17030 toc11 Gm(IMON) TRANSCONDUCTANCE DISTRIBUTION TRANCONDUCTANCE (s) 10 _ MAX17030 MAX17030 toc10 0 80 IMON (A) 15 SENSE VOLTAGE DIFFERENCE (mV) SENSE VOLTAGE (mV) VCSP1 - VCSN1 10 MAX17030 MAX17030 toc08 MAX17030 MAX17030 toc07 20 SAMPLE PERCENTAGE (%) MAX17030/MAX17036 MAX17030/MAX17036 1/2/3-Phase-Quick-PWM IMVP-6.5 VID Controllers 1/2/3-Phase-Quick-PWM IMVP-6.5 VID Controllers SOFT-START WAVEFORM (UP TO CLKEN) SOFT-START WAVEFORM (UP TO PWRGD) MAX17030 MAX17030 toc12 3.3V 0 3.3V 0 0.95V MAX17030 MAX17030 toc13 A B C 3.3V 0 3.3V 0 3.3V 0 0.95V A B C D 0 D 0 0 E 0 0 E F 0 F 0 G 0 200s/div 1ms/div D. ILX1, 10A/div E. ILX2, 10A/div F. ILX3, 10A/div IOUT, 15A A. SHDN, 5V/div B. CLKEN, 10V/div C. VOUT, 500mV/div SHUTDOWN WAVEFORM LOAD-TRANSIENT RESPONSE (HFM MODE) MAX17030 MAX17030 toc14 3.3V 0 3.3V 0 3.3V 0 0.95V E. DL1, 10V/div F. DL2, 10V/div G. DL3, 10V/div IOUT, 15A A. SHDN, 5V/div B. CLKEN, 6.6V/div C. PWRGD, 10V/div D. VOUT, 1V/div MAX17030 MAX17030 toc15 A 59A B C 7A A 0.935V D 0 B 0.84V 0 E 0 F 0 G C D E 200s/div A. SHDN, 5V/div B. PWRGD, 10V/div C. CLKEN, 10V/div D. VOUT, 500mV/div E. DL1, 10V/div F. DL2, 10V/div G. DL3, 10V/div 20s/div A. IOUT = 7A - 59A B. VOUT, 50mV/div C. ILX1, 20A/div D. ILX2, 20A/div E. ILX3, 20A/div _ 11 MAX17030/MAX17036 MAX17030/MAX17036 Typical Operating Characteristics (continued) (Circuit of Figure 1. VIN = 12V, VCC = VDD = 5V, SHDN = VCC, D0­D6 set for 0.95V, TA = +25°C, unless otherwise specified.) 1/2/3-Phase Quick-PWM IMVP-6.5 VID Controllers MAX17030/MAX17036 MAX17030/MAX17036 Pin Description PIN NAME FUNCTION CSN3 Negative Input of the Output Current Sense of Phase 3. This pin should be connected to the negative side of the output current-sensing resistor or the filtering capacitor if the DC resistance of the output inductor is utilized for current sensing. 2 CSP3 Positive Input of the Output Current Sense of Phase 3. This pin should be connected to the positive side of the output current-sensing resistor or the filtering capacitor if the DC resistance of the output inductor is utilized for current sensing. To disable phase 3, connect CSP3 to VCC and CSN3 to GND. 3 THRM Input of Internal Comparator. Connect the output of a resistor- and thermistor-divider (between VCC and GND) to THRM. Select the components such that the voltage at THRM falls below 1.5V (30% of VCC) at the desired high temperature. 1 Current Monitor Output Pin. The output current at this pin is: I IMON = GM(IMON) x 4 IMON V(CSP_,CSN_) where GM(IMON) = 1.6mS typical and denotes summation over all enabled phases. An external resistor RIMON between IMON and GNDS sets the current-monitor output voltage: VIMON = ILOAD x R SENSE x GM(IMON) x RIMON where RSENSE is the value of the effective current-sense resistance. Choose RIMON such that VIMON does not exceed 900mV at the maximum expected load current IMAX. IMON is high impedance when the MAX17030/MAX17036 MAX17030/MAX17036 are in shutdown. 5 ILIM Current-Limit Adjust Input. The valley positive current-limit threshold voltages at V(CSP_,CSN_) are precisely 1/10 the differential voltage V(TIME,ILIM) over a 0.1V to 0.5V range of V(TIME,ILIM). The valley negative current-limit thresholds are typically -125% of the corresponding valley positive current-limit thresholds. Connect ILIM to VCC to get the default current-limit threshold setting of 22.5mV typ. Slew-Rate Adjustment Pin. The total resistance RTIME from TIME to GND sets the internal slew rate: Slew rate = (12.5mV/s) x (71.5k /RTIME) where RTIME is between 35.7k and 178k . This "normal" slew rate applies to transitions into and out of the low-power pulse-skipping modes and to the transition from boot mode to VID. The slew rate for startup and for entering shutdown is always 1/4 of normal. If the VID DAC inputs are clocked, the slew rate for all other VID transitions is set by the rate at which they are clocked, up to a maximum slew rate equal to the normal slew rate defined above. 6 TIME 7 VCC Controller Supply Voltage. Connect to a 4.5V to 5.5V source. Bypass to GND with 1F minimum. FB Feedback Voltage Input. The voltage at the FB pin is compared with the slew-rate-controlled target voltage by the error comparator (fast regulation loop), as well as by the internal voltage integrator (slow, accurate regulation loop). Having sufficient ripple signal at FB that is in phase with the sum of the inductor currents is essential for cycle-by-cycle stability. The external connections and compensation at FB depend on the desired DC and transient (AC) droop values. If DC droop = AC droop, then short FB to FBAC. To disable DC droop, connect FB to the remote-sensed output voltage through a resistor R and feed forward the FBAC ripple to FB through capacitor C, where the R x C time constant should be at least 3x the switching period per phase. 8 12 _ 1/2/3-Phase Quick-PWM IMVP-6.5 VID Controllers PIN NAME FUNCTION Output of the Voltage-Positioning Transconductance Amplifier. Connect a resistor RFBAC between FBAC and the positive side of the feedback remote sense to set the transient (AC) droop based on the stability, load-transient response, and voltage-positioning gain requirements: RFBAC = RDROOP,AC/[RSENSE x Gm(FBAC)] where RDROOP,AC is the transient (AC) voltage-positioning slope that provides an acceptable tradeoff between stability and load-transient response, Gm(FBAC) = 400S typ, and RSENSE is the effective current-sense resistance that is used to provide the (CSP_, CSN_) current-sense voltages. A minimum RDROOP,AC value is required for stability, but if there are no ceramic output capacitors used, then the minimum requirement applies to RESR + RDROOP,AC, where RESR is the effective ESR of the output capacitors. If lossless sensing (inductor DCR sensing) is used, use a thermistor-resistor network to minimize the temperature dependence of the voltage-positioning slope. FBAC is high impedance in shutdown. 9 FBAC 10 GNDS Feedback Remote-Sense Input, Negative Side. Normally connected to GND directly at the load. GNDS internally connects to a transconductance amplifier that fine tunes the output voltage compensating for voltage drops from the regulator ground to the load ground. 11 CSN2 Negative Input of the Output Current Sense of Phase 2. This pin should be connected to the negative side of the output current-sensing resistor or the filtering capacitor if the DC resistance of the output inductor is utilized for current sensing. CSP2 Positive Input of the Output Current Sense of Phase 2. This pin should be connected to the positive side of the output current-sensing resistor or the filtering capacitor if the DC resistance of the output inductor is utilized for current sensing. To disable phase 2, connect CSP2 to VCC and CSN2 to GND. SHDN Shutdown Control Input. Connect to VCC for normal operation. Connect to ground to put the IC into the 1A (max at TA = +25°C) shutdown state. During startup, the output voltage is ramped up at 1/4 the slew rate set by the TIME resistor to the boot voltage or to the target voltage. During the transition from normal operation to shutdown, the output voltage is ramped down at 1/4 the slew rate set by the TIME resistor. Forcing SHDN to 11V~13V to enter no-fault test mode clears the fault latches, disables transient phase overlap, and turns off the internal BST_-to-VDD switches. However, internal diodes still exist between BST_ and VDD in this state. 12 13 14 DPRSLPVR Deeper Sleep VR Control Input. This low-voltage logic input indicates power usage and sets the operating mode together with PSI as shown in the truth table below. When DPRSLPVR is forced high, the controller is immediately set to 1-phase automatic pulse-skipping mode. The controller returns to forcedPWM mode when DPRSLPVR is forced low and the output is in regulation. The PWRGD upper threshold is blanked during any downward output-voltage transition that happens when the controller is in skip mode, and stays blanked until the slew-rate-controlled internal-transition-related PWRGD blanking period is complete and the output reaches regulation. During this blanking period, the overvoltage fault threshold is changed from a tracking [VID + 300mV] threshold to a fixed 1.5V threshold. The controller is in N-phase skip mode during startup including boot mode, but is in N-phase forced-PWM mode during the transition from boot mode to VID mode, during soft-shutdown, irrespective of the DPRSLPVR and PSI logic levels. However, if phases 2 and 3 are disabled by connecting CSP2, CSP3 to VCC, then only phase 1 is active in the above modes. DPRSLPVR PSI 1 0 0 X 0 1 MODE Very low current (1-phase skip) Intermediate power potential (N-1-phase PWM) Max power potential (full-phase PWM: N-phase or 1 phase as set by user at CSP2, CSP3) _ 13 MAX17030/MAX17036 MAX17030/MAX17036 Pin Description (continued) 1/2/3-Phase Quick-PWM IMVP-6.5 VID Controllers MAX17030/MAX17036 MAX17030/MAX17036 Pin Description (continued) PIN 15 NAME PSI FUNCTION This low-voltage logic input indicates power usage and sets the operating mode together with DPRSLPVR as shown in the truth table below. While DPRSLPVR is low, if PSI is forced low, the controller is immediately set to (N-1)-phase forced-PWM mode. The controller returns to N-phase forced-PWM mode when PSI is forced high. The controller is in N-phase skip mode during startup including boot mode, but is in N-phase forcedPWM mode during the transition from boot mode to VID mode, during soft-shutdown, irrespective of the DPRSLPVR and PSI logic levels. However, if phases 2 and 3 are disabled by connecting CSP2, CSP3 to VCC, then only phase 1 is active in the above modes. DPRSLPVR PSI 1 0 0 X 0 1 MODE Very low current (1-phase skip) Intermediate power potential (N-1-phase PWM) Max power potential (full-phase PWM: N-phase or 1 phase as set by user at CSP2, CSP3) Switching Frequency Setting Input. An external resistor between the input power source and this pin sets the switching frequency according to the following equation: fSW = 1/(CTON x (RTON + 6.5k) 16 17 18 19 14 TON where CTON = 16.26pF. The external resistor must also satisfy the requirement [VIN(MIN)/RTON] 10A where VIN(MIN) is the minimum VIN value expected in the application. TON is high impedance in shutdown. CLKEN Clock Enable Open-Drain Logic Output Powered by V3P3. This inverted logic output indicates when the output voltage sensed at FB is in regulation. CLKEN is forced high in shutdown and during soft-start and soft-stop transitions. CLKEN is forced low during dynamic VID transitions and for an additional 20s after the transition is completed. CLKEN is the inverse of PWRGD, except for the 5ms PWRGD startup delay period after CLKEN is pulled low. See the startup timing diagram (Figure 9). The CLKEN upper threshold is blanked during any downward output-voltage transition that happens when the controller is in skip mode, and stays blanked until the slew-rate-controlled internal-transition-related PWRGD blanking period is complete and the output reaches regulation. PWRGD Open-Drain Power-Good Output. After output-voltage transitions, except during power-up and powerdown, if FB is in regulation, then PWRGD is high impedance. PWRGD is low during startup, continues to be low while the output is at the boot voltage, and stays low until 5ms (typ) after CLKEN goes low, after which it starts monitoring the FB voltage and goes high if FB is within the PWRGD threshold window. PWRGD is forced low during soft-shutdown and while in shutdown. PWRGD is forced high impedance whenever the slew-rate controller is active (output-voltage transitions), and continues to be forced high impedance for an additional 20s after the transition is completed. The PWRGD upper threshold is blanked during any downward output-voltage transition that happens when the controller is in skip mode, and stays blanked until the slew-rate-controlled internal-transitionrelated PWRGD blanking period is complete and the output reaches regulation. A pullup resistor on PWRGD causes additional finite shutdown current. DRSKP Driver Skip Control Output. Push/pull logic output that controls the operating mode of the skip-mode driver IC. DRSKP swings from VDD to GND. When DRSKP is high, the driver ICs operate in forcedPWM mode. When DRSKP is low, the driver ICs enable their zero-crossing comparators and operate in pulse-skipping mode. DRSKP goes low at the end of the soft-shutdown sequence, instructing the external drivers to shut down. _ 1/2/3-Phase Quick-PWM IMVP-6.5 VID Controllers PIN NAME FUNCTION 20 PWM3 PWM Signal Output for Phase 3. Swings from GND to VDD. Three-state whenever phase 3 is disabled (in shutdown, when CSP3 is connected to VCC, and when operating with fewer than all phases). 21 BST2 Phase 2 Boost Flying Capacitor Connection. BST2 is the internal upper supply rail for the DH2 highside gate driver. An internal switch between VDD and BST2 charges the BST2-LX2 flying capacitor while the low-side MOSFET is on (DL2 pulled high). 22 LX2 Phase 2 Inductor Connection. LX2 is the internal lower supply rail for the DH2 high-side gate driver. Also used as an input to phase 2's zero-crossing comparator. 23 DH2 Phase 2 High-Side Gate-Driver Output. DH2 swings from LX2 to BST2. Low in shutdown. 24 DL2 Phase 2 Low-Side Gate-Driver Output. DL2 swings from GND to VDD. DL2 is forced low in shutdown. DL2 is forced high when an output overvoltage fault is detected, overriding any negative currentlimit condition that might be present. DL2 is forced low in skip mode after detecting an inductor current zero crossing. 25 VRHOT 26 VDD Supply Voltage Input for the DL_ Drivers. VDD is also the supply voltage used to internally recharge the BST_-LX_ flying capacitor during the times the respective DL_s are high. Connect VDD to the 4.5V to 5.5V system supply voltage. Bypass VDD to GND with a 1F or greater ceramic capacitor. 27 DL1 Phase 1 Low-Side Gate-Driver Output. DL1 swings from GND to VDD. DL1 is forced low in shutdown. DL1 is forced high when an output overvoltage fault is detected, overriding any negative currentlimit condition that might be present. DL1 is forced low in skip mode after detecting an inductor current zero crossing. 28 DH1 Phase 1 High-Side Gate-Driver Output. DH1 swings from LX1 to BST1. Low in shutdown. 29 LX1 Phase 1 Inductor Connection. LX1 is the internal lower supply rail for the DH1 high-side gate driver. Also used as an input to phase 1's zero-crossing comparator. 30 BST1 Phase 1 Boost Flying Capacitor Connection. BST1 is the internal upper supply rail for the DH1 highside gate driver. An internal switch between VDD and BST1 charges the BST1-LX1 flying capacitor while the low-side MOSFET is on (DL1 pulled high). PGD_IN Power-Good Logic Input Pin that Indicates the Power Status of Other System Rails and Used for Supply Sequencing. During startup, after soft-starting to the boot voltage, the output voltage remains at VBOOT, and the CLKEN and PWRGD outputs remain high and low, respectively, as long as the PGD_IN input stays low. When PGD_IN later goes high, the output is allowed to transition to the voltage set by the VID code, and CLKEN is allowed to go low. During normal operation, if PGD_IN goes low, the controller immediately forces CLKEN high and PWRGD low, and slews the output to the boot voltage while in skip mode at 1/4 the normal slew rate set by the TIME resistor. The output then stays at the boot voltage until the controller is turned off or power cycled, or until PGD_IN goes high again. 32­38 D0­D6 Low-Voltage (1.0V Logic) VID DAC Code Inputs. The D0­D6 inputs do not have internal pullups. These 1.0V logic inputs are designed to interface directly with the CPU. The output voltage is set by the VID code indicated by the logic-level voltages on D0­D6 (see Table 4). The 1111111 code corresponds to a shutdown mode. When this code is detected, The MAX17030/MAX17036 MAX17030/MAX17036 initiate a soft-shutdown transition identical to the shutdown transition for a SHDN falling edge. After slewing the output to 0V, it forces DH_, DL_, and DRSKP low, and three-states PWM3. The IC remains active and its VCC quiescent current consumption stays the same as in normal operation. If D6­D0 is changed from 1111111 to a different code, the MAX17030/MAX17036 MAX17030/MAX17036 initiate a startup sequence identical to the startup sequence for a SHDN rising edge. 39 CSP1 Positive Input of the Output Current Sense of Phase 1. This pin should be connected to the positive side of the output current-sensing resistor or the filtering capacitor if the DC resistance of the output inductor is utilized for current sensing. 31 Open-Drain Output of Internal Comparator. VRHOT is pulled low when the voltage at THRM goes below 1.5V (30% of VCC). VRHOT is high impedance in shutdown. _ 15 MAX17030/MAX17036 MAX17030/MAX17036 Pin Description (continued) 1/2/3-Phase Quick-PWM IMVP-6.5 VID Controllers MAX17030/MAX17036 MAX17030/MAX17036 Pin Description (continued) PIN NAME FUNCTION 40 CSN1 Negative Input of the Output Current Sense of Phase 1. This pin should be connected to the negative side of the output current-sensing resistor or the filtering capacitor if the DC resistance of the output inductor is utilized for current sensing. A 10 discharge FET is turned on in UVLO event or thermal shutdown, or at the end of soft-shutdown. - PAD (GND) Exposed Backplate (Pad) of Package. Internally connected to both analog ground and power (driver) grounds. Connect to the ground plane through a thermally enhanced via. 32 33 34 35 VID INPUTS 36 37 38 13 ON OFF (VRON) 14 DPRSLPVR 31 PGDIN 15 PSI 26 5V BIAS CVDD 2.2F RVCC 20 7 CVCC 1.0F 5 RILIM1 RILIM2 6 TON D0 RTON 200k 16 30 BST1 28 DH1 D1 D2 D3 LX1 29 8V TO 20V PWR INPUT CIN NH CBST L1 OUTPUT (IMVP-6.5 CORE) D4 D5 DL1 D6 CSP1 SHDN 27 CSN1 PSI BST2 DH2 VDD VCC MAX17030 MAX17030 MAX17036 MAX17036 LX2 DL2 CSP2 ILIM 2 R2 CSN2 RNTC1 CCS1 40 8V TO 20V PWR INPUT 21 CIN 23 22 NH CBST L2 24 NL R6 R4 COUT 12 2 TIME COUT 39 DPRSLPVR PGDIN R3 R1 NL 11 RNTC2 R5 CCS2 8V TO 20V PWR INPUT 5V BIAS 3.3V VCCP RVRHOT 56 RCLKEN 1.9k CVCC1 1.0F RPWRGD 1.9k 18 25 17 4 IMON PWRGD PWM3 VRHOT DRSKP CLKEN CSP3 IMON CSN3 VSS_SENSE 3 RTHRM 13k FBAC THRM FB NTC 100k = 4250 GNDS 20 NH DH CBST L3 LX PWM DL SKIP 19 CIN BST MAX8791 MAX8791 RIMON VCC VCC R9 GND R7 NL 2 R8 2 1 9 8 10 PAD RNTC3 CCS3 RFBS 10 RFB CFBS 1000pF VCC_SENSE RCATCHCORE 10 CPU REMOTE SENSE RGNDS 10 VSS_SENSE CGNDS 4700pF RCATCHGND 10 Figure 1. Standard 3-Phase IMVP-6.5 Application Circuit 16 _ COUT 1/2/3-Phase Quick-PWM IMVP-6.5 VID Controllers IMVP-6.5 XE CORE 3-PHASE DESIGN PARAMETERS IMVP-6.5 SV CORE 3-PHASE MAX17030/MAX17036 MAX17030/MAX17036 Table 1. Component Selection for Standard Applications IMVP-6.5 SV CORE 2-PHASE Circuit Figure 1 Figure 1 Input Voltage Range 8V to 20V 8V to 20V 8V to 20V Maximum Load Current 65A (48A TDC) 52A (38A TDC) 52A (38A TDC) Transient Load Current 49A (100A/s) 39A (100A/s) 39A (100A/s) Load Line -1.9mV/A -1.9mV/A -1.9mV/A POC Setting 110 101 101 TON Resistance (RTON) 200k Inductance (L) 0.36H, 36A, 0.82m (10mm x 10mm) Panasonic ETQP4LR36ZFC ETQP4LR36ZFC 0.42H, 20A, 1.55m (7mm x 7mm) NEC/TOKIN MPC0740LR42C MPC0740LR42C 0.36H, 36A, 0.82m (10mm x 10mm) Panasonic ETQP4LR36ZFC ETQP4LR36ZFC High-Side MOSFET (NH) Fairchildsemi 1x FDS6298 FDS6298 9.4m /12m (typ/max) Toshiba 1x TPCA8030-H TPCA8030-H 9.6m /13.4m (typ/max) Fairchildsemi 1x FDS6298 FDS6298 9.4m /12m (typ/max) Toshiba 1x TPCA8030-H TPCA8030-H 9.6m /13.4m (typ/max Fairchildsemi 1x FDS6298 FDS6298 9.4m /12m (typ/max) Toshiba 1x TPCA8030-H TPCA8030-H 9.6m /13.4m (typ/max) Fairchildsemi 2x FDS8670 FDS8670 Low-Side MOSFET (NL) 4.2m /5m (typ/max) Toshiba 2x TPCA8019-H TPCA8019-H 4x 330F, 2V, 4.5m Output Capacitors (COUT) Panasonic EEFSXOD331E4 EEFSXOD331E4 or (MAX17030 MAX17030 Only) NEC/Tokin PSGVOE337M4 PSGVOE337M4.5 Contact Maxim for MAX17036 MAX17036 27x 22F, 6.3V X5R reference design ceramic capacitor (0805) Fairchildsemi 1x FDS8670 FDS8670 4.2m /5m (typ/max) Toshiba 1x TPCA8019-H TPCA8019-H 3x 330F, 2V, 4.5m Panasonic EEFSXOD331E4 EEFSXOD331E4 or NEC/Tokin PSGVOE337M4 PSGVOE337M4.5 27x 22F, 6.3V X5R ceramic capacitor (0805) Fairchildsemi 2x FDS8670 FDS8670 4.2m /5m (typ/max) Toshiba 2x TPCA8019-H TPCA8019-H Input Capacitors (CIN) 4x 10F 25V ceramic (1210) (f SW = 300kHz) 6x 10F 25V ceramic (1210) 200k (f SW = 300kHz) Figure 2 200k (f SW = 300kHz) 4x 330F, 6m , 2.5V Panasonic EEFSX0D0D331XR EEFSX0D0D331XR 28x 10F, 6V ceramic (0805) 4x 10F 25V ceramic (1210) TIME-ILIM Resistance (RILIM2) 14k 14k 16.9k ILIM-GND Resistance (RILIM1) 137k 137k 133k FB Resistance (RFB) 6.04k 453k 6.04k IMON Resistance (RIMON) 12.1k LX-CSP Resistance 2.21k (R1, R4, R7) 1.4k CSP-CSN Resistance 3.24k 40.2k (R2, R5, R8) (R3, R6, R9) DCR Sense NTC (RNTC) DCR Sense Capacitance (CSENSE) 10.2k 14k (R1, R4, R7) 2.21k (R1, R7) 2k (R2, R5, R8) 40.2k (R3, R6, R9) 3.24k 40.2k (R2, R8) (R3, R9) 10k NTC B = 3380 TDK NTCG163JH103F NTCG163JH103F 10k NTC B = 3380 TDK NTCG163JH103F NTCG163JH103F 10k NTC B = 3380 TDK NTCG163JH103F NTCG163JH103F 0.22F, 6V ceramic (0805) 0.22F, 6V ceramic (0805) 0.22F, 6V ceramic (0805) _ 17 MAX17030/MAX17036 MAX17030/MAX17036 1/2/3-Phase Quick-PWM IMVP-6.5 VID Controllers Table 2. Component Suppliers MANUFACTURER WEBSITE MANUFACTURER WEBSITE AVX Corp. www.avxcorp.com Siliconix (Vishay) www.vishay.com Fairchild Semiconductor www.fairchildsemi.com Taiyo Yuden www.t-yuden.com NEC/TOKIN America, Inc. www.nec-tokinamerica.com TDK Corp. www.component.tdk.com Panasonic Corp. www.panasonic.com TOKO America, Inc. www.tokoam.com SANYO Electric Co., Ltd. www.sanyodevice.com Toshiba America Electronic Components, Inc. www.toshiba.com/taec 32 33 34 35 VID INPUTS 36 37 38 13 ON OFF (VRON) 14 DPRSLPVR 31 PGDIN PSI 5V BIAS CVDD 2.2F RVCC 20 RILIM2 BST1 D2 DH1 D3 D4 LX1 6 D6 DL1 RVRHOT 56 DPRSLPVR CSP1 25 17 4 IMON CSN1 VCC 29 L1 OUTPUT (IMVP-6.5 CORE) R3 R1 NL COUT 39 40 RNTC1 R2 2 CCS1 8V TO 20V PWR INPUT 21 CIN 23 NH CBST L2 LX2 ILIM DL2 TIME CSN2 24 R9 R7 NL 12 COUT RNTC3 R8 2 11 CCS2 PWRGD VRHOT PWM3 CLKEN DRSKP 20 19 IMON CSP3 CSN3 VSS_SENSE 3 NH CBST 27 MAX17030 MAX17030 DH2 MAX17036 MAX17036 22 RIMON VCC CIN 28 RPWRGD 1.9k 18 8V TO 20V PWR INPUT 30 PGDIN CSP2 RCLKEN 1.9k RTON 200k SHDN 3.3V VCCP 16 D5 BST2 5 RILIM1 TON D1 15 PSI 26 VDD 7 CVCC 1.0F D0 FBAC THRM RTHRM 13k FB NTC 100k = 4250 GNDS PAD 2 5V BIAS 1 RCATCHCORE 10 RFBS 10 9 8 10 RFB VCC_SENSE CFBS 1000pF VSS_SENSE RGNDS 10 RCATCHGND 10 Figure 2. Standard 2-Phase IMVP-6.5 Application Circuit 18 _ CPU REMOTE SENSE 1/2/3-Phase Quick-PWM IMVP-6.5 VID Controllers MAX17030/MAX17036 MAX17030/MAX17036 THRM VRHOT PWM3 PHASE 3 DRIVER CONTROL DRSKP CSN3 0.3 x VCC TRIG Q TRIG3 Gm(CCI) CSP3 TON CC13 ONE-SHOT PHASE 3 ON-TIME 10x CSN3 CSP3 CSP1 Gm(CCI3) CSN1 BST2 DH2 LX2 DL2 GND CSP2 10x PHASE 2 DRIVERS CSN2 CSP1 Q 10x CSN1 ILIM MINIMUM OFF-TIME TIME Q TRIG ONE-SHOT PHASE 2 ON-TIME CCI2 CSN2 TRIG TRIG 3 Gm(CCI) ONE SHOT VCC PHASE 1 ON-TIME ONE-SHOT REF (2.0V) Q GND D0­D6 PGDIN CSP1 FB Gm(CCI) TRIG SLEW DAC CSP2 CSN1 TON R-TO-I CONVERTER MAIN PHASE DRIVERS R Q BST1 DH1 S SHDN LX1 S PGND1 TARGET FAULT PHASE SEL Q LX1 R 0mV VDD SKIP DL1 TARGET - 300mV GND TARGET + 200mV FB PWRGD 5ms STARTUP DELAY GNDS SKIP CLKEN 60s x3 CSP Gm(FB) CSN FBAC MAX17030 MAX17030 MAX17036 MAX17036 MODE/PHASE/SLEWRATE CONTROL BLANK CSP IMON CSN PGDIN DPRSLPVR x3 Gm(IMON) PSI Figure 3. Functional Diagram _ 19 MAX17030/MAX17036 MAX17030/MAX17036 1/2/3-Phase Quick-PWM IMVP-6.5 VID Controllers Detailed Description Free-Running, Constant-On-Time PWM Controller with Input Feed-Forward The Quick-PWM control architecture is a pseudo-fixedfrequency, constant-on-time, current-mode regulator with voltage feed-forward (Figure 3). This architecture relies on the output filter capacitor's ESR to act as the currentsense resistor, so the output ripple voltage provides the PWM ramp signal. The control algorithm is simple: the high-side switch on-time is determined solely by a oneshot whose period is inversely proportional to input voltage, and directly proportional to output voltage or the difference between the main and secondary inductor currents (see the On-Time One-Shot section). Another oneshot sets a minimum off-time. The on-time one-shot triggers when the error comparator goes low, the inductor current of the selected phase is below the valley currentlimit threshold, and the minimum off-time one-shot times out. The controller maintains 120° out-of-phase operation by alternately triggering the three phases after the error comparator drops below the output-voltage set point. Triple 120° Out-of-Phase Operation The three phases in the MAX17030/MAX17036 MAX17030/MAX17036 operate 120° out-of-phase to minimize input and output filtering requirements, reduce electromagnetic interference (EMI), and improve efficiency. This effectively lowers component count-reducing cost, board space, and component power requirements-making the MAX17030/MAX17036 MAX17030/MAX17036 ideal for high-power, cost-sensitive applications. The MAX17030/MAX17036 MAX17030/MAX17036 share the current between three phases that operate 120° out-of-phase, so the high-side MOSFETs never turn on simultaneously during normal operation. The instantaneous input current of each phase is effectively reduced, resulting in reduced input voltage ripple, ESR power loss, and RMS ripple current (see the Input Capacitor Selection section). Therefore, the same performance can be achieved with fewer or less-expensive input capacitors. +5V Bias Supply (VCC and VDD) The Quick-PWM controller requires an external +5V bias supply in addition to the battery. Typically, this +5V bias supply is the notebook's 95% efficient +5V system supply. The +5V bias supply must provide VCC (PWM controller) and VDD (gate-drive power), so the maximum current drawn is: ( IBIAS = ICC + fSW Q G(LOW) + Q G(HIGH) ) where ICC is provided in the Electrical Characteristics table, fSW is the switching frequency, and QG(LOW) and Q G(HIGH) are the MOSFET data sheet's total gatecharge specification limits at VGS = 5V. 20 VIN and VDD can be connected together if the input power source is a fixed +4.5V to +5.5V supply. If the +5V bias supply is powered up prior to the battery supply, the enable signal (SHDN going from low to high) must be delayed until the battery voltage is present to ensure startup. Switching Frequency (TON) Connect a resistor (RTON) between TON and VIN to set the switching period TSW = 1/fSW, per phase: TSW = 16.26pF x (RTON + 6.5k) A 96.75k to 303.25k corresponds to switching periods of 167ns (600kHz) to 500ns (200kHz), respectively. High-frequency (600kHz) operation optimizes the application for the smallest component size, trading off efficiency due to higher switching losses. Low-frequency (200kHz) operation offers the best overall efficiency at the expense of component size and board space. TON Open-Circuit Protection The TON input includes open-circuit protection to avoid long, uncontrolled on-times that could result in an overvoltage condition on the output. The MAX17030/ MAX17030/ MAX17036 MAX17036 detect an open-circuit fault if the TON current drops below 10A for any reason-the TON resistor (RTON) is unpopulated, a high resistance value is used, the input voltage is low, etc. Under these conditions, the MAX17030/MAX17036 MAX17030/MAX17036 stop switching (DH and DL pulled low) and immediately set the fault latch. Toggle SHDN or cycle the VCC power supply below 0.5V to clear the fault latch and reactivate the controller. On-Time One-Shot The MAX17030/MAX17036 MAX17030/MAX17036 contain a fast, low-jitter, adjustable one-shot that sets the high-side MOSFETs on-time. It is shared among the three phases. The oneshot for the main phase varies the on-time in response to the input and feedback voltages. The main high-side switch on-time is inversely proportional to the input voltage as measured by the V+ input, and proportional to the feedback voltage (VFB): T ( V + 0.075V ) t ON = SW FB VIN The one-shot for the second phase and third phase varies the on-time in response to the input voltage and the difference between the main and the other inductor currents. Two identical transconductance amplifiers integrate the difference between the master and each slave's current-sense signals. The summed output is connected to an internal integrator for each masterslave pair, which serves as the input to the respective slave's high-side MOSFET TON timer. _ 1/2/3-Phase Quick-PWM IMVP-6.5 VID Controllers V + 0.075V t ON(SEC) = TSW CCI VIN V + 0.075V ICCIZ CCI 7 = TSW FB + TSW V VIN IN = (Main On-time) + ( Secondary Current Balance Correction) t where V CCI is the internal integrator node for each slave's current-balance integrator, and Z CCI is the effective impedance at that node. During phase overlap, t ON is calculated based on phase 1's on-time requirements, but reduced by 33% when operating with three phases. For a 3-phase regulator, each phase cannot be enabled until the other 2 phases have completed their on-time and the minimum off-times have expired. As such, the minimum period is limited by 3 x (t ON + tOFF(MIN). Maximum tON is dependent on minimum VIN and maximum output voltage: TSW(MIN) = NPH x (tON(MAX) + tOFF(MIN) including MOSFET, inductor, and PCB resistances; VCHG is the sum of the parasitic voltage drops in the inductor charge path, including high-side switch, inductor, and PCB resistances; and tON is the on-time as determined above. Current Sense The MAX17030/MAX17036 MAX17030/MAX17036 sense the output current of each phase allowing the use of current-sense resistors on inductor DCR as the current-sense element. Lowoffset amplifiers are used for current balance, voltagepositioning gain, and current limit. Using the DC resistance (RDCR) of the output inductor allows higher efficiency. The initial tolerance and temperature coefficient of the inductor's DCR must be accounted for in the output-voltage droop-error budget and current monitor. This current-sense method uses an RC filtering network to extract the current information from the output inductor (see Figure 4). The RC network should match the inductor's time constant (L/RDCR): R2 R CS = R R1 + R2 DCR and: R CS = L 1 1 + C EQ R1 R2 where: tON(MAX) = VFB(MAX)/VIN(MIN x TSW(MIN) so: TSW(MIN) = tOFF(MIN)/[1/NPH ­ VIN(MAX)/VIN(MIN)] Hence, for a 7V input and 1.1V output, 500kHz is the maximum switching frequency. Running at this limit is not desirable as there is no room to allow the regulator to make adjustments without triggering phase overlap. For a 3-phase, high-current application with minimum 8V input, the practical switching frequency is 300kHz. On-times translate only roughly to switching frequencies. The on-times guaranteed in the Electrical Characteristics are influenced by parasitics in the conduction paths and propagation delays. For loads above the critical conduction point, where the dead-time effect (LX flying high and conducting through the high-side FET body diode) is no longer a factor, the actual switching frequency (per phase) is: fSW = ( VOUT + VDIS ) t ON ( VIN + VDIS - VCHG ) where VDIS and VCHG are the sum of the parasitic voltage drops in the inductor discharge and charge paths, where RCS is the required current-sense resistance, and RDCR is the inductor's series DC resistance. Use the typical inductance and RDCR values provided by the inductor manufacturer. To minimize the currentsense error due to the current-sense inputs' bias current (ICSP_ and ICSN_), choose R1//R2 to be less than 2k and use the above equation to determine the sense capacitance (CEQ). Choose capacitors with 5% tolerance and resistors with 1% tolerance specifications. Temperature compensation is recommended for this current-sense method. See the Voltage Positioning and Loop Compensation section for detailed information. When using a current-sense resistor for accurate output-voltage positioning, the circuit requires a differential RC filter to eliminate the AC voltage step caused by the equivalent series inductance (L ESL ) of the currentsense resistor (see Figure 4). The ESL induced voltage step might affect the average current-sense voltage. The RC filter's time constant should match the LESL/ R SENSE time constant formed by the current-sense resistor's parasitic inductance: L ESL = C EQR EQ R SENSE _ 21 MAX17030/MAX17036 MAX17030/MAX17036 When the main and other phase current-sense signals (VCM = VCMP - VCMN and VCS = VCSP - VCSM) become unbalanced, the transconductance amplifiers adjust the other phase's on-time, which increases or decreases the phase inductor current until the current-sense signals are properly balanced: MAX17030/MAX17036 MAX17030/MAX17036 1/2/3-Phase Quick-PWM IMVP-6.5 VID Controllers INPUT (VIN) CIN NH DH_ SENSE RESISTOR LX_ LESL L MAX17030 MAX17030 DL_ MAX17036 MAX17036 NL RSENSE COUT DL REQ CEQREQ = LESL RSENSE CEQ CSP_ CSN_ A) OUTPUT SERIES RESISTOR SENSING INPUT (VIN) CIN NH DH_ INDUCTOR LX_ L RDCR RCS = MAX17030 MAX17030 DL_ MAX17036 MAX17036 NL DL COUT R1 R2 RDCR R1 + R2 R2 RDCR = [ L 1 1 + CEQ R1 R2 ] CEQ CSP_ CSN_ B) LOSSLESS INDUCTOR SENSING FOR THERMAL COMPENSATION: R2 SHOULD CONSIST OF AN NTC RESISTOR IN SERIES WITH A STANDARD THIN-FILM RESISTOR Figure 4. Current-Sense Methods where LESL is the equivalent series inductance of the current-sense resistor, RSENSE is current-sense resistance value, and CEQ and REQ are the time-constant matching components. Current Balance The MAX17030/MAX17036 MAX17030/MAX17036 integrate the difference between the current-sense voltages and adjust the ontime of the secondary phase to maintain current balance. The current balance relies on the accuracy of the current-sense signals across the current-sense resistor or inductor DCR. With active current balancing, the current mismatch is determined by the current-sense resistor or inductor DCR values and the offset voltage of the transconductance amplifiers: 22 IOS(IBAL) = ILMAIN - ILSEC = VOS(IBAL) R SENSE where R SENSE = R CM = R CS and V OS(IBAL) is the current balance offset specification in the Electrical Characteristics table. The worst-case current mismatch occurs immediately after a load transient due to inductor value mismatches resulting in different di/dt for the two phases. The time it takes the current-balance loop to correct the transient imbalance depends on the mismatch between the inductor values and switching frequency. _ 1/2/3-Phase Quick-PWM IMVP-6.5 VID Controllers Feedback Adjustment Amplifiers Voltage-Positioning Amplifier (Steady-State Droop) The MAX17030/MAX17036 MAX17030/MAX17036 include a transconductance amplifier for adding gain to the voltage-positioning sense path. The amplifier's input is generated by summing the current-sense inputs, which differentially sense the voltage across either current-sense resistors or the inductor's DCR. The amplifier's output connects directly to the regulator's voltage-positioned feedback input (FB), so the resistance between FB and the output-voltage sense point determines the voltage-positioning gain: VOUT = VTARGET - R FBIFB where the target voltage (VTARGET) is defined in the Nominal Output Voltage Selection section, and the FB amplifier's output current (IFB) is determined by the sum of the current-sense voltages: PH IFB = Gm(FB) VCSX X =1 where VCSX = VCSP - VCSN is the differential currentsense voltage, and G m(FB) is typically 400S as defined in the Electrical Characteristics. Differential Remote Sense The MAX17030/MAX17036 MAX17030/MAX17036 include differential, remotesense inputs to eliminate the effects of voltage drops along the PCB traces and through the processor's power pins. The feedback-sense node connects to the voltage-positioning resistor (RFB). The ground-sense (GNDS) input connects to an amplifier that adds an offset directly to the target voltage, effectively adjusting the output voltage to counteract the voltage drop in the ground path. Connect the voltage-positioning resistor (RFB) and ground sense (GNDS) input directly to the processor's remote sense outputs as shown in Figure 1. Integrator Amplifier An internal integrator amplifier forces the DC average of the FB voltage to equal the target voltage, allowing accurate DC output-voltage regulation regardless of the output ripple voltage. The MAX17030/MAX17036 MAX17030/MAX17036 disable the integrator by connecting the amplifier inputs together at the beginning of all VID transitions done in pulse-skipping mode (DPRSLPVR = high). The integrator remains disabled until 20s after the transition is completed (the internal target settles) and the output is in regulation (edge detected on the error comparator). Transient Overlap Operation When a transient occurs, the response time of the controller depends on how quickly it can slew the inductor current. Multiphase controllers that remain 120° out-ofphase when a transient occurs actually respond slower than an equivalent single-phase controller. In order to provide fast transient response, the MAX17030/ MAX17030/ MAX17036 MAX17036 support a phase overlap mode, which allows the triple regulators to operate in-phase when heavy load transients are detected, effectively reducing the response time. After any high-side MOSFET turns off, if the output voltage does not exceed the regulation voltage when the minimum off-time expires, the controller simultaneously turns on all high-side MOSFETs with the same on-time during the next on-time cycle. The phases remain overlapped until the output voltage exceeds the regulation voltage after the minimum _ 23 MAX17030/MAX17036 MAX17030/MAX17036 Current Limit The current-limit circuit employs a unique "valley" current-sensing algorithm that senses the voltage across the current-sense resistors or inductor DCR at the current-sense inputs (CSP_ to CSN_). If the current-sense signal of the selected phase is above the current-limit threshold, the PWM controller does not initiate a new cycle until the inductor current of the selected phase drops below the valley current-limit threshold. When any one phase exceeds the current limit, all phases are effectively current limited since the interleaved controller does not initiate a cycle with the next phase. Since only the valley current is actively limited, the actual peak current is greater than the current-limit threshold by an amount equal to the inductor ripple current. Therefore, the exact current-limit characteristic and maximum load capability are a function of the currentsense resistance, inductor value, and battery voltage. The positive valley current-limit threshold voltage at CSP to CSN equals precisely 1/10 of the differential TIME to ILIM voltage over a 0.1V to 0.5V range (10mV to 50mV current-sense range). Connect ILIM directly to VCC to set the default current-limit threshold setting of 22.5mV (typ). The negative current-limit threshold (forced-PWM mode only) is nominally -125% of the corresponding valley current-limit threshold. When the inductor current drops below the negative current limit, the controller immediately activates an on-time pulse-DL turns off, and DH turns on-allowing the inductor current to remain above the negative current threshold. Carefully observe the PCB layout guidelines to ensure that noise and DC errors do not corrupt the current-sense signals seen by the current-sense inputs (CSP_, CSN_). MAX17030/MAX17036 MAX17030/MAX17036 1/2/3-Phase Quick-PWM IMVP-6.5 VID Controllers off-time expires. The on-time for each phase is based on the input voltage to FB ratio (i.e., follows the master on-time), but reduced by 33% in a 3-phase configuration, and not reduced in a 2-phase configuration. This maximizes the total inductor current slew rate. After the phase-overlap mode ends, the controller automatically begins with the next phase. For example, if phase 2 provided the last on-time pulse before overlap operation began, the controller starts switching with phase 3 when overlap operation ends. Nominal Output Voltage Selection The nominal no-load output voltage (V TARGET ) is defined by the selected voltage reference (VID DAC) plus the remote ground-sense adjustment (VGNDS) as defined in the following equation: VTARGET = VFB = VDAC + VGNDS where VDAC is the selected VID voltage. On startup, the MAX17030/MAX17036 MAX17030/MAX17036 slew the target voltage from ground to the preset boot voltage. Table 3 is the operating mode truth table. DAC Inputs (D0­D6) The digital-to-analog converter (DAC) programs the output voltage using the D0­D6 inputs. D0­D6 are low-voltage (1.0V) logic inputs, designed to interface directly with the CPU. Do not leave D0­D6 unconnected. Changing D0­D6 initiates a transition to a new output-voltage level. Change D0­D6 together, avoiding greater than 20ns skew between bits. Otherwise, incorrect DAC readings might cause a partial transition to the wrong voltage level followed by the intended transition to the correct voltage level, lengthening the overall transition time. The available DAC codes and resulting output voltages are compatible with the IMVP-6.5 (Table 4) specifications. OFF Code VID = 1111111 is defined as an OFF code. When the OFF code is set, the MAX17030/MAX17036 MAX17030/MAX17036 go through the same shutdown sequence as though SHDN has been pulled low-output discharged to zero, CLKEN high, and PWRGD low. Only the IC supply currents remain at the operating levels rather than the shutdown level. When exiting from the OFF code, the MAX17030/ MAX17030/ MAX17036 MAX17036 go through the boot sequence, similar to the sequence when SHDN is first pulled high. Table 3. Operating Mode Truth Table INPUTS SHDN DPRSLPVR PSI PHASE OPERATION* GND X X Disabled OPERATING MODE Low-Power Shutdown Mode. DL1 and DL2 forced low, and the controller is disabled. The supply current drops to 1A (max). Startup/Boot. When SHDN is pulled high, the MAX17030/ MAX17030/ Multiphase Pulse Skipping MAX17036 MAX17036 begin the startup sequence. Once the REF is above 1.84V, the controller enables the PWM controller and ramps the output 1/4 RTIME Slew Rate voltage up to the boot voltage. See Figure 9. Rising X X High Low High Multiphase Forced-PWM Nominal RTIME Slew Rate Full Power. The no-load output voltage is determined by the selected VID DAC code (D0­D6, Table 4). Low (N-1)-Phase Forced-PWM Nominal RTIME Slew Rate Intermediate Power. The no-load output voltage is determined by the selected VID DAC code (D0­D6, Table 4). When PSI is pulled low, the MAX17030/MAX17036 MAX17030/MAX17036 immediately disable phase 3, PWM3 is threestate, and DRSKP is low. 1-Phase Pulse Skipping Nominal RTIME Slew Rate Deeper Sleep Mode. The no-load output voltage is determined by the selected VID DAC code (D0­D6, Table 4). When DPRSLPVR is pulled high, the MAX17030/MAX17036 MAX17030/MAX17036 immediately enter 1-phase pulseskipping operation allowing automatic PWM/PFM switchover under light loads. The PWRGD and CLKEN upper thresholds are blanked. DH2 and DL2 are pulled low, PWM3 is three-state and DRSKP is low. High High Low High X *Multiphase operation = All enabled phases active. 24 _ 1/2/3-Phase Quick-PWM IMVP-6.5 VID Controllers INPUTS SHDN Falling X High PHASE OPERATION* X X OPERATING MODE Multiphase Forced-PWM 1/4 RTIME Slew Rate PSI DPRSLPVR Shutdown. When SHDN is pulled low, the MAX17030/MAX17036 MAX17030/MAX17036 immediately pull PWRGD low, CLKEN becomes high impedance, all enabled phases are activated, and the output voltage is ramped down to 12.5mV; then DH and DL are pulled low and CSN1 discharge FET is turned on. X Fault Mode. The fault latch has been set by the MAX17030/MAX17036 MAX17030/MAX17036 UVP or thermal-shutdown protection, or by the OVP protection. The controller remains in fault mode until VCC power is cycled or SHDN toggled. Disabled *Multiphase operation = All enabled phases active. Table 4. IMVP-6.5 Output Voltage VID DAC Codes D6 D5 D4 D3 D2 D1 D0 OUTPUT VOLTAGE (V) D6 D5 D4 D3 D2 D1 D0 OUTPUT VOLTAGE (V) 0 0 0 0 0 0 0 1.5000 1 0 0 0 0 0 0 0.7000 0 0 0 0 0 0 1 1.4875 1 0 0 0 0 0 1 0.6875 0 0 0 0 0 1 0 1.4750 1 0 0 0 0 1 0 0.6750 0 0 0 0 0 1 1 1.4625 1 0 0 0 0 1 1 0.6625 0 0 0 0 1 0 0 1.4500 1 0 0 0 1 0 0 0.6500 0 0 0 0 1 0 1 1.4375 1 0 0 0 1 0 1 0.6375 0 0 0 0 1 1 0 1.4250 1 0 0 0 1 1 0 0.6250 0 0 0 0 1 1 1 1.4125 1 0 0 0 1 1 1 0.6125 0 0 0 1 0 0 0 1.4000 1 0 0 1 0 0 0 0.6000 0 0 0 1 0 0 1 1.3875 1 0 0 1 0 0 1 0.5875 0 0 0 1 0 1 0 1.3750 1 0 0 1 0 1 0 0.5750 0 0 0 1 0 1 1 1.3625 1 0 0 1 0 1 1 0.5625 0 0 0 1 1 0 0 1.3500 1 0 0 1 1 0 0 0.5500 0 0 0 1 1 0 1 1.3375 1 0 0 1 1 0 1 0.5375 0 0 0 1 1 1 0 1.3250 1 0 0 1 1 1 0 0.5250 0 0 0 1 1 1 1 1.3125 1 0 0 1 1 1 1 0.5125 0 0 1 0 0 0 0 1.3000 1 0 1 0 0 0 0 0.5000 0 0 1 0 0 0 1 1.2875 1 0 1 0 0 0 1 0.4875 0 0 1 0 0 1 0 1.2750 1 0 1 0 0 1 0 0.4750 0 0 1 0 0 1 1 1.2625 1 0 1 0 0 1 1 0.4625 0 0 1 0 1 0 0 1.2500 1 0 1 0 1 0 0 0.4500 0 0 1 0 1 0 1 1.2375 1 0 1 0 1 0 1 0.4375 0 0 1 0 1 1 0 1.2250 1 0 1 0 1 1 0 0.4250 0 0 1 0 1 1 1 1.2125 1 0 1 0 1 1 1 0.4125 0 0 1 1 0 0 0 1.2000 1 0 1 1 0 0 0 0.4000 0 0 1 1 0 0 1 1.1875 1 0 1 1 0 0 1 0.3875 _ 25 MAX17030/MAX17036 MAX17030/MAX17036 Table 3. Operating Mode Truth Table (continued) MAX17030/MAX17036 MAX17030/MAX17036 1/2/3-Phase Quick-PWM IMVP-6.5 VID Controllers Table 4. IMVP-6.5 Output Voltage VID DAC Codes (continued) D6 D5 D4 D3 D2 D1 D0 OUTPUT VOLTAGE (V) D6 D5 D4 D3 D2 D1 D0 OUTPUT VOLTAGE (V) 0 0 1 1 0 1 0 1.1750 1 0 1 1 0 1 0 0.3750 0 0 1 1 0 1 1 1.1625 1 0 1 1 0 1 1 0.3625 0 0 1 1 1 0 0 1.1500 1 0 1 1 1 0 0 0.3500 0 0 1 1 1 0 1 1.1375 1 0 1 1 1 0 1 0.3375 0 0 1 1 1 1 0 1.1250 1 0 1 1 1 1 0 0.3250 0 0 1 1 1 1 1 1.1125 1 0 1 1 1 1 1 0.3125 0 1 0 0 0 0 0 1.1000 1 1 0 0 0 0 0 0.3000 0 1 0 0 0 0 1 1.0875 1 1 0 0 0 0 1 0.2875 0 1 0 0 0 1 0 1.0750 1 1 0 0 0 1 0 0.2750 0 1 0 0 0 1 1 1.0625 1 1 0 0 0 1 1 0.2625 0 1 0 0 1 0 0 1.0500 1 1 0 0 1 0 0 0.2500 0 1 0 0 1 0 1 1.0375 1 1 0 0 1 0 1 0.2375 0 1 0 0 1 1 0 1.0250 1 1 0 0 1 1 0 0.2250 0 1 0 0 1 1 1 1.0125 1 1 0 0 1 1 1 0.2125 0 1 0 1 0 0 0 1.0000 1 1 0 1 0 0 0 0.2000 0 1 0 1 0 0 1 0.9875 1 1 0 1 0 0 1 0.1875 0 1 0 1 0 1 0 0.9750 1 1 0 1 0 1 0 0.1750 0 1 0 1 0 1 1 0.9625 1 1 0 1 0 1 1 0.1625 0 1 0 1 1 0 0 0.9500 1 1 0 1 1 0 0 0.1500 0 1 0 1 1 0 1 0.9375 1 1 0 1 1 0 1 0.1375 0 1 0 1 1 1 0 0.9250 1 1 0 1 1 1 0 0.1250 0 1 0 1 1 1 1 0.9125 1 1 0 1 1 1 1 0.1125 0 1 1 0 0 0 0 0.9000 1 1 1 0 0 0 0 0.1000 0 1 1 0 0 0 1 0.8875 1 1 1 0 0 0 1 0.0875 0 1 1 0 0 1 0 0.8750 1 1 1 0 0 1 0 0.0750 0 1 1 0 0 1 1 0.8625 1 1 1 0 0 1 1 0.0625 0 1 1 0 1 0 0 0.8500 1 1 1 0 1 0 0 0.0500 0 1 1 0 1 0 1 0.8375 1 1 1 0 1 0 1 0.0375 0 1 1 0 1 1 0 0.8250 1 1 1 0 1 1 0 0.0250 0 1 1 0 1 1 1 0.8125 1 1 1 0 1 1 1 0.0125 0 1 1 1 0 0 0 0.8000 1 1 1 1 0 0 0 0 0 1 1 1 0 0 1 0.7875 1 1 1 1 0 0 1 0 0 1 1 1 0 1 0 0.7750 1 1 1 1 0 1 0 0 0 1 1 1 0 1 1 0.7625 1 1 1 1 0 1 1 0 0 1 1 1 1 0 0 0.7500 1 1 1 1 1 0 0 0 0 1 1 1 1 0 1 0.7375 1 1 1 1 1 0 1 0 0 1 1 1 1 1 0 0.7250 1 1 1 1 1 1 0 0 0 1 1 1 1 1 1 0.7125 1 1 1 1 1 1 1 Off 26 _ 1/2/3-Phase Quick-PWM IMVP-6.5 VID Controllers Output-Voltage-Transition Timing At the beginning of an output-voltage transition, the MAX17030/MAX17036 MAX17030/MAX17036 blank both PWRGD thresholds, preventing the PWRGD open-drain output from changing states during the transition. The controller enables the lower PWRGD threshold approximately 20s after the slew-rate controller reaches the target output voltage, but the upper PWRGD threshold is enabled only if the controller remains in forced-PWM operation. If the controller enters pulse-skipping operation, the upper PWRGD threshold remains blanked. The slew rate (set by resistor RTIME) must be set fast enough to ensure that the transition can be completed within the maximum allotted time. The MAX17030/MAX17036 MAX17030/MAX17036 automatically control the current to the minimum level required to complete the transition. The total transition time depends on RTIME, the voltage difference, and the accuracy of the slew-rate controller (CSLEW accuracy). The slew rate is not dependent on the total output capacitance, as long as the surge current is less than the current limit. For all dynamic VID transitions, the transition time (tTRAN) is given by: t TRAN = VNEW - VOLD (dVTARGET dt ) where dVTARGET/dt = 12.5mV/s × 71.5k/RTIME is the slew rate, VOLD is the original output voltage, and VNEW is the new target voltage. See TIME Slew-Rate Accuracy in the Electrical Characteristics for slew-rate limits. For soft-start and shutdown, the controller automatically reduces the slew rate to 1/4. The average inductor current per phase required to make an output-voltage transition is: IL C OUT × (dVTARGET dt ) TOTAL where dVTARGET/dt is the required slew rate, COUT is the total output capacitance, and TOTAL is the number of active phases. Deeper Sleep Transitions When DPRSLPVR goes high, the MAX17030/MAX17036 MAX17030/MAX17036 immediately disable phases 2 and 3 (DH2, DL2 forced low, PWM3 three-state, DRSKP low), and enter pulseskipping operation (see Figures 5 and 6). If the VIDs are set to a lower voltage setting, the output drops at a rate determined by the load and the output capacitance. The internal target still ramps as before, and PWRGD remains blanked high impedance until 20s after the output voltage reaches the internal target. Once this time expires, PWRGD monitors only the lower threshold: · Fast C4E Deeper Sleep Exit: When exiting deeper sleep (DPRSLPVR pulled low) while the output voltage still exceeds the deeper sleep voltage, the MAX17030/MAX17036 MAX17030/MAX17036 quickly slew (50mV/s min regardless of RTIME setting) the internal target voltage to the DAC code provided by the processor as long as the output voltage is above the new target. The controller remains in skip mode until the output voltage equals the internal target. Once the internal target reaches the output voltage, phase 2 is enabled. The controller blanks PWRGD and CLKEN (forced high impedance) until 20s after the transition is completed. See Figure 5. · Standard C4 Deeper Sleep Exit: When exiting deeper sleep (DPRSLPVR pulled low) while the output voltage is regulating to the deeper sleep voltage, the MAX17030/MAX17036 MAX17030/MAX17036 immediately activate all enabled phases and ramp the output voltage to the LFM DAC code provided by the processor at the slew rate set by RTIME. The controller blanks PWRGD and CLKEN (forced high impedance) until 20s after the transition is completed. See Figure 6. _ 27 MAX17030/MAX17036 MAX17030/MAX17036 Suspend Mode When the processor enters low-power deeper sleep mode, the IMVP-6.5 CPU sets the VID DAC code to a lower output voltage and drives DPRSLPVR high. The MAX17030/MAX17036 MAX17030/MAX17036 respond by slewing the internal target voltage to the new DAC code, switching to singlephase operation, and letting the output voltage gradually drift down to the deeper sleep voltage. During the transition, the MAX17030/MAX17036 MAX17030/MAX17036 blank both the upper and lower PWRGD and CLKEN thresholds until 20s after the internal target reaches the deeper sleep voltage. Once the 20s timer expires, the MAX17030/ MAX17030/ MAX17036 MAX17036 reenable the lower PWRGD and CLKEN threshold, but keep the upper threshold blanked. MAX17030/MAX17036 MAX17030/MAX17036 1/2/3-Phase Quick-PWM IMVP-6.5 VID Controllers ACTUAL VOUT CPU CORE VOLTAGE INTERNAL TARGET VID (D0­D6) DEEPER SLEEP VID DPRSLPVR PSI INTERNAL PWM CONTROL DO NOT CARE (DPRSLPVR DOMINATES STATE) 1-PHASE SKIP (DH1 ACTIVE, DH2, DL2 FORCED LOW, PWM3 THREE-STATE) DH1 FORCED-PWM NO PULSES: VOUT > VTARGET DH2 PWM3 PWRGD BLANK HIGH-Z BLANK HIGH THRESHOLD ONLY BLANK HI-Z CLKEN BLANK LOW BLANK HIGH THRESHOLD ONLY BLANK LO SET TO 1.5V MIN OVP TRACKS INTERNAL TARGET tBLANK 20s typ tBLANK 20s typ Figure 5. C4E (C4 Early Exit) Transition ACTIVE VID CPU CORE VOLTAGE ACTUAL VOUT INTERNAL TARGET VID (D0­D6) DEEPER SLEEP VID LFM VID DPRSLP VID LFM VID DPRSLPVR DO NOT CARE (DPRSLPVR DOMINATES STATE) PSI INTERNAL PWM CONTROL FORCED-PWM 1-PHASE SKIP (DH1 ACTIVE, DH2, DL2 FORCED LOW, PWM3 THREE-STATE) DH1 NO PULSES: VOUT > VTARGET DH2 PWM3 PWRGD CLKEN OVP BLANK HIGH-Z BLANK HIGH THRESHOLD ONLY BLANK HIGH-Z BLANK LOW BLANK HIGH THRESHOLD ONLY BLANK LOW SET TO 1.5V MIN tBLANK 20s TYP TRACKS INTERNAL TARGET tBLANK 20s TYP Figure 6. Standard C4 Transition 28 _ 1/2/3-Phase Quick-PWM IMVP-6.5 VID Controllers Forced-PWM Operation (Normal Mode) During soft-shutdown and normal operation-when the CPU is actively running (DPRSLPVR = low, Table 5)- the MAX17030/MAX17036 MAX17030/MAX17036 operate with the low-noise, forced-PWM control scheme. Forced-PWM operation disables the zero-crossing comparators of all active phases, forcing the low-side gate-drive waveforms to constantly be the complement of the high-side gatedrive waveforms. This keeps the switching frequency constant and allows the inductor current to reverse under light loads, providing fast, accurate negative output-voltage transitions by quickly discharging the output capacitors. Forced-PWM operation comes at a cost: the no-load +5V bias supply current remains between 10mA to 50mA per phase, depending on the external MOSFETs and switching frequency. To maintain high efficiency under light-load conditions, the processor can switch the controller to a low-power pulse-skipping control scheme by entering suspend mode. PSI determines how many phases are active when operating in forced-PWM mode (DPRSLPVR = low). When PSI is pulled low, phases 1 and 2 remain active but phase 3 is disabled (PWM3 three-state, DRSKP forced low). Light-Load Pulse-Skipping Operation (Deeper Sleep) During soft-start and normal operation when DPRSLPVR is pulled high, the MAX17030/MAX17036 MAX17030/MAX17036 operate with a single-phase pulse-skipping mode. The pulse-skipping mode enables the driver's zero-crossing comparator, so the controller pulls DL1 low when its current-sense inputs detect "zero" inductor current. This keeps the inductor from discharging the output capacitors and forces the controller to skip pulses under lightload conditions to avoid overcharging the output. CPU FREQ CPU LOAD VID (D0­D6) CPU CORE VOLTAGE PSI DH1 DH2 PWM3 THREE-STATE PWM3 PWRGD CLKEN BLANK HIGH-Z BLANK HIGH-Z BLANK LOW BLANK LOW 180° OUT-OF-PHASE tBLANK 20s typ tBLANK 20s typ Figure 7. PSI Transition _ 29 MAX17030/MAX17036 MAX17030/MAX17036 PSI Transitions When PSI is pulled low, the MAX17030/MAX17036 MAX17030/MAX17036 immediately disable phase 3 (PWM3 three-state, DRSKP forced low) and enter 2-phase PWM operation (see Figure 7). When PSI is pulled high, the MAX17030/ MAX17030/ MAX17036 MAX17036 enable phase 3. When pulse-skipping, the controller blanks the upper PWRGD and CLKEN thresholds. Upon entering pulseskipping operation, the controller temporarily sets the OVP threshold to 1.5V, preventing false OVP faults when the transition to pulse-skipping operation coincides with a VID code change. Once the error amplifier detects that the output voltage is in regulation, the OVP threshold tracks the selected VID DAC code. The MAX17030/MAX17036 MAX17030/MAX17036 automatically use forced-PWM operation during soft-start and soft shutdown, regardless of the DPRSLPVR and PSI configuration. Automatic Pulse-Skipping Switchover In skip mode (DPRSLPVR = high), an inherent automatic switchover to PFM takes place at light loads (Figure 8). This switchover is affected by a comparator that truncates the low-side switch on-time at the inductor current's zero crossing. The zero-crossing comparator senses the inductor current across the low-side MOSFETs. Once VLX drops below the zero-crossing comparator threshold (see the Electrical Characteristics), the comparator forces DL low. This mechanism causes the threshold between pulse-skipping PFM and nonskipping PWM operation to coincide with the boundary between continuous and discontinuous inductor-current operation. The PFM/PWM crossover occurs when the load current of each phase is equal to 1/2 the peak-topeak ripple current, which is a function of the inductor value (Figure 8). For a battery input range of 7V to 20V, this threshold is relatively constant, with only a minor dependence on the input voltage due to the typically low duty cycles. The total load-current at the PFM/PWM crossover threshold (ILOAD(SKIP) is approximately: T V V - VOUT ILOAD(SKIP) = SW OUT IN 2 × VIN L Power-Up Sequence (POR, UVLO) The MAX17030/MAX17036 MAX17030/MAX17036 are enabled when SHDN is driven high (Figure 9). The reference powers up first. Once the reference exceeds its undervoltage-lockout (UVLO) threshold, the internal analog blocks are turned on and masked by a 150s one-shot delay. The PWM controller then begins switching. V ­ VOUT I = IN t L INDUCTOR CURRENT MAX17030/MAX17036 MAX17030/MAX17036 1/2/3-Phase Quick-PWM IMVP-6.5 VID Controllers IPEAK ILOAD = IPEAK/2 0 ON-TIME TIME Figure 8. Pulse-Skipping/Discontinuous Crossover Point VCC SHDN VID (D0­D6) IGNORE VID IGNORE VID SOFT-START 1/4 SLEW RATE SET BY RTIME SOFT-SHUTDOWN 1/4 SLEW RATE SET BY RTIME VCORE INTERNAL PWM CONTROL PULSE-SKIPPING FORCED-PWM CLKEN IMVPOK tBLANK 60s TYP tBLANK 20s TYP tBLANK 5ms TYP tBLANK 20s TYP Figure 9. Power-Up and Shutdown Sequence Timing Diagram 30 _ 1/2/3-Phase Quick-PWM IMVP-6.5 VID Controllers t TRAN(START) = 4VBOOT (dVTARGET dt ) where dVTARGET/dt = 12.5mV/s x 71.5k/RTIME is the slew rate. The soft-start circuitry does not use a variable current limit, so full output current is available immediately. CLKEN is pulled low approximately 60s after the MAX17030/MAX17036 MAX17030/MAX17036 reach the boot voltage. At the same time, the MAX17030/MAX17036 MAX17030/MAX17036 slew the output to the voltage set at the VID inputs at the programmed slew rate. PWRGD becomes high impedance approximately 5ms after CLKEN is pulled low. The MAX17030/ MAX17030/ MAX17036 MAX17036 automatically operate in pulse-skipping mode during soft-start, and use forced-PWM operation during soft-shutdown, regardless of the DPRSLPVR and PSI configuration. If the VCC voltage drops below 4.25V, the controller assumes that there is not enough supply voltage to make valid decisions, and shuts down immediately. DH and DL are forced low, and CSN1 10 discharge FET is enabled. Shutdown When SHDN goes low, the MAX17030/MAX17036 MAX17030/MAX17036 enters low-power shutdown mode. PWRGD is pulled low immediately, and the output voltage ramps down at 1/4 the slew rate set by RTIME: t TRAN(SHDN) = 4VOUT (dVTARGET dt ) where dVTARGET/dt = 12.5mV/s x 71.5k/RTIME is the slew rate. After the output voltage drops to 12.5mV, the MAX17030/MAX17036 MAX17030/MAX17036 shut down completely-the drivers are disabled (DL1 and DL2 driven low, PWM3 is three-state, and DRSKP low), the reference turns off, 10 CSN1 discharge FET is turned on, and the supply current drops below 1A. When an undervoltage fault condition activates the shutdown sequence, the protection circuitry sets the fault latch to prevent the controller from restarting. To clear the fault latch and reactivate the controller, toggle SHDN or cycle VCC power below 0.5V. Current Monitor (IMON) The MAX17030/MAX17036 MAX17030/MAX17036 include a unidirectional transconductance amplifier that sources current proportional to the positive current-sense voltage. The IMON output current is defined by: IIMON = Gm(IMON) x (VCSP - VCSN) where Gm(IMON) = 1.6mS (typ) and the IMON current is unidirectional (sources current out of IMON only) for positive current-sense values. For negative currentsense voltages, the IMON current is zero. Connect an external resistor between IMON and GNDS to create the desired IMON gain based on the following equation: RIMON = 0.9V/(IMAX x RSENSE(MIN) x Gm(IMON_MIN) where IMAX is defined in the Current Monitor section of the Intel IMVP-6.5 specification and based on discrete increments (10A, 20A, 30A, 40A, etc.), RSENSE(MIN) is the minimum effective value of the current-sense element (sense resistor or inductor DCR) that is used to provide the current-sense voltage, and Gm(IMON_MIN) is the minimum transconductance amplifier gain as defined in the Electrical Characteristics. The IMON voltage is internally clamped to a maximum of 1.1V (typ), preventing the IMON output from exceeding the IMON voltage rating even under overload or short-circuit conditions. When the controller is disabled, IMON is pulled to ground. The transconductance amplifier and voltage clamp are internally compensated, so IMON cannot directly drive large capacitance values. To filter the IMON signal, use an RC filter as shown in Figure 1. Temperature Comparator (VRHOT) The MAX17030/MAX17036 MAX17030/MAX17036 also feature an independent comparator with an accurate threshold (V HOT ) that tracks the analog supply voltage (VHOT = 0.3VCC). This makes the thermal trip threshold independent of the VCC supply voltage tolerance. Use a resistor- and thermistordivider between VCC and GND to generate a voltageregulator overtemperature monitor. Place the thermistor as close to the MOSFETs and inductors as possible. Fault Protection (Latched) Output Overvoltage Protection The overvoltage-protection (OVP) circuit is designed to protect the CPU against a shorted high-side MOSFET by drawing high current and blowing the battery fuse. The MAX17030/MAX17036 MAX17030/MAX17036 continuously monitor the output for an overvoltage fault. An OVP fault is detected if the output voltage exceeds the set VID DAC voltage by more than 300mV, or the fixed 1.5V (typ) threshold _ 31 MAX17030/MAX17036 MAX17030/MAX17036 Power-on reset (POR) occurs when VCC rises above approximately 2V, resetting the fault latch and preparing the controller for operation. The VCC UVLO circuitry inhibits switching until VCC rises above 4.25V. The controller powers up the reference once the system enables the controller, VCC is above 4.25V, and SHDN driven high. With the reference in regulation, the controller ramps the output voltage to the boot voltage (1.1V) at 1/4 the slew rate set by RTIME: MAX17030/MAX17036 MAX17030/MAX17036 1/2/3-Phase Quick-PWM IMVP-6.5 VID Controllers during a downward VID transition in skip mode. During pulse-skipping operation (DPRSLPVR = high), the OVP threshold tracks the VID DAC voltage as soon as the output is in regulation; otherwise, the fixed 1.5V (typ) threshold is used. When the OVP circuit detects an overvoltage fault while in multiphase mode (DPRSLPVR = low, PSI = high), the MAX17030/MAX17036 MAX17030/MAX17036 immediately force DL1 and DL2 high, PWM3 low, and DRSKP high; and pull DH1 and DH2 low. This action turns on the synchronous-rectifier MOSFETs with 100% duty and, in turn, rapidly discharges the output filter capacitor and forces the output low. If the condition that caused the overvoltage (such as a shorted high-side MOSFET) persists, the battery fuse blows. Toggle SHDN or cycle the VCC power supply below 0.5V to clear the fault latch and reactivate the controller. When an overvoltage fault occurs while in 1-phase operation (DPRSLPVR = high, or PSI = low), the MAX17030/MAX17036 MAX17030/MAX17036 immediately force DL1 high and pull DH1 low. DL2 and DH2 remain low as phase 2 was disabled. DL2 does not react. Overvoltage protection can be disabled through the nofault test mode (see the No-Fault Test Mode section). Output Undervoltage Protection If the MAX17030/MAX17036 MAX17030/MAX17036 output voltage is 400mV below the target voltage, the controller activates the shutdown sequence and sets the fault latch. Once the output voltage ramps down to 12.5mV, it forces the DL1 and DL2 low and pulls DH1 and DH2 low, three-states PWM3, and sets DRSKP low 10 CSN1 discharge FET is turned on. Toggle SHDN or cycle the VCC power supply below 0.5V to clear the fault latch and reactivate the controller. UVP can be disabled through the no-fault test mode (see the No-Fault Test Mode section). Thermal-Fault Protection The MAX17030/MAX17036 MAX17030/MAX17036 feature a thermal fault-protection circuit. When the junction temperature rises above +160°C, a thermal sensor sets the fault latch and forces the DL1 and DL2 low and pulls DH1 and DH2 low, three-states PWM3, sets DRSKP low, and enables 10 CSN1 discharge FET on. Toggle SHDN or cycle the VCC power supply below 0.5V to clear the fault latch and reactivate the controller after the junction temperature cools by 15°C. Thermal shutdown can be disabled through the no-fault test mode (see the No-Fault Test Mode section). 32 No-Fault Test Mode The latched fault-protection features can complicate the process of debugging prototype breadboards since there are (at most) a few milliseconds in which to determine what went wrong. Therefore, a "no-fault" test mode is provided to disable the fault protection-overvoltage protection, undervoltage protection, and thermal shutdown. Additionally, the test mode clears the fault latch if it has been set. The no-fault test mode is entered by forcing 11V to 13V on SHDN. MOSFET Gate Drivers The DH and DL drivers are optimized for driving moderate-sized high-side and larger low-side power MOSFETs. This is consistent with the low duty factor seen in notebook applications, where a large V IN VOUT differential exists. The high-side gate drivers (DH) source 2.7A and sink 2.2A, and the low-side gate drivers (DL) source 2.7A and sink 8A. This ensures robust gate drive for high-current applications. The DH_ floating high-side MOSFET drivers are powered by internal boost switch charge pumps at BST_, while the DL_ synchronous-rectifier drivers are powered directly by the 5V bias supply (VDD). Adaptive dead-time circuits monitor the DL and DH drivers and prevent either FET from turning on until the other is fully off. The adaptive driver dead time allows operation without shoot-through with a wide range of MOSFETs, minimizing delays and maintaining efficiency. A low-resistance, low-inductance path from the DL and DH drivers to the MOSFET gates is required for the adaptive dead-time circuits to work properly; otherwise, the sense circuitry in the MAX17030/MAX17036 MAX17030/MAX17036 interprets the MOSFET gates as "off" while charge actually remains. Use very short, wide traces (50 mils to 100 mils wide if the